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change(csi): changed the clk_freq_hz to lane_bit_rate_mbps

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Armando 2024-03-26 16:00:11 +08:00
parent 699f3e1245
commit 8cef97beac
5 changed files with 7 additions and 5 deletions
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2
components/esp_driver_cam/csi/include/esp_cam_ctlr_csi.h
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@ -29,7 +29,7 @@ typedef struct {
uint32_t h_res; ///< Input horizontal resolution, i.e. the number of pixels in a line uint32_t h_res; ///< Input horizontal resolution, i.e. the number of pixels in a line
uint32_t v_res; ///< Input vertical resolution, i.e. the number of lines in a frame uint32_t v_res; ///< Input vertical resolution, i.e. the number of lines in a frame
uint8_t data_lane_num; ///< Data lane num uint8_t data_lane_num; ///< Data lane num
int clk_freq_hz; ///< Frequency of CLK, in Hz. int lane_bit_rate_mbps; ///< Lane bit rate in Mbps
mipi_csi_color_t input_data_color_type; ///< Input color type mipi_csi_color_t input_data_color_type; ///< Input color type
mipi_csi_color_t output_data_color_type; ///< Output color type mipi_csi_color_t output_data_color_type; ///< Output color type
bool byte_swap_en; ///< Enable byte swap bool byte_swap_en; ///< Enable byte swap

2
components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c
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@ -161,7 +161,7 @@ esp_err_t esp_cam_new_csi_ctlr(const esp_cam_ctlr_csi_config_t *config, esp_cam_
mipi_csi_hal_config_t hal_config; mipi_csi_hal_config_t hal_config;
hal_config.frame_height = config->h_res; hal_config.frame_height = config->h_res;
hal_config.frame_width = config->v_res; hal_config.frame_width = config->v_res;
hal_config.clk_freq_hz = config->clk_freq_hz; hal_config.lane_bit_rate_mbps = config->lane_bit_rate_mbps;
hal_config.lanes_num = config->data_lane_num; hal_config.lanes_num = config->data_lane_num;
hal_config.byte_swap_en = config->byte_swap_en; hal_config.byte_swap_en = config->byte_swap_en;
mipi_csi_hal_init(&ctlr->hal, &hal_config); mipi_csi_hal_init(&ctlr->hal, &hal_config);

2
components/esp_driver_cam/test_apps/csi/main/test_csi_driver.c
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@ -15,7 +15,7 @@ TEST_CASE("TEST CSI driver allocation", "[csi]")
.ctlr_id = 0, .ctlr_id = 0,
.h_res = 800, .h_res = 800,
.v_res = 640, .v_res = 640,
.clk_freq_hz = 200000000, .lane_bit_rate_mbps = 200,
.input_data_color_type = MIPI_CSI_COLOR_RAW8, .input_data_color_type = MIPI_CSI_COLOR_RAW8,
.output_data_color_type = MIPI_CSI_COLOR_RGB565, .output_data_color_type = MIPI_CSI_COLOR_RGB565,
.data_lane_num = 2, .data_lane_num = 2,

2
components/hal/include/hal/mipi_csi_hal.h
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@ -43,7 +43,7 @@ typedef struct {
uint32_t in_bpp; ///< In bits per pixel uint32_t in_bpp; ///< In bits per pixel
uint32_t out_bpp; ///< Out bits per pixel uint32_t out_bpp; ///< Out bits per pixel
bool byte_swap_en; ///< Enable byte swap bool byte_swap_en; ///< Enable byte swap
int clk_freq_hz; ///< Clock frequency in hz int lane_bit_rate_mbps; ///< Lane bit rate in Mbps
} mipi_csi_hal_config_t; } mipi_csi_hal_config_t;
/** /**

4
components/hal/mipi_csi_hal.c
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@ -9,6 +9,8 @@
#include "hal/mipi_csi_ll.h" #include "hal/mipi_csi_ll.h"
#include "soc/mipi_csi_periph.h" #include "soc/mipi_csi_periph.h"
#define MHZ (1000 * 1000)
void s_mipi_csi_hal_phy_write_register(mipi_csi_hal_context_t *hal, uint8_t reg_addr, uint8_t reg_val) void s_mipi_csi_hal_phy_write_register(mipi_csi_hal_context_t *hal, uint8_t reg_addr, uint8_t reg_val)
{ {
mipi_csi_phy_ll_write_clock(hal->host_dev, 0, false); mipi_csi_phy_ll_write_clock(hal->host_dev, 0, false);
@ -24,7 +26,7 @@ void mipi_csi_hal_init(mipi_csi_hal_context_t *hal, const mipi_csi_hal_config_t
{ {
hal->bridge_dev = MIPI_CSI_BRG_LL_GET_HW(0); hal->bridge_dev = MIPI_CSI_BRG_LL_GET_HW(0);
hal->host_dev = MIPI_CSI_HOST_LL_GET_HW(0); hal->host_dev = MIPI_CSI_HOST_LL_GET_HW(0);
int csi_lane_rate = config->clk_freq_hz; int csi_lane_rate = config->lane_bit_rate_mbps * MHZ;
// reset PHY // reset PHY
mipi_csi_phy_ll_enable_shutdown_input(hal->host_dev, true); mipi_csi_phy_ll_enable_shutdown_input(hal->host_dev, true);