alex/esp-idf
alex/esp-idf
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Merge branch 'feature/esp32s2beta_todos_to_warnings' into feature/esp32s2beta

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This commit is contained in:
suda-morris 2019-06-13 13:42:36 +08:00
commit 8cd58625d0
41 changed files with 90 additions and 337 deletions
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15
components/driver/CMakeLists.txt
View File

@ -1,16 +1,11 @@
set(COMPONENT_SRCS "can.c"
"gpio.c"
"i2c.c"
"i2s.c"
"ledc.c"
"mcpwm.c"
"pcnt.c"
"periph_ctrl.c"
"rmt.c"
"rtc_module.c"
"sdio_slave.c"
"sdmmc_host.c"
"sdmmc_transaction.c"
"sdspi_crc.c"
"sdspi_host.c"
"sdspi_transaction.c"
@ -20,6 +15,16 @@ set(COMPONENT_SRCS "can.c"
"spi_slave.c"
"timer.c"
"uart.c")
if(CONFIG_IDF_TARGET_ESP32)
# SDMMC and MCPWM are in ESP32 only, I2S not ported yet.
list(APPEND COMPONENT_SRCS "i2s.c"
"mcpwm.c"
"sdio_slave.c"
"sdmmc_host.c"
"sdmmc_transaction.c")
endif()
set(COMPONENT_ADD_INCLUDEDIRS "include")
set(COMPONENT_PRIV_INCLUDEDIRS "include/driver")
set(COMPONENT_REQUIRES esp_ringbuf soc) #cannot totally hide soc headers, since there are a lot arguments in the driver are chip-dependent

2
components/driver/i2s.c
View File

@ -36,7 +36,6 @@
#include "esp_pm.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
static const char* I2S_TAG = "I2S";
@ -1389,4 +1388,3 @@ int i2s_pop_sample(i2s_port_t i2s_num, void *sample, TickType_t ticks_to_wait)
return bytes_pop;
}
}
#endif

2
components/driver/mcpwm.c
View File

@ -25,7 +25,6 @@
#include "driver/periph_ctrl.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
static mcpwm_dev_t *MCPWM[2] = {&MCPWM0, &MCPWM1};
static const char *MCPWM_TAG = "MCPWM";
@ -730,4 +729,3 @@ esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *a
ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle);
return ret;
}
#endif

4
components/driver/sdmmc_host.c
View File

@ -25,7 +25,7 @@
#include "sdmmc_private.h"
#include "freertos/semphr.h"
#include "soc/sdmmc_periph.h"
#if CONFIG_IDF_TARGET_ESP32
#define SDMMC_EVENT_QUEUE_LENGTH 32
@ -635,4 +635,4 @@ esp_err_t sdmmc_host_pullup_en(int slot, int width)
}
return ESP_OK;
}
#endif

45
components/esp32s2beta/Makefile.projbuild
View File

@ -1,44 +1 @@
ifdef CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
PHY_INIT_DATA_OBJ = $(BUILD_DIR_BASE)/phy_init_data.o
PHY_INIT_DATA_BIN = $(BUILD_DIR_BASE)/phy_init_data.bin
# Command to flash PHY init data partition
PHY_INIT_DATA_FLASH_CMD = $(ESPTOOLPY_SERIAL) write_flash $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
ESPTOOL_ALL_FLASH_ARGS += $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
ESP32_COMPONENT_PATH := $(COMPONENT_PATH)
$(PHY_INIT_DATA_OBJ): $(ESP32_COMPONENT_PATH)/phy_init_data.h $(BUILD_DIR_BASE)/include/sdkconfig.h
$(summary) CC $(notdir $@)
printf "#include \"phy_init_data.h\"\n" | $(CC) -I $(BUILD_DIR_BASE)/include -I $(ESP32_COMPONENT_PATH) -I $(ESP32_COMPONENT_PATH)/include -c -o $@ -xc -
$(PHY_INIT_DATA_BIN): $(PHY_INIT_DATA_OBJ)
$(summary) BIN $(notdir $@)
$(OBJCOPY) -O binary $< $@
phy_init_data: $(PHY_INIT_DATA_BIN)
phy_init_data-flash: $(BUILD_DIR_BASE)/phy_init_data.bin
@echo "Flashing PHY init data..."
$(PHY_INIT_DATA_FLASH_CMD)
phy_init_data-clean:
rm -f $(PHY_INIT_DATA_BIN) $(PHY_INIT_DATA_OBJ)
all: phy_init_data
flash: phy_init_data
endif # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
# Enable psram cache bug workaround in compiler if selected
ifdef CONFIG_SPIRAM_CACHE_WORKAROUND
CFLAGS+=-mfix-esp32-psram-cache-issue
CXXFLAGS+=-mfix-esp32-psram-cache-issue
endif
# Enable dynamic esp_timer overflow value if building unit tests
ifneq ("$(TEST_COMPONENTS_LIST)","")
CPPFLAGS += -DESP_TIMER_DYNAMIC_OVERFLOW_VAL
endif
# nothing here, esp32s2beta is not suppoted in Make build system

2
components/esp32s2beta/brownout.c
View File

@ -48,7 +48,7 @@ static void rtc_brownout_isr_handler()
void esp_brownout_init()
{
//TODO, chip7.2.2 will use i2c inteface to configure brown out threshold
#warning "TODO: implement brownout threshold configuration for esp32s2beta"
ESP_ERROR_CHECK( rtc_isr_register(rtc_brownout_isr_handler, NULL, RTC_CNTL_BROWN_OUT_INT_ENA_M) );

2
components/esp32s2beta/cache_err_int.c
View File

@ -51,6 +51,8 @@ void esp_cache_err_int_init()
// For this reason, panic handler backtrace will not be correct if the
// interrupt is connected to PRO CPU and invalid access happens on the APP
// CPU.
#warning "TODO: implement cache error access interrupt for esp32s2beta"
#if 0
DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_IA_INT_EN_REG,
DPORT_CACHE_IA_INT_PRO_DRAM1 |

3
components/esp32s2beta/cpu_start.c
View File

@ -499,7 +499,8 @@ static void main_task(void* args)
#endif
//Add IDLE 0 to task wdt
#if 0 // TODO: re-enable task WDT
#warning "cpu_start.c: TODO: re-enable task WDT"
#if 0
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
if(idle_0 != NULL){

2
components/esp32s2beta/crosscore_int.c
View File

@ -40,6 +40,8 @@
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t reason[ portNUM_PROCESSORS ];
#warning "crosscore_int: TODO: simplify for esp32s2beta"
/*
ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.

2
components/esp32s2beta/dport_access.c
View File

@ -41,6 +41,8 @@
#include "xtensa/core-macros.h"
#warning "dport_access: TODO: simplify for esp32s2beta"
#ifndef CONFIG_FREERTOS_UNICORE
static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;

3
components/esp32s2beta/spiram.c
View File

@ -37,7 +37,8 @@ we add more types of external RAM memory, this can be made into a more intellige
#if CONFIG_FREERTOS_UNICORE
#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
#else
#if 0 /* TODO: no even/odd mode for ESP32S2 PSRAM? */
#warning "spiram.c: TODO: no even/odd mode for ESP32S2 PSRAM?"
#if 0
#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
#else
#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH

6
components/esp32s2beta/spiram_psram.c
View File

@ -570,6 +570,7 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
{
uint8_t k;
SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP);
#warning "psram_spi_init: part of configuration missing for esp32s2beta"
#if 0
// SPI_CPOL & SPI_CPHA
CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(spi_num), SPI_MEM_CK_IDLE_EDGE);
@ -627,6 +628,9 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
gpio_matrix_in(PSRAM_SPIWP_IO, SPIWP_IN_IDX, 0);
gpio_matrix_out(PSRAM_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
gpio_matrix_in(PSRAM_SPIHD_IO, SPIHD_IN_IDX, 0);
#warning "psram_gpio_config: parts not implemented for esp32s2beta"
switch (mode) {
case PSRAM_CACHE_F80M_S40M:
extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
@ -713,6 +717,8 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
s_psram_mode = mode;
periph_module_enable(PERIPH_SPI_MODULE);
#warning "psram_enable: some code disabled for esp32s2beta"
#if 0
WRITE_PERI_REG(SPI_MEM_EXT3_REG(0), 0x1);
CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_USR_PREP_HOLD_M);

1
components/esp32s2beta/system_api.c
View File

@ -81,6 +81,7 @@ esp_err_t esp_efuse_mac_get_custom(uint8_t *mac)
esp_err_t esp_efuse_mac_get_default(uint8_t* mac)
{
#warning "esp_efuse_mac_get_default: not implemented for esp32s2beta"
uint32_t mac_low;
uint32_t mac_high;
// uint8_t efuse_crc;

12
components/esp_event/test/test_event.c
View File

@ -289,6 +289,9 @@ static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t
}
#endif
#if CONFIG_IDF_TARGET_ESP32S2BETA
#warning "test_event_on_timer_alarm not ported to esp32s2beta"
#else
#if CONFIG_ESP_EVENT_POST_FROM_ISR
void IRAM_ATTR test_event_on_timer_alarm(void* para)
{
@ -316,6 +319,7 @@ void IRAM_ATTR test_event_on_timer_alarm(void* para)
}
}
#endif //CONFIG_ESP_EVENT_POST_FROM_ISR
#endif //CONFIG_IDF_TARGET_ESP32S2BETA
TEST_CASE("can create and delete event loops", "[event]")
{
@ -1188,6 +1192,9 @@ TEST_CASE("can properly prepare event data posted to loop", "[event]")
TEST_TEARDOWN();
}
#if CONFIG_IDF_TARGET_ESP32S2BETA
#warning "can post events from interrupt handler not ported to esp32s2beta"
#else
TEST_CASE("can post events from interrupt handler", "[event]")
{
SemaphoreHandle_t sem = xSemaphoreCreateBinary();
@ -1223,7 +1230,8 @@ TEST_CASE("can post events from interrupt handler", "[event]")
TEST_TEARDOWN();
}
#endif
#endif // CONFIG_IDF_TARGET_ESP32S2BETA
#endif // CONFIG_ESP_EVENT_POST_FROM_ISR
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
TEST_CASE("can dump event loop profile", "[event]")
@ -1277,4 +1285,4 @@ TEST_CASE("can dump event loop profile", "[event]")
TEST_TEARDOWN();
}
#endif
#endif // CONFIG_ESP_EVENT_LOOP_PROFILING

5
components/esp_wifi/CMakeLists.txt
View File

@ -16,6 +16,11 @@ if (CONFIG_ESP32_NO_BLOBS OR CONFIG_ESP32S2_NO_BLOBS)
set(link_binary_libs 0)
endif()
if (CONFIG_IDF_TARGET_ESP32S2BETA)
message(WARNING "No Wi-Fi libraries yet for esp32s2beta")
set(link_binary_libs 0)
endif()
if(link_binary_libs)
set(COMPONENT_ADD_LDFRAGMENTS "linker.lf")
endif()

5
components/freertos/port.c
View File

@ -109,11 +109,6 @@
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/ets_sys.h"
#endif
/* Defined in portasm.h */
extern void _frxt_tick_timer_init(void);

5
components/freertos/queue.c
View File

@ -79,11 +79,6 @@
#include <stdlib.h>
#include <string.h>
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/ets_sys.h"
#endif
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
all the API functions to use the MPU wrappers. That should only be done when

5
components/freertos/tasks.c
View File

@ -76,11 +76,6 @@
all the API functions to use the MPU wrappers. That should only be done when
task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/ets_sys.h"
#endif
#include "esp_newlib.h"
#include "esp_debug_helpers.h"

229
components/freertos/test/test_freertos.c
View File

@ -1,229 +0,0 @@
/*
Test for multicore FreeRTOS. This test spins up threads, fiddles with queues etc.
*/
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/xtensa_api.h"
#include "unity.h"
#include "soc/uart_periph.h"
#include "soc/dport_reg.h"
#include "driver/gpio.h"
void ets_isr_unmask(uint32_t unmask);
static xQueueHandle myQueue;
static xQueueHandle uartRxQueue;
int ctr;
#if 1
//Idle-loop for delay. Tests involuntary yielding
static void cvTaskDelay(int dummy)
{
volatile int i;
for (i = 0; i < (1 << 17); i++);
}
#else
//Delay task execution using FreeRTOS methods. Tests voluntary yielding.
#define cvTaskDelay(x) vTaskDelay(x)
#endif
#if 0
static void dosegfault3(int i)
{
volatile char *p = (volatile char *)0;
*p = i;
}
static void dosegfault2(int i)
{
if (i > 3) {
dosegfault3(i);
}
}
static void dosegfault(int i)
{
if (i < 5) {
dosegfault(i + 1);
}
dosegfault2(i);
}
#endif
static void queueSender(void *pvParameters)
{
int myCtr = xPortGetCoreID() * 100000;
while (1) {
printf("Core %d: Send to queue: %d\n", xPortGetCoreID(), myCtr);
xQueueSend(myQueue, (void *)(&myCtr), portMAX_DELAY);
printf("Send to queue done.\n");
cvTaskDelay(100);
myCtr++;
}
}
static void queueReceiver(void *pvParameters)
{
int theCtr;
while (1) {
xQueueReceive(myQueue, &theCtr, portMAX_DELAY);
printf("Core %d: Receive from queue: %d\n", xPortGetCoreID(), theCtr);
}
}
static void tskone(void *pvParameters)
{
// char *p=(char *)0;
while (1) {
ctr++;
// if (ctr>60) dosegfault(3);
printf("Task1, core %d, ctr=%d\n", xPortGetCoreID(), ctr);
cvTaskDelay(500);
}
}
static void tsktwo(void *pvParameters)
{
while (1) {
ctr++;
printf("Task2, core %d, ctr=%d\n", xPortGetCoreID(), ctr);
cvTaskDelay(500);
}
}
static void tskthree(void *pvParameters)
{
while (1) {
ctr++;
printf("Task3, core %d, ctr=%d\n", xPortGetCoreID(), ctr);
cvTaskDelay(500);
}
}
static void tskfour(void *pvParameters)
{
while (1) {
ctr++;
printf("Task4, core %d, ctr=%d\n", xPortGetCoreID(), ctr);
cvTaskDelay(500);
}
}
static void tskfive(void *pvParameters)
{
while (1) {
ctr++;
printf("Task5, core %d, ctr=%d\n", xPortGetCoreID(), ctr);
cvTaskDelay(500);
}
}
static void tskyield(void *pvParameters)
{
while (1) {
portYIELD();
}
}
static void tskUartRecv(void *pvParameters)
{
char c;
while (1) {
xQueueReceive(uartRxQueue, &c, portMAX_DELAY);
printf("Uart received %c!\n", c);
}
}
static void uartIsrHdl(void *arg)
{
char c;
BaseType_t xHigherPriorityTaskWoken;
SET_PERI_REG_MASK(UART_INT_CLR_REG(0), UART_RXFIFO_FULL_INT_CLR);
while (READ_PERI_REG(UART_STATUS_REG(0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) {
c = READ_PERI_REG(UART_FIFO_REG(0));
xQueueSendFromISR(uartRxQueue, &c, &xHigherPriorityTaskWoken);
printf("ISR: %c\n", c);
}
if (xHigherPriorityTaskWoken) {
portYIELD_FROM_ISR();
}
}
static void uartRxInit(xQueueHandle q)
{
uint32_t reg_val;
gpio_pullup_dis(1);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD);
// reg_val = READ_PERI_REG(UART_CONF1(0));
reg_val = (1 << UART_RXFIFO_FULL_THRHD_S);
WRITE_PERI_REG(UART_CONF1_REG(0), reg_val);
CLEAR_PERI_REG_MASK(UART_INT_ENA_REG(0), UART_TXFIFO_EMPTY_INT_ENA | UART_RXFIFO_TOUT_INT_ENA);
SET_PERI_REG_MASK(UART_INT_ENA_REG(0), UART_RXFIFO_FULL_INT_ENA);
printf("Enabling int %d\n", ETS_UART0_INUM);
DPORT_REG_SET_FIELD(DPORT_PRO_UART_INTR_MAP_REG, DPORT_PRO_UART_INTR_MAP, ETS_UART0_INUM);
DPORT_REG_SET_FIELD(DPORT_PRO_UART1_INTR_MAP_REG, DPORT_PRO_UART1_INTR_MAP, ETS_UART0_INUM);
xt_set_interrupt_handler(ETS_UART0_INUM, uartIsrHdl, NULL);
xt_ints_on(1 << ETS_UART0_INUM);
}
// TODO: split this thing into separate orthogonal tests
TEST_CASE("Bunch of FreeRTOS tests", "[freertos][ignore]")
{
char *tst;
TaskHandle_t th[12];
int i;
printf("%s\n", __FUNCTION__);
tst = pvPortMalloc(16);
printf("Test malloc returns addr %p\n", tst);
printf("Free heap: %u\n", xPortGetFreeHeapSize());
myQueue = xQueueCreate(10, sizeof(int));
uartRxQueue = xQueueCreate(256, sizeof(char));
printf("Free heap: %u\n", xPortGetFreeHeapSize());
printf("Creating tasks\n");
xTaskCreatePinnedToCore(tskyield , "tskyield1" , 2048, NULL, 3, &th[0], 0);
xTaskCreatePinnedToCore(tskyield , "tskyield2" , 2048, NULL, 3, &th[1], 1);
xTaskCreatePinnedToCore(tskone , "tskone" , 2048, NULL, 3, &th[2], 0);
xTaskCreatePinnedToCore(tsktwo , "tsktwo" , 2048, NULL, 3, &th[3], 1);
xTaskCreatePinnedToCore(tskthree, "tskthree", 2048, NULL, 3, &th[4], 0);
xTaskCreatePinnedToCore(tskfour , "tskfour" , 2048, NULL, 3, &th[5], tskNO_AFFINITY);
xTaskCreatePinnedToCore(tskfive , "tskfive" , 2048, NULL, 3, &th[6], tskNO_AFFINITY);
xTaskCreatePinnedToCore(queueSender , "qsend1" , 2048, NULL, 3, &th[7], 0);
xTaskCreatePinnedToCore(queueSender , "qsend2" , 2048, NULL, 3, &th[8], 1);
xTaskCreatePinnedToCore(queueReceiver , "qrecv1" , 2048, NULL, 3, &th[9], 1);
xTaskCreatePinnedToCore(queueReceiver , "qrecv2" , 2048, NULL, 3, &th[10], 0);
xTaskCreatePinnedToCore(tskUartRecv , "tskuart" , 2048, NULL, 4, &th[11], 1);
printf("Free heap: %u\n", xPortGetFreeHeapSize());
uartRxInit(uartRxQueue);
// Let stuff run for 20s
vTaskDelay(20000 / portTICK_PERIOD_MS);
//Shut down all the tasks
for (i = 0; i < 12; i++) {
vTaskDelete(th[i]);
}
xt_ints_off(1 << ETS_UART0_INUM);
}

6
components/freertos/test/test_freertos_eventgroups.c
View File

@ -8,6 +8,12 @@
#include "driver/timer.h"
#include "unity.h"
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
#define int_clr_timers int_clr
#define update update.update
#define int_st_timers int_st
#endif
#define BIT_CALL (1 << 0)
#define BIT_RESPONSE(TASK) (1 << (TASK+1))
#define ALL_RESPONSE_BITS (((1 << NUM_TASKS) - 1) << 1)

1
components/freertos/test/test_freertos_isinisrcontext.c
View File

@ -4,7 +4,6 @@
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

6
components/freertos/test/test_freertos_task_delay_until.c
View File

@ -27,6 +27,10 @@
static SemaphoreHandle_t task_delete_semphr;
#if CONFIG_IDF_TARGET_ESP32S2BETA
#warning "Test not ported to esp32s2beta"
#else
static void delaying_task(void* arg)
{
uint64_t ref_prev, ref_current;
@ -72,3 +76,5 @@ TEST_CASE("Test vTaskDelayUntil", "[freertos]")
vSemaphoreDelete(task_delete_semphr);
ref_clock_deinit();
}
#endif // CONFIG_IDF_TARGET_ESP32S2BETA

1
components/freertos/test/test_freertos_task_delete.c
View File

@ -17,7 +17,6 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_heap_caps.h"
#include "esp32/rom/ets_sys.h"
#include "unity.h"
#include "test_utils.h"

6
components/freertos/test/test_freertos_task_notify.c
View File

@ -15,6 +15,12 @@
#include "unity.h"
#include "test_utils.h"
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
#define int_clr_timers int_clr
#define update update.update
#define int_st_timers int_st
#endif
#define NO_OF_NOTIFS 4
#define NO_OF_TASKS 2 //Sender and receiver
#define TIMER_DIVIDER 10000

1
components/freertos/test/test_newlib_reent.c
View File

@ -5,7 +5,6 @@
#include <esp_types.h>
#include <stdio.h>
#include <stdlib.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

1
components/freertos/test/test_panic.c
View File

@ -4,7 +4,6 @@
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

1
components/freertos/test/test_preemption.c
View File

@ -4,7 +4,6 @@
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

1
components/freertos/test/test_spinlocks.c
View File

@ -4,7 +4,6 @@
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

6
components/freertos/test/test_suspend_scheduler.c
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@ -13,6 +13,12 @@
#include "driver/timer.h"
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
#define int_clr_timers int_clr
#define update update.update
#define int_st_timers int_st
#endif
static SemaphoreHandle_t isr_semaphore;
static volatile unsigned isr_count;

5
components/freertos/test/test_task_suspend_resume.c
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@ -18,6 +18,11 @@
#include "esp_freertos_hooks.h"
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
#define int_clr_timers int_clr
#define update update.update
#define int_st_timers int_st
#endif
/* Counter task counts a target variable forever */
static void task_count(void *vp_counter)

5
components/freertos/xtensa_intr.c
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@ -34,11 +34,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "freertos/xtensa_api.h"
#include "freertos/portable.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/ets_sys.h"
#endif
#if XCHAL_HAVE_EXCEPTIONS

4
components/soc/esp32s2beta/include/soc/soc.h
View File

@ -241,8 +241,8 @@
#define SOC_IROM_HIGH 0x40c00000
#define SOC_IRAM_LOW 0x40020000
#define SOC_IRAM_HIGH 0x40070000
#define SOC_DRAM_LOW 0x3FFD0000
#define SOC_DRAM_HIGH 0x3FF80000 // TODO: check RAM ranges
#define SOC_DRAM_LOW 0x3FFB0000
#define SOC_DRAM_HIGH 0x40000000
#define SOC_RTC_IRAM_LOW 0x40070000
#define SOC_RTC_IRAM_HIGH 0x40072000
#define SOC_RTC_DRAM_LOW 0x3ff9e000

1
components/soc/esp32s2beta/rtc_init.c
View File

@ -195,6 +195,7 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config()
result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
return result;
}
#warning "rtc_vddsdio_get_config: efuse part not implemented for esp32s2beta"
#if 0
uint32_t efuse_reg = REG_READ(EFUSE_BLK0_RDATA4_REG);
if (efuse_reg & EFUSE_RD_SDIO_FORCE) {

22
components/soc/esp32s2beta/soc_memory_layout.c
View File

@ -121,28 +121,20 @@ extern int _data_start_xtos;
These are removed from the soc_memory_regions array when heaps are created.
*/
const soc_reserved_region_t soc_reserved_regions[] = {
// { 0x40070000, 0x40078000 }, //CPU0 cache region
// { 0x40078000, 0x40080000 }, //CPU1 cache region
// DRAM counterpart of the of the region reserved for IRAM in the linker script
SOC_RESERVE_MEMORY_REGION(0x3ffb8000, 0x3FFD0000, dram_mapped_to_iram);
{ 0x3fff8000, (intptr_t)&_data_start_xtos}, //ROM data region
//ROM data region
SOC_RESERVE_MEMORY_REGION(0x3fff8000, (intptr_t)&_data_start_xtos, rom_data_region);
#if CONFIG_ESP32S2_MEMMAP_TRACEMEM
#if CONFIG_ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
{ 0x3fff8000, 0x40000000 }, //Reserve trace mem region
#else
{ 0x3fff8000, 0x3fffc000 }, //Reserve trace mem region
#endif
#endif
#warning "soc_memory_layout: trace memory regions not handled"
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH}, //SPI RAM gets added later if needed, in spiram.c; reserve it for now
SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
{ SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH}, //SPI RAM(Slow) gets added later if needed, in spiram.c; reserve it for now
SOC_RESERVE_MEMORY_REGION( SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH, extram_slow_data_region); //SPI RAM(Slow) gets added later if needed, in spiram.c; reserve it for now
#endif
#endif
};
const size_t soc_reserved_region_count = sizeof(soc_reserved_regions)/sizeof(soc_reserved_region_t);
#endif

1
components/xtensa/include/esp_debug_helpers.h
View File

@ -6,6 +6,7 @@ extern "C" {
#ifndef __ASSEMBLER__
#include <stdbool.h>
#include "esp_err.h"
#define ESP_WATCHPOINT_LOAD 0x40000000

2
tools/unit-test-app/components/test_utils/CMakeLists.txt
View File

@ -1,4 +1,4 @@
set(COMPONENT_SRCS "ref_clock.c"
set(COMPONENT_SRCS "ref_clock_${CONFIG_IDF_TARGET}.c"
"test_runner.c"
"test_utils.c")
set(COMPONENT_ADD_INCLUDEDIRS include)

1
tools/unit-test-app/components/test_utils/component.mk
View File

@ -0,0 +1 @@
COMPONENT_OBJEXCLUDE := ref_clock_esp32s2beta.o

2
tools/unit-test-app/components/test_utils/ref_clock.c → tools/unit-test-app/components/test_utils/ref_clock_esp32.c
View File

@ -35,8 +35,6 @@
#include "soc/pcnt_periph.h"
#include "soc/gpio_periph.h"
#include "soc/dport_reg.h"
#include "esp32/rom/gpio.h"
#include "esp32/rom/ets_sys.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "driver/periph_ctrl.h"

1
tools/unit-test-app/components/test_utils/ref_clock_esp32s2beta.c Normal file
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@ -0,0 +1 @@
#warning "unit_test_app ref_clock not implemented for esp32s2beta"

2
tools/unit-test-app/components/test_utils/test_utils.c
View File

@ -15,8 +15,6 @@
#include <string.h>
#include "unity.h"
#include "test_utils.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "tcpip_adapter.h"

1
tools/unit-test-app/sdkconfig.defaults.esp32s2beta Normal file
View File

@ -0,0 +1 @@
CONFIG_MBEDTLS_HARDWARE_MPI=n