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soc: define named constants for DPORT_CPUPERIOD_SEL values

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This commit is contained in:
Ivan Grokhotkov 2019-02-26 17:07:59 +08:00
parent 178e5b25e6
commit 8cc6226051
3 changed files with 10 additions and 7 deletions
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2
components/bootloader_support/src/bootloader_clock.c
View File

@ -38,7 +38,7 @@ void bootloader_clock_configure()
*/ */
uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG); uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 && if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == 2) { DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) {
cpu_freq_mhz = 240; cpu_freq_mhz = 240;
} }

3
components/soc/esp32/include/soc/dport_reg.h
View File

@ -179,6 +179,9 @@
#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) #define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
#define DPORT_CPUPERIOD_SEL_V 0x3 #define DPORT_CPUPERIOD_SEL_V 0x3
#define DPORT_CPUPERIOD_SEL_S 0 #define DPORT_CPUPERIOD_SEL_S 0
#define DPORT_CPUPERIOD_SEL_80 0
#define DPORT_CPUPERIOD_SEL_160 1
#define DPORT_CPUPERIOD_SEL_240 2
#define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) #define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040)
/* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */ /* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */

12
components/soc/esp32/rtc_clk.c
View File

@ -453,14 +453,14 @@ static void rtc_clk_bbpll_enable()
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
{ {
int dbias = DIG_DBIAS_80M_160M; int dbias = DIG_DBIAS_80M_160M;
int per_conf = 0; int per_conf = DPORT_CPUPERIOD_SEL_80;
if (cpu_freq_mhz == 80) { if (cpu_freq_mhz == 80) {
/* nothing to do */ /* nothing to do */
} else if (cpu_freq_mhz == 160) { } else if (cpu_freq_mhz == 160) {
per_conf = 1; per_conf = DPORT_CPUPERIOD_SEL_160;
} else if (cpu_freq_mhz == 240) { } else if (cpu_freq_mhz == 240) {
dbias = DIG_DBIAS_240M; dbias = DIG_DBIAS_240M;
per_conf = 2; per_conf = DPORT_CPUPERIOD_SEL_240;
} else { } else {
SOC_LOGE(TAG, "invalid frequency"); SOC_LOGE(TAG, "invalid frequency");
abort(); abort();
@ -688,15 +688,15 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config)
case RTC_CNTL_SOC_CLK_SEL_PLL: { case RTC_CNTL_SOC_CLK_SEL_PLL: {
source = RTC_CPU_FREQ_SRC_PLL; source = RTC_CPU_FREQ_SRC_PLL;
uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
if (cpuperiod_sel == 0) { if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
source_freq_mhz = RTC_PLL_FREQ_320M; source_freq_mhz = RTC_PLL_FREQ_320M;
div = 4; div = 4;
freq_mhz = 80; freq_mhz = 80;
} else if (cpuperiod_sel == 1) { } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
source_freq_mhz = RTC_PLL_FREQ_320M; source_freq_mhz = RTC_PLL_FREQ_320M;
div = 2; div = 2;
freq_mhz = 160; freq_mhz = 160;
} else if (cpuperiod_sel == 2) { } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) {
source_freq_mhz = RTC_PLL_FREQ_480M; source_freq_mhz = RTC_PLL_FREQ_480M;
div = 2; div = 2;
freq_mhz = 240; freq_mhz = 240;