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feat(psram): support bss on psram on p4
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@ -11,6 +11,7 @@
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* When we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
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*----------------------------------------------------------------------------------------------------*/
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#include <sys/param.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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@ -521,3 +522,11 @@ bool esp_psram_extram_test(void)
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return true;
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}
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void esp_psram_bss_init(void)
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{
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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size_t size = (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start);
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memset(&_ext_ram_bss_start, 0, size);
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#endif
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}
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -55,6 +55,11 @@ esp_err_t esp_psram_extram_reserve_dma_pool(size_t size);
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*/
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bool esp_psram_extram_test(void);
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/**
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* @brief Init .bss on psram
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*/
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void esp_psram_bss_init(void);
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#if CONFIG_IDF_TARGET_ESP32
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/**
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* @brief Force a writeback of the data in the PSRAM cache. This is to be called whenever
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@ -103,6 +103,9 @@ MEMORY
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This segment is placed at the beginning of LP RAM, as the end of LP RAM is occupied by LP ROM stack/data
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*/
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lp_reserved_seg(RW) : org = 0x50108000, len = RESERVE_RTC_MEM
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/* PSRAM seg */
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extern_ram_seg(RWX) : org = 0x48000000, len = IDROM_SEG_SIZE
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}
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/* Heap ends at top of dram0_0_seg */
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@ -135,6 +138,12 @@ REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
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REGION_ALIAS("rodata_seg_high", sram_high);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_SPIRAM_XIP_FROM_PSRAM
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REGION_ALIAS("ext_ram_seg", drom_seg);
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#else
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REGION_ALIAS("ext_ram_seg", extern_ram_seg);
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#endif //#if CONFIG_SPIRAM_XIP_FROM_PSRAM
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/**
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* If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
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* also be first in the segment.
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@ -475,6 +475,28 @@ SECTIONS
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mapping[rodata_noload]
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} > rodata_seg_low
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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#if CONFIG_SPIRAM_XIP_FROM_PSRAM
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/**
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* This section is required to skip flash sections, because `extern_ram_seg`
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* and `drom_seg` / `irom_seg` are on the same bus when xip on psram
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*/
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.ext_ram.dummy (NOLOAD):
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{
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. = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start);
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. = ALIGN (0x10000);
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} > ext_ram_seg
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#endif //CONFIG_SPIRAM_XIP_FROM_PSRAM
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/* This section holds .ext_ram.bss data, and will be put in PSRAM */
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.ext_ram.bss (NOLOAD) :
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{
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_ext_ram_bss_start = ABSOLUTE(.);
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mapping[extern_ram]
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ALIGNED_SYMBOL(4, _ext_ram_bss_end)
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} > ext_ram_seg
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#endif //CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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.dram0.bss (NOLOAD) :
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{
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ALIGNED_SYMBOL(4, _bss_start_low)
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@ -148,11 +148,6 @@ extern int _mtvt_table;
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static const char *TAG = "cpu_start";
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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extern int _ext_ram_bss_start;
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extern int _ext_ram_bss_end;
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#endif
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#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
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extern int _iram_bss_start;
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extern int _iram_bss_end;
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@ -683,7 +678,7 @@ void IRAM_ATTR call_start_cpu0(void)
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
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esp_psram_bss_init();
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#endif
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//Enable trace memory and immediately start trace.
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