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refactor(intr): add plic and intc interrupt rv util apis

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refactor(intr): remove the extra instructions in plic and intc
This commit is contained in:
Xiaoyu Liu 2024-08-14 16:12:24 +08:00
parent f0a2091e4d
commit 8a608da2b0
2 changed files with 56 additions and 0 deletions
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28
components/riscv/include/esp_private/interrupt_intc.h
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@ -11,6 +11,7 @@
#include "esp_attr.h" #include "esp_attr.h"
#include "soc/interrupt_reg.h" #include "soc/interrupt_reg.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#include "riscv/csr.h"
#if !SOC_INT_CLIC_SUPPORTED && !SOC_INT_PLIC_SUPPORTED #if !SOC_INT_CLIC_SUPPORTED && !SOC_INT_PLIC_SUPPORTED
@ -63,6 +64,33 @@ FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(uint32_t intr_num)
REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num); REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
} }
/**
* @brief Restore the CPU interrupt level to the value returned by `rv_utils_set_intlevel_regval`.
*
* @param restoreval Former raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
*/
FORCE_INLINE_ATTR void rv_utils_restore_intlevel_regval(uint32_t restoreval)
{
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, restoreval);
}
/**
* @brief Set the interrupt threshold to `intlevel` while getting the current level.
*
* @param intlevel New raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
*
* @return Current raw interrupt level, can be restored by calling `rv_utils_restore_intlevel_regval`.
*/
FORCE_INLINE_ATTR uint32_t rv_utils_set_intlevel_regval(uint32_t intlevel)
{
uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
uint32_t old_thresh = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
rv_utils_restore_intlevel_regval(intlevel);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
return old_thresh;
}
#ifdef __cplusplus #ifdef __cplusplus
} }

28
components/riscv/include/esp_private/interrupt_plic.h
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@ -11,6 +11,7 @@
#include "esp_attr.h" #include "esp_attr.h"
#include "soc/interrupt_reg.h" #include "soc/interrupt_reg.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#include "riscv/csr.h"
#if SOC_INT_PLIC_SUPPORTED #if SOC_INT_PLIC_SUPPORTED
@ -64,6 +65,33 @@ FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(uint32_t intr_num)
REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num); REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
} }
/**
* @brief Restore the CPU interrupt level to the value returned by `rv_utils_set_intlevel_regval`.
*
* @param restoreval Former raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
*/
FORCE_INLINE_ATTR void rv_utils_restore_intlevel_regval(uint32_t restoreval)
{
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, restoreval);
}
/**
* @brief Set the interrupt threshold to `intlevel` while getting the current level.
*
* @param intlevel New raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
*
* @return Current raw interrupt level, can be restored by calling `rv_utils_restore_intlevel_regval`.
*/
FORCE_INLINE_ATTR uint32_t rv_utils_set_intlevel_regval(uint32_t intlevel)
{
uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
uint32_t old_thresh = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
rv_utils_restore_intlevel_regval(intlevel);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
return old_thresh;
}
#ifdef __cplusplus #ifdef __cplusplus
} }