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uart: support examples and tests on esp32c6

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This commit is contained in:
laokaiyao 2022-11-15 18:22:50 +08:00
parent 7778ab6d5c
commit 888ca08cb2
13 changed files with 62 additions and 116 deletions
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6
components/driver/.build-test-rules.yml
View File

@ -88,9 +88,3 @@ components/driver/test_apps/touch_sensor_v2:
components/driver/test_apps/twai:
disable:
- if: SOC_TWAI_SUPPORTED != 1
components/driver/test_apps/uart:
disable_test:
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target esp32c6 not supported yet

5
components/driver/uart.c
View File

@ -232,6 +232,11 @@ esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t* out_freq_hz)
case UART_SCLK_XTAL:
freq = esp_clk_xtal_freq();
break;
#endif
#if SOC_UART_SUPPORT_PLL_F80M_CLK
case UART_SCLK_PLL_F80M:
freq = UART_LL_PLL_DIV_FREQ;
break;
#endif
default:
return ESP_ERR_INVALID_ARG;

100
components/hal/esp32c6/include/hal/uart_ll.h
View File

@ -31,6 +31,20 @@ extern "C" {
#define UART_LL_FSM_IDLE (0x0)
#define UART_LL_FSM_TX_WAIT_SEND (0xf)
#define UART_LL_PLL_DIV_FREQ (80000000) // 80 MHz
#define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \
if ((hw) == &UART0) { \
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \
} else { \
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \
}
#define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? \
HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix) : \
HAL_FORCE_READ_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix))
#define UART_LL_PCR_REG_SET(hw, reg_suffix, field_suffix, val) \
if ((hw) == &UART0) { \
PCR.uart0_##reg_suffix.uart0_##field_suffix = (val); \
@ -62,14 +76,21 @@ typedef enum {
UART_INTR_RS485_FRM_ERR = (0x1 << 16),
UART_INTR_RS485_CLASH = (0x1 << 17),
UART_INTR_CMD_CHAR_DET = (0x1 << 18),
// UART_INTR_WAKEUP = (0x1 << 19), // TODO: IDF-5338
// UART_INTR_WAKEUP = (0x1 << 19), // TODO: Test UART wakeup while supporting sleep
} uart_intr_t;
/**
* @brief Sync the update to UART core clock domain
*
* @param hw Beginning address of the peripheral registers.
*
* @return None.
*/
static inline void uart_ll_update(uart_dev_t *hw)
{
// TODO: set a timeout ??
while (hw->reg_update.reg_update);
hw->reg_update.reg_update = 1;
while (hw->reg_update.reg_update);
}
/**
@ -82,7 +103,7 @@ static inline void uart_ll_update(uart_dev_t *hw)
*/
static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en);
hw->clk_conf.rst_core = core_rst_en;
}
/**
@ -94,7 +115,6 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
*/
static inline void uart_ll_sclk_enable(uart_dev_t *hw)
{
UART_LL_PCR_REG_SET(hw, conf, clk_en, 1);
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1);
}
@ -107,7 +127,6 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw)
*/
static inline void uart_ll_sclk_disable(uart_dev_t *hw)
{
UART_LL_PCR_REG_SET(hw, conf, clk_en, 0);
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0);
}
@ -124,7 +143,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
{
switch (source_clk) {
default:
case UART_SCLK_APB:
case UART_SCLK_PLL_F80M:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1);
break;
case UART_SCLK_RTC:
@ -149,7 +168,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
default:
case 1:
*source_clk = UART_SCLK_APB;
*source_clk = UART_SCLK_PLL_F80M;
break;
case 2:
*source_clk = UART_SCLK_RTC;
@ -180,7 +199,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
uart_ll_update(hw);
}
@ -197,7 +216,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
{
typeof(hw->clkdiv_sync) div_reg;
div_reg.val = hw->clkdiv_sync.val;
return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_div_num) + 1));
return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * (UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1));
}
/**
@ -211,7 +230,6 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
uart_ll_update(hw);
}
/**
@ -225,7 +243,6 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
uart_ll_update(hw);
}
/**
@ -251,7 +268,6 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_clr.val = mask;
uart_ll_update(hw);
}
/**
@ -425,7 +441,6 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode
static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
{
hw->conf1.rxfifo_full_thrhd = full_thrhd;
uart_ll_update(hw);
}
/**
@ -440,7 +455,6 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr
static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
{
hw->conf1.txfifo_empty_thrhd = empty_thrhd;
uart_ll_update(hw);
}
/**
@ -484,13 +498,11 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
{
if (break_num > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num);
uart_ll_update(hw);
hw->conf0_sync.txd_brk = 1;
uart_ll_update(hw);
} else {
hw->conf0_sync.txd_brk = 0;
uart_ll_update(hw);
}
uart_ll_update(hw);
}
/**
@ -507,20 +519,16 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs;
uart_ll_update(hw);
hw->hwfc_conf_sync.rx_flow_en = 1;
uart_ll_update(hw);
} else {
hw->hwfc_conf_sync.rx_flow_en = 0;
uart_ll_update(hw);
}
if (flow_ctrl & UART_HW_FLOWCTRL_CTS) {
hw->conf0_sync.tx_flow_en = 1;
uart_ll_update(hw);
} else {
hw->conf0_sync.tx_flow_en = 0;
uart_ll_update(hw);
}
uart_ll_update(hw);
}
/**
@ -555,21 +563,16 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
{
if (sw_flow_ctrl_en) {
hw->swfc_conf0_sync.xonoff_del = 1;
uart_ll_update(hw);
hw->swfc_conf0_sync.sw_flow_con_en = 1;
uart_ll_update(hw);
hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
uart_ll_update(hw);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
uart_ll_update(hw);
} else {
hw->swfc_conf0_sync.sw_flow_con_en = 0;
uart_ll_update(hw);
hw->swfc_conf0_sync.xonoff_del = 0;
uart_ll_update(hw);
}
uart_ll_update(hw);
}
/**
@ -588,13 +591,9 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char);
uart_ll_update(hw);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
uart_ll_update(hw);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle);
uart_ll_update(hw);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle);
uart_ll_update(hw);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout);
uart_ll_update(hw);
}
@ -638,7 +637,6 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
{
hw->conf1.sw_dtr = level & 0x1;
uart_ll_update(hw);
}
/**
@ -653,7 +651,6 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
{
hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
uart_ll_update(hw);
}
/**
@ -666,11 +663,8 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
{
hw->rs485_conf_sync.rs485_en = 0;
uart_ll_update(hw);
hw->rs485_conf_sync.rs485tx_rx_en = 0;
uart_ll_update(hw);
hw->rs485_conf_sync.rs485rxby_tx_en = 0;
uart_ll_update(hw);
hw->conf0_sync.irda_en = 0;
uart_ll_update(hw);
}
@ -686,17 +680,11 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
{
// Application software control, remove echo
hw->rs485_conf_sync.rs485rxby_tx_en = 1;
uart_ll_update(hw);
hw->conf0_sync.irda_en = 0;
uart_ll_update(hw);
hw->conf0_sync.sw_rts = 0;
uart_ll_update(hw);
hw->conf0_sync.irda_en = 0;
uart_ll_update(hw);
hw->rs485_conf_sync.dl0_en = 1;
uart_ll_update(hw);
hw->rs485_conf_sync.dl1_en = 1;
uart_ll_update(hw);
hw->rs485_conf_sync.rs485_en = 1;
uart_ll_update(hw);
}
@ -712,20 +700,14 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
{
// Enable receiver, sw_rts = 1 generates low level on RTS pin
hw->conf0_sync.sw_rts = 1;
uart_ll_update(hw);
// Half duplex mode
hw->rs485_conf_sync.rs485tx_rx_en = 0;
uart_ll_update(hw);
// Setting this bit will allow data to be transmitted while receiving data(full-duplex mode).
// But note that this full-duplex mode has no conflict detection function
hw->rs485_conf_sync.rs485rxby_tx_en = 0;
uart_ll_update(hw);
hw->conf0_sync.irda_en = 0;
uart_ll_update(hw);
hw->rs485_conf_sync.dl0_en = 1;
uart_ll_update(hw);
hw->rs485_conf_sync.dl1_en = 1;
uart_ll_update(hw);
hw->rs485_conf_sync.rs485_en = 1;
uart_ll_update(hw);
}
@ -740,19 +722,13 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
{
hw->conf0_sync.irda_en = 0;
uart_ll_update(hw);
// Enable full-duplex mode
hw->rs485_conf_sync.rs485tx_rx_en = 1;
uart_ll_update(hw);
// Transmitter should send data when the receiver is busy,
hw->rs485_conf_sync.rs485rxby_tx_en = 1;
uart_ll_update(hw);
hw->rs485_conf_sync.dl0_en = 1;
uart_ll_update(hw);
hw->rs485_conf_sync.dl1_en = 1;
uart_ll_update(hw);
hw->conf0_sync.sw_rts = 0;
uart_ll_update(hw);
hw->rs485_conf_sync.rs485_en = 1;
uart_ll_update(hw);
}
@ -767,13 +743,9 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
{
hw->rs485_conf_sync.rs485_en = 0;
uart_ll_update(hw);
hw->rs485_conf_sync.rs485tx_rx_en = 0;
uart_ll_update(hw);
hw->rs485_conf_sync.rs485rxby_tx_en = 0;
uart_ll_update(hw);
hw->conf0_sync.sw_rts = 0;
uart_ll_update(hw);
hw->conf0_sync.irda_en = 1;
uart_ll_update(hw);
}
@ -820,9 +792,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
{
*cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data);
uart_ll_update(hw);
*char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
uart_ll_update(hw);
}
/**
@ -928,7 +898,6 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0;
conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0;
hw->conf0_sync.val = conf0_reg.val;
uart_ll_update(hw);
typeof(hw->conf1) conf1_reg;
conf1_reg.val = hw->conf1.val;
@ -953,13 +922,11 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
uint16_t tout_val = tout_thrd;
if(tout_thrd > 0) {
hw->tout_conf_sync.rx_tout_thrhd = tout_val;
uart_ll_update(hw);
hw->tout_conf_sync.rx_tout_en = 1;
uart_ll_update(hw);
} else {
hw->tout_conf_sync.rx_tout_en = 0;
uart_ll_update(hw);
}
uart_ll_update(hw);
}
/**
@ -1062,7 +1029,6 @@ static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
static inline void uart_ll_force_xoff(uart_port_t uart_num)
{
REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
uart_ll_update(UART_LL_GET_HW(uart_num));
REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF);
uart_ll_update(UART_LL_GET_HW(uart_num));
}
@ -1077,9 +1043,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num)
static inline void uart_ll_force_xon(uart_port_t uart_num)
{
REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XOFF);
uart_ll_update(UART_LL_GET_HW(uart_num));
REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
uart_ll_update(UART_LL_GET_HW(uart_num));
REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XON);
uart_ll_update(UART_LL_GET_HW(uart_num));
}

8
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -807,19 +807,15 @@ config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_APB_CLK
config SOC_UART_SUPPORT_PLL_F80M_CLK
bool
default y
config SOC_UART_SUPPORT_RTC_CLK
bool
default n
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_REQUIRE_CORE_RESET
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y

10
components/soc/esp32c6/include/soc/clk_tree_defs.h
View File

@ -224,13 +224,13 @@ typedef enum {
* @brief Type of UART clock source, reserved for the legacy UART driver
*/
typedef enum {
UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
#if CONFIG_IDF_ENV_FPGA
UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< UART source clock default choice is XTAL for FPGA environment */
UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< UART source clock default choice is XTAL for FPGA environment */
#else
UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
#endif
} soc_periph_uart_clk_src_legacy_t;

7
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -393,11 +393,10 @@
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */
#define SOC_UART_SUPPORT_RTC_CLK (0) /*!< Support RTC clock as the clock source */ // TODO: IDF-5338
#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_DIV as the clock source */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: IDF-5338
#define SOC_UART_REQUIRE_CORE_RESET (1)
// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: Test UART wakeup while supporting sleep
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)

12
components/soc/esp32c6/include/soc/uart_channel.h
View File

@ -10,12 +10,12 @@
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO21_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 21
#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 20
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17
#define UART_TXD_GPIO21_DIRECT_CHANNEL UART_GPIO21_DIRECT_CHANNEL
#define UART_RXD_GPIO20_DIRECT_CHANNEL UART_GPIO20_DIRECT_CHANNEL
#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
#endif

1
docs/docs_not_updated/esp32c6.txt
View File

@ -113,7 +113,6 @@ api-reference/peripherals/ds
api-reference/peripherals/sd_pullup_requirements
api-reference/peripherals/index
api-reference/peripherals/sdmmc_host
api-reference/peripherals/uart
api-reference/kconfig
api-reference/network
api-reference/network/esp_openthread

10
examples/peripherals/.build-test-rules.yml
View File

@ -238,19 +238,9 @@ examples/peripherals/twai/twai_self_test:
temporary: true
reason: lack of runners
examples/peripherals/uart/uart_echo:
disable:
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target esp32c6 is not supported yet
examples/peripherals/uart/uart_echo_rs485:
enable:
- if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "esp32h4"
disable:
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target esp32c6 is not supported yet
examples/peripherals/usb:
disable:

4
examples/peripherals/uart/uart_echo/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
# UART Echo Example

4
examples/peripherals/uart/uart_echo/main/Kconfig.projbuild
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@ -6,8 +6,8 @@ menu "Echo Example Configuration"
int "UART port number"
range 0 2 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
default 2 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
range 0 1 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4
default 1 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4
range 0 1
default 1
help
UART communication port number for the example.
See UART documentation for available port numbers.

7
examples/peripherals/uart/uart_echo_rs485/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-H4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# UART RS485 Echo Example
@ -36,8 +36,7 @@ ESP32 BOARD | | RS-485 side | | SERIAL AD
Connect a USB-to-RS485 adapter to a computer, then connect the adapter's A/B output lines with the corresponding A/B output lines of the RS485 line driver connected to the ESP32 chip (see figure above).
```
------------------------------------------------------------------------------------------------------------------------------
| UART Interface | #define | Default ESP32 Pin | Default pins for | External RS485 Driver Pin |
| | | | ESP32-S2(S3, C3, C2, H4) | |
| UART Interface | #define | Default pin for ESP32 | Default pins for others | External RS485 Driver Pin |
| ----------------------|--------------------|-----------------------|---------------------------|---------------------------|
| Transmit Data (TxD) | CONFIG_MB_UART_TXD | GPIO23 | GPIO9 | DI |
| Receive Data (RxD) | CONFIG_MB_UART_RXD | GPIO22 | GPIO8 | RO |

4
examples/peripherals/uart/uart_echo_rs485/main/Kconfig.projbuild
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@ -6,8 +6,8 @@ menu "Echo RS485 Example Configuration"
int "UART port number"
range 0 2 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
default 2 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
range 0 1 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4
default 1 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4
range 0 1
default 1
help
UART communication port number for the example.
See UART documentation for available port numbers.