From 8842e5764f2e73b010eda14b1e31246c0cc85954 Mon Sep 17 00:00:00 2001 From: Armando Date: Tue, 3 Sep 2024 14:08:15 +0800 Subject: [PATCH] feat(psram): xip psram c5 --- .../src/bootloader_utility.c | 2 +- components/esp_psram/esp32c5/Kconfig.spiram | 34 +++++++++++++++++++ .../esp_psram/test_apps/psram/pytest_psram.py | 1 + .../psram/sdkconfig.ci.esp32c5_advanced | 15 ++++++++ components/esp_system/port/image_process.c | 3 ++ components/hal/esp32c5/include/hal/mmu_ll.h | 2 ++ .../soc/esp32c5/include/soc/ext_mem_defs.h | 4 +-- .../flash_mmap/sdkconfig.ci.xip_psram_esp32c5 | 2 ++ 8 files changed, 60 insertions(+), 3 deletions(-) create mode 100644 components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c5_advanced create mode 100644 components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram_esp32c5 diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 4e469b4018..30dd5049fc 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -875,7 +875,7 @@ static void set_cache_and_start_app( } //we use the MMU_LL_END_DROM_ENTRY_ID mmu entry as a map page for app to find the boot partition mmu_hal_map_region(0, MMU_TARGET_FLASH0, MMU_LL_END_DROM_ENTRY_VADDR, drom_addr_aligned, CONFIG_MMU_PAGE_SIZE, &actual_mapped_len); - ESP_EARLY_LOGV(TAG, "mapped one page of the rodata, from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len); + ESP_EARLY_LOGV(TAG, "mapped one page of the rodata, from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, MMU_LL_END_DROM_ENTRY_VADDR, actual_mapped_len); #endif //-----------------------MAP IROM-------------------------- diff --git a/components/esp_psram/esp32c5/Kconfig.spiram b/components/esp_psram/esp32c5/Kconfig.spiram index 725b456a3c..75e0ec8da9 100644 --- a/components/esp_psram/esp32c5/Kconfig.spiram +++ b/components/esp_psram/esp32c5/Kconfig.spiram @@ -44,5 +44,39 @@ menu "SPI RAM config" default 80 if SPIRAM_SPEED_80M default 40 if SPIRAM_SPEED_40M + config SPIRAM_FETCH_INSTRUCTIONS + bool + help + Enable this option allows moving application's instruction segment from the SPI Flash to PSRAM + + config SPIRAM_RODATA + bool + help + Enable this option allows moving application's rodata segment from the SPI Flash to + PSRAM + + config SPIRAM_XIP_FROM_PSRAM + bool "Enable Executable in place from (XiP) from PSRAM feature (READ HELP)" + default n + select SPIRAM_FETCH_INSTRUCTIONS + select SPIRAM_RODATA + select SPIRAM_FLASH_LOAD_TO_PSRAM + help + If enabled, firmware in flash including instructions and data will be moved into PSRAM on startup, + firmware code will execute directly from PSRAM. + + With this option enabled, code that requires execution during an MSPI1 Flash operation + does not have to be placed in IRAM. Therefore codes that need to be executing during Flash + operations can continue working normally. + + This feature is useful for high throughput peripheral involved applications to improve + the performance during MSPI1 flash operations. + + config SPIRAM_FLASH_LOAD_TO_PSRAM + bool + help + This is a helper indicating this condition: + `CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_IDF_TARGET_ESP32C5` + source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here endmenu diff --git a/components/esp_psram/test_apps/psram/pytest_psram.py b/components/esp_psram/test_apps/psram/pytest_psram.py index 949aea2d4f..04dd2807b8 100644 --- a/components/esp_psram/test_apps/psram/pytest_psram.py +++ b/components/esp_psram/test_apps/psram/pytest_psram.py @@ -94,6 +94,7 @@ def test_psram_esp32p4(dut: Dut) -> None: 'config', [ 'esp32c5_release', + 'esp32c5_advanced', ], indirect=True, ) diff --git a/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c5_advanced b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c5_advanced new file mode 100644 index 0000000000..cab65486e0 --- /dev/null +++ b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32c5_advanced @@ -0,0 +1,15 @@ +CONFIG_IDF_TARGET="esp32c5" + +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y + +CONFIG_SPIRAM=y +CONFIG_SPIRAM_SPEED_80M=y +CONFIG_SPIRAM_XIP_FROM_PSRAM=y +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y +CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y + +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" diff --git a/components/esp_system/port/image_process.c b/components/esp_system/port/image_process.c index 2f795bf765..9dec8b125b 100644 --- a/components/esp_system/port/image_process.c +++ b/components/esp_system/port/image_process.c @@ -176,6 +176,9 @@ static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segme ESP_RETURN_ON_FALSE_ISR(false, ESP_ERR_INVALID_STATE, TAG, "unaligned segment length 0x%"PRIx32, data_len); } + mmu_ll_set_entry_invalid(0, MMU_LL_END_DROM_ENTRY_ID); + s_current_read_mapping = UINT32_MAX; + return ESP_OK; } diff --git a/components/hal/esp32c5/include/hal/mmu_ll.h b/components/hal/esp32c5/include/hal/mmu_ll.h index 398d2bd7a1..39f3bd0db3 100644 --- a/components/hal/esp32c5/include/hal/mmu_ll.h +++ b/components/hal/esp32c5/include/hal/mmu_ll.h @@ -24,6 +24,8 @@ extern "C" { #endif +#define MMU_LL_FLASH_MMU_ID 0 +#define MMU_LL_PSRAM_MMU_ID 0 #define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE) #define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1) diff --git a/components/soc/esp32c5/include/soc/ext_mem_defs.h b/components/soc/esp32c5/include/soc/ext_mem_defs.h index e694359f34..de680754ad 100644 --- a/components/soc/esp32c5/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c5/include/soc/ext_mem_defs.h @@ -58,7 +58,7 @@ extern "C" { * valid bit + value bits * valid bit is BIT(9), so value bits are 0x1ff */ -#define SOC_MMU_VALID_VAL_MASK (SOC_MMU_ACCESS_SPIRAM-1) +#define SOC_MMU_VALID_VAL_MASK (SOC_MMU_ACCESS_SPIRAM - 1) /** * Max MMU available paddr page num. * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: @@ -72,7 +72,7 @@ extern "C" { * This is the mask used for mapping. e.g.: * 0x4200_0000 & SOC_MMU_VADDR_MASK */ -#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1) +#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1) #define SOC_MMU_DBUS_VADDR_BASE 0x42000000 #define SOC_MMU_IBUS_VADDR_BASE 0x42000000 diff --git a/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram_esp32c5 b/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram_esp32c5 new file mode 100644 index 0000000000..9c3610a24b --- /dev/null +++ b/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram_esp32c5 @@ -0,0 +1,2 @@ +CONFIG_IDF_TARGET="esp32c5" +CONFIG_SPIRAM_XIP_FROM_PSRAM=y