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rtc_clk: Remove the ck8m fpu logic when setting rtc slow clock source, ck8m fpu in sleep logic is now completely handled in sleep_modes.c

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This commit is contained in:
songruojing 2022-05-20 00:21:07 +08:00 committed by BOT
parent 911b310a90
commit 87b917c04a
4 changed files with 0 additions and 16 deletions
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4
components/esp_hw_support/port/esp32c2/rtc_clk.c
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@ -75,10 +75,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
(slow_freq == RTC_SLOW_FREQ_EXT_CLK) ? 1 : 0); (slow_freq == RTC_SLOW_FREQ_EXT_CLK) ? 1 : 0);
/* The clk_8m_d256 will be closed when rtc_state in SLEEP,
so if the slow_clk is 8md256, clk_8m must be force power on
*/
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
} }

4
components/esp_hw_support/port/esp32c3/rtc_clk.c
View File

@ -125,10 +125,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
(slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
/* The clk_8m_d256 will be closed when rtc_state in SLEEP,
so if the slow_clk is 8md256, clk_8m must be force power on
*/
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
} }

4
components/esp_hw_support/port/esp32s2/rtc_clk.c
View File

@ -218,10 +218,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
(slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
/* The clk_8m_d256 will be closed when rtc_state in SLEEP,
so if the slow_clk is 8md256, clk_8m must be force power on
*/
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
} }

4
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@ -146,10 +146,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
(slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
/* The clk_8m_d256 will be closed when rtc_state in SLEEP,
so if the slow_clk is 8md256, clk_8m must be force power on
*/
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
} }