Merge branch 'feat/ram_loadable_app_c5_c61' into 'master'

ram_app: support c5 c61, fixed PMA15 occupied by ROM issue

Closes IDF-8644, IDF-9251, IDF-10315, and IDF-10951

See merge request espressif/esp-idf!33381

components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h

@@ -28,12 +28,10 @@ esp_err_t bootloader_init_spi_flash(void);
 void bootloader_flash_hardware_init(void);
 #endif
 
-#if SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
 /**
- * @brief Initialise flash core clock
+ * @brief Initialise mspi core clock
  */
-void bootloader_flash_init_core_clock(void);
-#endif  //SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
+void bootloader_init_mspi_clock(void);
 
 #ifdef __cplusplus
 }

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c

@@ -48,8 +48,18 @@ void IRAM_ATTR bootloader_flash_cs_timing_config()
     SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
 }
 
+void IRAM_ATTR bootloader_init_mspi_clock(void)
+{
+    // Set source mspi pll clock as 80M in bootloader stage.
+    // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
+    // in this stage, set divider as 6
+    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
+    mspi_ll_fast_set_hs_divider(6);
+}
+
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
 {
+    bootloader_init_mspi_clock();
     uint32_t spi_clk_div = 0;
     switch (pfhdr->spi_speed) {
     case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -204,11 +214,7 @@ static void bootloader_spi_flash_resume(void)
 
 esp_err_t bootloader_init_spi_flash(void)
 {
-    // Set source mspi pll clock as 80M in bootloader stage.
-    // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
-    // in this stage, set divider as 6
-    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
-    mspi_ll_fast_set_hs_divider(6);
+    bootloader_init_mspi_clock();
 
     bootloader_init_flash_configure();
     bootloader_spi_flash_resume();

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c

@@ -46,8 +46,19 @@ void IRAM_ATTR bootloader_flash_cs_timing_config()
     SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
 }
 
+void IRAM_ATTR bootloader_init_mspi_clock(void)
+{
+    // Set source mspi pll clock as 80M in bootloader stage.
+    // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
+    // in this stage, set divider as 6
+    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
+    mspi_ll_fast_set_hs_divider(6);
+}
+
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
 {
+    bootloader_init_mspi_clock();
+
     uint32_t spi_clk_div = 0;
     switch (pfhdr->spi_speed) {
     case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -198,13 +209,7 @@ static void bootloader_spi_flash_resume(void)
 
 esp_err_t bootloader_init_spi_flash(void)
 {
-
-    // Set source mspi pll clock as 80M in bootloader stage.
-    // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
-    // in this stage, set divider as 6
-    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
-    mspi_ll_fast_set_hs_divider(6);
-
+    bootloader_init_mspi_clock();
     bootloader_init_flash_configure();
     bootloader_spi_flash_resume();
     bootloader_flash_unlock();

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c

@@ -42,7 +42,7 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
     SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S);
 }
 
-void IRAM_ATTR bootloader_flash_init_core_clock(void)
+void IRAM_ATTR bootloader_init_mspi_clock(void)
 {
     _spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
     _spimem_ctrlr_ll_set_core_clock(0, 6);
@@ -50,7 +50,7 @@ void IRAM_ATTR bootloader_flash_init_core_clock(void)
 
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
 {
-    bootloader_flash_init_core_clock();
+    bootloader_init_mspi_clock();
 
     uint32_t spi_clk_div = 0;
     switch (pfhdr->spi_speed) {

components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

@@ -112,7 +112,7 @@ static inline void bootloader_hardware_init(void)
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
     // IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used.
     if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) {
-        bootloader_flash_init_core_clock();
+        bootloader_init_mspi_clock();
     }
 #endif
 }

components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5

@@ -1 +1,2 @@
 CONFIG_SDMMC_BOARD_ESP32C5_BREAKOUT=y
+CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y

components/esp_hw_support/port/esp32c5/cpu_region_protect.c

@@ -69,6 +69,8 @@ static void esp_cpu_configure_invalid_regions(void)
 
     // 8. End of address space
     PMA_ENTRY_SET_TOR(14, SOC_PERIPHERAL_HIGH, PMA_NONE);
+
+    PMA_ENTRY_CFG_RESET(15);
     PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
 }
 

components/riscv/include/riscv/csr.h

@@ -136,6 +136,12 @@ extern "C" {
     RV_CLEAR_CSR((CSR_PMPCFG0) + (ENTRY)/4, (0xFF) << (ENTRY%4)*8); \
     } while(0)
 
+/*Reset all permissions of a particular PMACFG entry*/
+#define PMA_ENTRY_CFG_RESET(ENTRY) do {\
+    RV_WRITE_CSR((CSR_PMACFG0) + (ENTRY) , 0); \
+    RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY) , 0); \
+    } while(0)
+
 /********************************************************
    Trigger Module register fields (Debug specification)
  ********************************************************/

examples/storage/sd_card/sdspi/sdkconfig.defaults.esp32c5

@@ -0,0 +1 @@
+CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y

tools/test_apps/system/.build-test-rules.yml

@@ -76,12 +76,6 @@ tools/test_apps/system/panic:
   enable:
     - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4", "esp32c61"] # preview targets
 
-tools/test_apps/system/ram_loadable_app:
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: not supported  # TODO: [ESP32C5] IDF-8644, IDF-10315
-
 tools/test_apps/system/rtc_mem_reserve:
   enable:
     - if: IDF_TARGET in ["esp32p4"]

tools/test_apps/system/ram_loadable_app/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # RAM loadable app Example
 

tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py

@@ -4,7 +4,6 @@ import pytest
 from pytest_embedded_idf.dut import IdfDut
 
 
-@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='esp32c5 support TBD')  # TODO: [ESP32C5] IDF-8644, IDF-10315
 @pytest.mark.esp32
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
@@ -12,7 +11,6 @@ from pytest_embedded_idf.dut import IdfDut
 @pytest.mark.esp32c3
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
-@pytest.mark.esp32c5
 @pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize('config', ['pure_ram',], indirect=True,)
@@ -21,8 +19,6 @@ def test_pure_ram_loadable_app(dut: IdfDut) -> None:
     dut.expect('Time since boot: 3 seconds...', timeout=10)
 
 
-# TODO: [ESP32C5] IDF-8644, IDF-10315, [ESP32C61] IDF-10951
-@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='support TBD')
 @pytest.mark.esp32
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
@@ -30,7 +26,6 @@ def test_pure_ram_loadable_app(dut: IdfDut) -> None:
 @pytest.mark.esp32c3
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
-@pytest.mark.esp32c5
 @pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize('config', ['defaults',], indirect=True,)
@@ -41,6 +36,7 @@ def test_ram_loadable_app(dut: IdfDut) -> None:
 
 # Tests with ram_app runners
 @pytest.mark.esp32p4
+@pytest.mark.esp32c5
 @pytest.mark.ram_app
 @pytest.mark.parametrize('config', ['defaults',], indirect=True,)
 def test_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None:
@@ -49,6 +45,7 @@ def test_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None:
 
 
 @pytest.mark.esp32p4
+@pytest.mark.esp32c5
 @pytest.mark.ram_app
 @pytest.mark.parametrize('config', ['pure_ram',], indirect=True,)
 def test_pure_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None:

tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32c5

@@ -0,0 +1 @@
+CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y