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Merge branch 'bugfix/xtal_to_pll_8684' into 'master'

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rtc_clk: change clock source from XTAL to PLL on real board(8684)

See merge request espressif/esp-idf!16397
This commit is contained in:
Simon 2021-12-15 08:47:42 +00:00
commit 878c643743
6 changed files with 28 additions and 103 deletions
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1
Kconfig
View File

@ -88,7 +88,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV
select ESPTOOLPY_NO_STUB # remove if ESPTOOL-303
select IDF_ENV_FPGA
config IDF_TARGET_LINUX
bool

3
components/esp8684/Kconfig
View File

@ -15,8 +15,6 @@ menu "ESP8684-Specific"
bool "80 MHz"
config ESP8684_DEFAULT_CPU_FREQ_120
bool "120 MHz"
config ESP8684_DEFAULT_CPU_FREQ_160
bool "160 MHz"
endchoice
config ESP8684_DEFAULT_CPU_FREQ_MHZ
@ -24,7 +22,6 @@ menu "ESP8684-Specific"
default 40 if ESP8684_DEFAULT_CPU_FREQ_40
default 80 if ESP8684_DEFAULT_CPU_FREQ_80
default 120 if ESP8684_DEFAULT_CPU_FREQ_120
default 160 if ESP8684_DEFAULT_CPU_FREQ_160
menu "Cache config"

105
components/esp_hw_support/port/esp8684/rtc_clk.c
View File

@ -26,7 +26,6 @@
static const char *TAG = "rtc_clk";
#define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480
#define DELAY_RTC_CLK_SWITCH 5
@ -137,85 +136,21 @@ static void rtc_clk_bbpll_enable(void)
void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
{
uint8_t div_ref;
uint8_t div7_0;
uint8_t dr1;
uint8_t dr3;
uint8_t dchgp;
uint8_t dcur;
uint8_t dbias;
(void) xtal_freq;
// ESP8684 only support 40M XTAL, all the parameters are given as 40M XTAL directly.
uint8_t div_ref = 0;
uint8_t div7_0 = 8;
uint8_t dr1 = 0;
uint8_t dr3 = 0;
uint8_t dchgp = 5;
uint8_t dcur = 3;
uint8_t dbias = 2;
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
if (pll_freq == RTC_PLL_FREQ_480M) {
/* Set this register to let the digital part know 480M PLL is used */
SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
/* Configure 480M PLL */
switch (xtal_freq) {
case RTC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
div_ref = 1;
div7_0 = 26;
dr1 = 1;
dr3 = 1;
dchgp = 4;
dcur = 0;
dbias = 2;
break;
default:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
}
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
} else {
/* Clear this register to let the digital part know 320M PLL is used */
CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
/* Configure 320M PLL */
switch (xtal_freq) {
case RTC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
div_ref = 1;
div7_0 = 6;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
default:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
}
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
}
uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
uint8_t i2c_bbpll_div_7_0 = div7_0;
uint8_t i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
@ -241,8 +176,8 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
int per_conf = DPORT_CPUPERIOD_SEL_80;
if (cpu_freq_mhz == 80) {
/* nothing to do */
} else if (cpu_freq_mhz == 160) {
per_conf = DPORT_CPUPERIOD_SEL_160;
} else if (cpu_freq_mhz == 120) {
per_conf = DPORT_CPUPERIOD_SEL_120;
} else {
SOC_LOGE(TAG, "invalid frequency");
abort();
@ -250,7 +185,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
rtc_clk_apb_freq_update(80 * MHZ);
rtc_clk_apb_freq_update(40 * MHZ);
ets_update_cpu_frequency(cpu_freq_mhz);
}
@ -277,11 +212,11 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
source = RTC_CPU_FREQ_SRC_PLL;
source_freq_mhz = RTC_PLL_FREQ_480M;
divider = 6;
} else if (freq_mhz == 160) {
} else if (freq_mhz == 120) {
real_freq_mhz = freq_mhz;
source = RTC_CPU_FREQ_SRC_PLL;
source_freq_mhz = RTC_PLL_FREQ_480M;
divider = 3;
divider = 4;
} else {
// unsupported frequency
return false;
@ -335,15 +270,13 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
case DPORT_SOC_CLK_SEL_PLL: {
source = RTC_CPU_FREQ_SRC_PLL;
uint32_t cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL);
uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M;
source_freq_mhz = RTC_PLL_FREQ_480M; // PLL clock on ESP8684 was fixed to 480MHz
if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4;
div = 6;
freq_mhz = 80;
} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 3 : 2;
div = 3;
freq_mhz = 160;
} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_120) {
div = 4;
freq_mhz = 120;
} else {
SOC_LOGE(TAG, "unsupported frequency configuration");
abort();

2
components/esp_hw_support/port/esp8684/rtc_clk_common.h
View File

@ -9,7 +9,7 @@
#define MHZ (1000000)
#define DPORT_CPUPERIOD_SEL_80 0
#define DPORT_CPUPERIOD_SEL_160 1
#define DPORT_CPUPERIOD_SEL_120 1
#define DPORT_SOC_CLK_SEL_XTAL 0
#define DPORT_SOC_CLK_SEL_PLL 1

2
components/esp_system/port/soc/esp8684/clk.c
View File

@ -68,7 +68,7 @@ static const char *TAG = "clk";
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
soc_reset_reason_t rst_reas;
rst_reas = esp_rom_get_reset_reason(0);
if (rst_reas == POWERON_RESET) {
if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
cfg.cali_ocode = 1;
}
rtc_init(cfg);

12
components/soc/esp8684/include/soc/rtc.h
View File

@ -129,7 +129,6 @@ storing in efuse (based on ATE 5k ECO3 chips)
* Enum values should be equal to frequency in MHz.
*/
typedef enum {
RTC_XTAL_FREQ_32M = 32,
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
} rtc_xtal_freq_t;
@ -139,12 +138,9 @@ typedef enum {
typedef enum {
RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency
RTC_CPU_FREQ_80M = 1, //!< 80 MHz
RTC_CPU_FREQ_160M = 2, //!< 160 MHz
RTC_CPU_FREQ_240M = 3, //!< 240 MHz
RTC_CPU_FREQ_2M = 4, //!< 2 MHz
RTC_CPU_320M_80M = 5, //!< for test
RTC_CPU_320M_160M = 6, //!< for test
RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset
RTC_CPU_FREQ_120M = 2, //!< 120 MHz
RTC_CPU_FREQ_160M = 3, //!< 160 MHz
RTC_CPU_FREQ_XTAL_DIV2 = 4, //!< XTAL/2 after reset
} rtc_cpu_freq_t;
/**
@ -152,7 +148,7 @@ typedef enum {
*/
typedef enum {
RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M)
RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M)
RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator
RTC_CPU_FREQ_SRC_APLL //!< APLL
} rtc_cpu_freq_src_t;