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https://github.com/espressif/esp-idf.git
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Merge branch 'feat/c5mp_i2s_support' into 'master'
feat(i2s): c5mp i2s support Closes IDF-8713 and IDF-8714 See merge request espressif/esp-idf!30828
This commit is contained in:
Wan Lei
commit
8778917cb0
@ -22,6 +22,7 @@
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#include "soc/lldesc.h"
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#include "driver/gpio.h"
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#include "esp_private/gpio.h"
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#include "hal/gpio_hal.h"
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#include "driver/i2s_types_legacy.h"
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#include "hal/i2s_hal.h"
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@ -1849,7 +1850,7 @@ static void gpio_matrix_out_check_and_set(gpio_num_t gpio, uint32_t signal_idx,
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{
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//if pin = -1, do not need to configure
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if (gpio != -1) {
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
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gpio_func_sel(gpio, PIN_FUNC_GPIO);
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gpio_set_direction(gpio, GPIO_MODE_OUTPUT);
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esp_rom_gpio_connect_out_signal(gpio, signal_idx, out_inv, oen_inv);
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}
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@ -1858,7 +1859,7 @@ static void gpio_matrix_out_check_and_set(gpio_num_t gpio, uint32_t signal_idx,
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static void gpio_matrix_in_check_and_set(gpio_num_t gpio, uint32_t signal_idx, bool inv)
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{
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if (gpio != -1) {
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
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gpio_func_sel(gpio, PIN_FUNC_GPIO);
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/* Set direction, for some GPIOs, the input function are not enabled as default */
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gpio_set_direction(gpio, GPIO_MODE_INPUT);
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esp_rom_gpio_connect_in_signal(gpio, signal_idx, inv);
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@ -22,6 +22,7 @@
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#include "soc/i2s_periph.h"
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#include "soc/soc_caps.h"
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#include "driver/gpio.h"
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#include "esp_private/gpio.h"
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#include "hal/gpio_hal.h"
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#include "unity.h"
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#include "math.h"
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@ -47,9 +48,9 @@
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static void i2s_test_io_config(int mode)
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{
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// Connect internal signals using IO matrix.
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_BCK_IO], PIN_FUNC_GPIO);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_WS_IO], PIN_FUNC_GPIO);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[DATA_OUT_IO], PIN_FUNC_GPIO);
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gpio_func_sel(MASTER_BCK_IO, PIN_FUNC_GPIO);
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gpio_func_sel(MASTER_WS_IO, PIN_FUNC_GPIO);
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gpio_func_sel(DATA_OUT_IO, PIN_FUNC_GPIO);
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gpio_set_direction(MASTER_BCK_IO, GPIO_MODE_INPUT_OUTPUT);
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gpio_set_direction(MASTER_WS_IO, GPIO_MODE_INPUT_OUTPUT);
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@ -869,7 +870,7 @@ static void i2s_test_common_sample_rate(i2s_port_t id)
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TEST_ESP_OK(pcnt_unit_enable(pcnt_unit));
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// Reconfig GPIO signal
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_WS_IO], PIN_FUNC_GPIO);
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gpio_func_sel(MASTER_WS_IO, PIN_FUNC_GPIO);
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gpio_set_direction(MASTER_WS_IO, GPIO_MODE_INPUT_OUTPUT);
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esp_rom_gpio_connect_out_signal(MASTER_WS_IO, i2s_periph_signal[0].m_tx_ws_sig, 0, 0);
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esp_rom_gpio_connect_in_signal(MASTER_WS_IO, pcnt_periph_signals.groups[0].units[0].channels[0].pulse_sig, 0);
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@ -42,6 +42,7 @@
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#include "esp_private/esp_clk.h"
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#include "driver/gpio.h"
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#include "esp_private/gpio.h"
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#include "driver/i2s_common.h"
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#include "i2s_private.h"
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@ -789,7 +790,7 @@ void i2s_gpio_check_and_set(i2s_chan_handle_t handle, int gpio, uint32_t signal_
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{
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/* Ignore the pin if pin = I2S_GPIO_UNUSED */
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if (gpio != (int)I2S_GPIO_UNUSED) {
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
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gpio_func_sel(gpio, PIN_FUNC_GPIO);
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if (is_input) {
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/* Set direction, for some GPIOs, the input function are not enabled as default */
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gpio_set_direction(gpio, GPIO_MODE_INPUT);
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@ -806,7 +807,7 @@ void i2s_gpio_loopback_set(i2s_chan_handle_t handle, int gpio, uint32_t out_sig_
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{
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if (gpio != (int)I2S_GPIO_UNUSED) {
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i2s_output_gpio_reserve(handle, gpio);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
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gpio_func_sel(gpio, PIN_FUNC_GPIO);
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gpio_set_direction(gpio, GPIO_MODE_INPUT_OUTPUT);
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esp_rom_gpio_connect_out_signal(gpio, out_sig_idx, 0, 0);
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esp_rom_gpio_connect_in_signal(gpio, in_sig_idx, 0);
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@ -14,6 +14,7 @@
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#include "sdkconfig.h"
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#include "driver/gpio.h"
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#include "hal/gpio_hal.h"
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#include "esp_private/gpio.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "unity.h"
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@ -71,9 +72,9 @@
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static void i2s_test_io_config(int mode)
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{
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// Connect internal signals using IO matrix.
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_BCK_IO], PIN_FUNC_GPIO);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_WS_IO], PIN_FUNC_GPIO);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[DATA_OUT_IO], PIN_FUNC_GPIO);
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gpio_func_sel(MASTER_BCK_IO, PIN_FUNC_GPIO);
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gpio_func_sel(MASTER_WS_IO, PIN_FUNC_GPIO);
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gpio_func_sel(DATA_OUT_IO, PIN_FUNC_GPIO);
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gpio_set_direction(MASTER_BCK_IO, GPIO_MODE_INPUT_OUTPUT);
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gpio_set_direction(MASTER_WS_IO, GPIO_MODE_INPUT_OUTPUT);
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@ -745,7 +746,7 @@ static void i2s_test_common_sample_rate(i2s_chan_handle_t rx_chan, i2s_std_clk_c
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TEST_ESP_OK(pcnt_unit_enable(pcnt_unit));
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// Reconfig GPIO signal
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_WS_IO], PIN_FUNC_GPIO);
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gpio_func_sel(MASTER_WS_IO, PIN_FUNC_GPIO);
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gpio_set_direction(MASTER_WS_IO, GPIO_MODE_INPUT_OUTPUT);
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esp_rom_gpio_connect_out_signal(MASTER_WS_IO, i2s_periph_signal[0].m_rx_ws_sig, 0, 0);
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esp_rom_gpio_connect_in_signal(MASTER_WS_IO, pcnt_periph_signals.groups[0].units[0].channels[0].pulse_sig, 0);
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@ -54,6 +54,14 @@ extern "C" {
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#define SLAVE_WS_IO 23
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#define DATA_IN_IO 47
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#define DATA_OUT_IO 48
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#elif CONFIG_IDF_TARGET_ESP32C5
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#define MASTER_MCK_IO 6
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#define MASTER_BCK_IO 8
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#define MASTER_WS_IO 9
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#define SLAVE_BCK_IO 23
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#define SLAVE_WS_IO 24
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#define DATA_IN_IO 10
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#define DATA_OUT_IO 25
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#else
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#define MASTER_MCK_IO 0
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#define MASTER_BCK_IO 4
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1196
components/hal/esp32c5/include/hal/i2s_ll.h
Normal file
1196
components/hal/esp32c5/include/hal/i2s_ll.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -40,7 +40,7 @@ typedef struct {
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i2s_std_slot_mask_t slot_mask; /*!< Select the left, right or both slot */
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uint32_t ws_width; /*!< WS signal width (i.e. the number of bclk ticks that ws signal is high) */
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bool ws_pol; /*!< WS signal polarity, set true to enable high lever first */
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bool bit_shift; /*!< Set to enbale bit shift in Philips mode */
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bool bit_shift; /*!< Set to enable bit shift in Philips mode */
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#if SOC_I2S_HW_VERSION_1 // For esp32/esp32-s2
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bool msb_right; /*!< Set to place right channel data at the MSB in the FIFO */
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#else
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@ -350,7 +350,7 @@ void i2s_hal_tdm_enable_rx_channel(i2s_hal_context_t *hal);
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#define i2s_hal_rx_reset_fifo(hal) i2s_ll_rx_reset_fifo((hal)->dev)
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#if !SOC_I2S_SUPPORTS_GDMA
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#if !SOC_GDMA_SUPPORTED
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/**
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* @brief Enable I2S TX DMA
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*
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35
components/soc/esp32c5/mp/i2s_periph.c
Normal file
35
components/soc/esp32c5/mp/i2s_periph.c
Normal file
@ -0,0 +1,35 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/i2s_periph.h"
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#include "soc/gpio_sig_map.h"
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/*
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Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
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*/
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const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
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{
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.mck_out_sig = I2S_MCLK_OUT_IDX,
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.mck_in_sig = I2S_MCLK_IN_IDX,
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.m_tx_bck_sig = I2SO_BCK_OUT_IDX,
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.m_rx_bck_sig = I2SI_BCK_OUT_IDX,
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.m_tx_ws_sig = I2SO_WS_OUT_IDX,
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.m_rx_ws_sig = I2SI_WS_OUT_IDX,
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.s_tx_bck_sig = I2SO_BCK_IN_IDX,
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.s_rx_bck_sig = I2SI_BCK_IN_IDX,
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.s_tx_ws_sig = I2SO_WS_IN_IDX,
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.s_rx_ws_sig = I2SI_WS_IN_IDX,
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.data_out_sigs[0] = I2SO_SD_OUT_IDX,
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.data_out_sigs[1] = I2SO_SD1_OUT_IDX,
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.data_in_sig = I2SI_SD_IN_IDX,
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.irq = ETS_I2S1_INTR_SOURCE,
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.module = -1,
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}
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};
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@ -43,6 +43,10 @@ config SOC_RTC_MEM_SUPPORTED
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bool
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default y
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config SOC_I2S_SUPPORTED
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bool
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default y
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config SOC_GPSPI_SUPPORTED
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bool
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default y
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@ -215,6 +219,54 @@ config SOC_HP_I2C_NUM
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int
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default 1
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config SOC_I2S_NUM
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int
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default 1
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config SOC_I2S_HW_VERSION_2
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bool
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default y
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config SOC_I2S_SUPPORTS_TX_SYNC_CNT
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bool
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default y
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config SOC_I2S_SUPPORTS_XTAL
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bool
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default y
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config SOC_I2S_SUPPORTS_PLL_F160M
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bool
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default y
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config SOC_I2S_SUPPORTS_PLL_F240M
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bool
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default y
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config SOC_I2S_SUPPORTS_PCM
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bool
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default y
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config SOC_I2S_SUPPORTS_PDM
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bool
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default y
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config SOC_I2S_SUPPORTS_PDM_TX
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bool
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default y
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config SOC_I2S_PDM_MAX_TX_LINES
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int
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default 2
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config SOC_I2S_SUPPORTS_TDM
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bool
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default y
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config SOC_I2S_TDM_FULL_DATA_WIDTH
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bool
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default y
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config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
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bool
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default y
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@ -315,15 +315,16 @@ typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
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/**
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* @brief Array initializer for all supported clock sources of I2S
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*/
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#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
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#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_PLL_F240M, I2S_CLK_SRC_EXTERNAL}
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/**
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* @brief I2S clock source enum
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*/
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typedef enum { // TODO: [ESP32C5] IDF-8713 (inherit from C6)
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typedef enum {
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
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I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
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I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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I2S_CLK_SRC_PLL_240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
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I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
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I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
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} soc_periph_i2s_clk_src_t;
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@ -267,117 +267,33 @@ typedef union {
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uint32_t val;
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} i2s_rx_recomb_ctrl_reg_t;
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/** Type of rx_recomb_dma_ch0 register
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/** Type of rx_recomb_dma_chn register
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* I2S RX recombined-dma-channel configuration register
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*/
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typedef union {
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struct {
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/** rx_recomb_dma_ch0_valid : R/W; bitpos: [0]; default: 0;
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/** rx_recomb_dma_ch_valid : R/W; bitpos: [0]; default: 0;
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* Set this bit to enable the adc-dma-channel.
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*/
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uint32_t rx_recomb_dma_ch0_valid:1;
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/** rx_recomb_dma_ch0_style : R/W; bitpos: [4:1]; default: 0;
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uint32_t rx_recomb_dma_ch_valid:1;
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/** rx_recomb_dma_ch_style : R/W; bitpos: [4:1]; default: 0;
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* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
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* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
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*/
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uint32_t rx_recomb_dma_ch0_style:4;
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/** rx_recomb_dma_ch0_order : R/W; bitpos: [12:5]; default: 0;
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uint32_t rx_recomb_dma_ch_style:4;
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/** rx_recomb_dma_ch_order : R/W; bitpos: [12:5]; default: 0;
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* Set this field to set the recombined-dma-channel order. If choose to use the order
|
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* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
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*/
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uint32_t rx_recomb_dma_ch0_order:8;
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/** rx_recomb_dma_ch0_eof_num : R/W; bitpos: [28:13]; default: 0;
|
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uint32_t rx_recomb_dma_ch_order:8;
|
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/** rx_recomb_dma_ch_eof_num : R/W; bitpos: [28:13]; default: 0;
|
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* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
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*/
|
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uint32_t rx_recomb_dma_ch0_eof_num:16;
|
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uint32_t rx_recomb_dma_ch_eof_num:16;
|
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uint32_t reserved_29:3;
|
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};
|
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uint32_t val;
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} i2s_rx_recomb_dma_ch0_reg_t;
|
||||
|
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/** Type of rx_recomb_dma_ch1 register
|
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* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_recomb_dma_ch1_valid : R/W; bitpos: [0]; default: 0;
|
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* Set this bit to enable the adc-dma-channel.
|
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*/
|
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uint32_t rx_recomb_dma_ch1_valid:1;
|
||||
/** rx_recomb_dma_ch1_style : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch1_style:4;
|
||||
/** rx_recomb_dma_ch1_order : R/W; bitpos: [12:5]; default: 0;
|
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* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch1_order:8;
|
||||
/** rx_recomb_dma_ch1_eof_num : R/W; bitpos: [28:13]; default: 0;
|
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* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch1_eof_num:16;
|
||||
uint32_t reserved_29:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rx_recomb_dma_ch1_reg_t;
|
||||
|
||||
/** Type of rx_recomb_dma_ch2 register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_recomb_dma_ch2_valid : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch2_valid:1;
|
||||
/** rx_recomb_dma_ch2_style : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch2_style:4;
|
||||
/** rx_recomb_dma_ch2_order : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch2_order:8;
|
||||
/** rx_recomb_dma_ch2_eof_num : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch2_eof_num:16;
|
||||
uint32_t reserved_29:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rx_recomb_dma_ch2_reg_t;
|
||||
|
||||
/** Type of rx_recomb_dma_ch3 register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_recomb_dma_ch3_valid : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch3_valid:1;
|
||||
/** rx_recomb_dma_ch3_style : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch3_style:4;
|
||||
/** rx_recomb_dma_ch3_order : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch3_order:8;
|
||||
/** rx_recomb_dma_ch3_eof_num : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch3_eof_num:16;
|
||||
uint32_t reserved_29:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rx_recomb_dma_ch3_reg_t;
|
||||
} i2s_rx_recomb_dma_chn_reg_t;
|
||||
|
||||
/** Type of rx_pdm2pcm_conf register
|
||||
* I2S RX configure register
|
||||
@ -510,7 +426,7 @@ typedef union {
|
||||
uint32_t val;
|
||||
} i2s_rx_tdm_ctrl_reg_t;
|
||||
|
||||
/** Type of rxeof_num register
|
||||
/** Type of rx_eof_num register
|
||||
* I2S RX data number control register.
|
||||
*/
|
||||
typedef union {
|
||||
@ -523,7 +439,7 @@ typedef union {
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rxeof_num_reg_t;
|
||||
} i2s_rx_eof_num_reg_t;
|
||||
|
||||
|
||||
/** Group: TX Control and configuration registers */
|
||||
@ -549,7 +465,7 @@ typedef union {
|
||||
*/
|
||||
uint32_t tx_slave_mod:1;
|
||||
/** tx_stop_en : R/W; bitpos: [4]; default: 1;
|
||||
* Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
|
||||
* Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
|
||||
*/
|
||||
uint32_t tx_stop_en:1;
|
||||
/** tx_chan_equal : R/W; bitpos: [5]; default: 0;
|
||||
@ -987,7 +903,7 @@ typedef union {
|
||||
uint32_t val;
|
||||
} i2s_lc_hung_conf_reg_t;
|
||||
|
||||
/** Type of conf_sigle_data register
|
||||
/** Type of conf_single_data register
|
||||
* I2S signal data register
|
||||
*/
|
||||
typedef union {
|
||||
@ -998,7 +914,7 @@ typedef union {
|
||||
uint32_t single_data:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_conf_sigle_data_reg_t;
|
||||
} i2s_conf_single_data_reg_t;
|
||||
|
||||
|
||||
/** Group: TX status registers */
|
||||
@ -1119,10 +1035,7 @@ typedef struct {
|
||||
volatile i2s_rx_conf1_reg_t rx_conf1;
|
||||
volatile i2s_tx_conf1_reg_t tx_conf1;
|
||||
volatile i2s_rx_recomb_ctrl_reg_t rx_recomb_ctrl;
|
||||
volatile i2s_rx_recomb_dma_ch0_reg_t rx_recomb_dma_ch0;
|
||||
volatile i2s_rx_recomb_dma_ch1_reg_t rx_recomb_dma_ch1;
|
||||
volatile i2s_rx_recomb_dma_ch2_reg_t rx_recomb_dma_ch2;
|
||||
volatile i2s_rx_recomb_dma_ch3_reg_t rx_recomb_dma_ch3;
|
||||
volatile i2s_rx_recomb_dma_chn_reg_t rx_recomb_dma_ch[4];
|
||||
volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
|
||||
volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
|
||||
volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
|
||||
@ -1131,8 +1044,8 @@ typedef struct {
|
||||
volatile i2s_rx_timing_reg_t rx_timing;
|
||||
volatile i2s_tx_timing_reg_t tx_timing;
|
||||
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
|
||||
volatile i2s_rxeof_num_reg_t rxeof_num;
|
||||
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
|
||||
volatile i2s_rx_eof_num_reg_t rx_eof_num;
|
||||
volatile i2s_conf_single_data_reg_t conf_single_data;
|
||||
volatile i2s_state_reg_t state;
|
||||
volatile i2s_etm_conf_reg_t etm_conf;
|
||||
volatile i2s_fifo_cnt_reg_t fifo_cnt;
|
||||
@ -1141,7 +1054,7 @@ typedef struct {
|
||||
volatile i2s_date_reg_t date;
|
||||
} i2s_dev_t;
|
||||
|
||||
extern i2s_dev_t I2S;
|
||||
extern i2s_dev_t I2S0;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
|
||||
|
||||
@ -38,7 +38,7 @@
|
||||
#define SOC_EFUSE_SUPPORTED 1
|
||||
#define SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_MEM_SUPPORTED 1
|
||||
// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8726
|
||||
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687
|
||||
#define SOC_GPSPI_SUPPORTED 1
|
||||
@ -259,15 +259,19 @@
|
||||
// #define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
|
||||
|
||||
/*-------------------------- I2S CAPS ----------------------------------------*/
|
||||
// #define SOC_I2S_NUM (1U)
|
||||
// #define SOC_I2S_HW_VERSION_2 (1)
|
||||
// #define SOC_I2S_SUPPORTS_XTAL (1)
|
||||
// #define SOC_I2S_SUPPORTS_PLL_F160M (1)
|
||||
// #define SOC_I2S_SUPPORTS_PCM (1)
|
||||
// #define SOC_I2S_SUPPORTS_PDM (1)
|
||||
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
|
||||
// #define SOC_I2S_PDM_MAX_TX_LINES (2)
|
||||
// #define SOC_I2S_SUPPORTS_TDM (1)
|
||||
#define SOC_I2S_NUM (1U)
|
||||
#define SOC_I2S_HW_VERSION_2 (1)
|
||||
#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1)
|
||||
// #define SOC_I2S_SUPPORTS_RX_RECOMB (1) //TODO[C5] IDF-9966
|
||||
#define SOC_I2S_SUPPORTS_XTAL (1)
|
||||
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
|
||||
#define SOC_I2S_SUPPORTS_PLL_F240M (1)
|
||||
#define SOC_I2S_SUPPORTS_PCM (1)
|
||||
#define SOC_I2S_SUPPORTS_PDM (1)
|
||||
#define SOC_I2S_SUPPORTS_PDM_TX (1)
|
||||
#define SOC_I2S_PDM_MAX_TX_LINES (2)
|
||||
#define SOC_I2S_SUPPORTS_TDM (1)
|
||||
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
// TODO: [ESP32C5] 8684
|
||||
|
||||
@ -17,7 +17,7 @@ PROVIDE ( TIMERG0 = 0x60008000 );
|
||||
PROVIDE ( TIMERG1 = 0x60009000 );
|
||||
PROVIDE ( SYSTIMER = 0x6000A000 );
|
||||
PROVIDE ( TWAI0 = 0x6000B000 );
|
||||
PROVIDE ( I2S = 0x6000C000 );
|
||||
PROVIDE ( I2S0 = 0x6000C000 );
|
||||
PROVIDE ( TWAI1 = 0x6000D000 );
|
||||
PROVIDE ( APB_SARADC = 0x6000E000 );
|
||||
PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
|
||||
|
||||
@ -111,7 +111,6 @@ api-reference/peripherals/usb_device.rst
|
||||
api-reference/peripherals/sdspi_host.rst
|
||||
api-reference/peripherals/spi_slave.rst
|
||||
api-reference/peripherals/etm.rst
|
||||
api-reference/peripherals/i2s.rst
|
||||
api-reference/peripherals/gptimer.rst
|
||||
api-reference/peripherals/pcnt.rst
|
||||
api-reference/peripherals/touch_element.rst
|
||||
|
||||
@ -74,14 +74,18 @@ Clock Source
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_DEFAULT`: Default PLL clock.
|
||||
|
||||
.. only:: not esp32h2
|
||||
.. only:: SOC_I2S_SUPPORTS_PLL_F160M
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`: 160 MHz PLL clock.
|
||||
|
||||
.. only:: esp32h2
|
||||
.. only:: SOC_I2S_SUPPORTS_PLL_F96M
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`: 96 MHz PLL clock.
|
||||
|
||||
.. only:: SOC_I2S_SUPPORTS_PLL_F240M
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_240M`: 240 MHz PLL clock.
|
||||
|
||||
.. only:: SOC_I2S_SUPPORTS_APLL
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_APLL`: Audio PLL clock, which is more precise than ``I2S_CLK_SRC_PLL_160M`` in high sample rate applications. Its frequency is configurable according to the sample rate. However, if APLL has been occupied by EMAC or other channels, the APLL frequency cannot be changed, and the driver will try to work under this APLL frequency. If this frequency cannot meet the requirements of I2S, the clock configuration will fail.
|
||||
@ -117,6 +121,7 @@ ESP32-C6 I2S 0 I2S 0 none I2S 0 none none
|
||||
ESP32-S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 none none
|
||||
ESP32-H2 I2S 0 I2S 0 none I2S 0 none none
|
||||
ESP32-P4 I2S 0~2 I2S 0 I2S 0 I2S 0~2 none none
|
||||
ESP32-C5 I2S 0 I2S 0 none I2S 0 none none
|
||||
========= ======== ======== ======== ======== ======== ==========
|
||||
|
||||
Standard Mode
|
||||
|
||||
@ -74,14 +74,18 @@ I2S 时钟
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_DEFAULT`：默认 PLL 时钟。
|
||||
|
||||
.. only:: not esp32h2
|
||||
.. only:: SOC_I2S_SUPPORTS_PLL_F160M
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`：160 MHz PLL 时钟。
|
||||
|
||||
.. only:: esp32h2
|
||||
.. only:: SOC_I2S_SUPPORTS_PLL_F96M
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`：96 MHz PLL 时钟。
|
||||
|
||||
.. only:: SOC_I2S_SUPPORTS_PLL_F240M
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_240M`：240 MHz PLL 时钟。
|
||||
|
||||
.. only:: SOC_I2S_SUPPORTS_APLL
|
||||
|
||||
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_APLL`：音频 PLL 时钟，在高采样率应用中比 ``I2S_CLK_SRC_PLL_160M`` 更精确。其频率可根据采样率进行配置，但如果 APLL 已经被 EMAC 或其他通道占用，则无法更改 APLL 频率，驱动程序将尝试在原有 APLL 频率下工作。如果原有 APLL 频率无法满足 I2S 的需求，时钟配置将失败。
|
||||
@ -117,6 +121,7 @@ ESP32-C6 I2S 0 I2S 0 无 I2S 0 无 无
|
||||
ESP32-S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 无 无
|
||||
ESP32-H2 I2S 0 I2S 0 无 I2S 0 无 无
|
||||
ESP32-P4 I2S 0~2 I2S 0 I2S 0 I2S 0~2 无 无
|
||||
ESP32-C5 I2S 0 I2S 0 无 I2S 0 无 无
|
||||
========= ======== ======== ======== ======== ======== ==========
|
||||
|
||||
标准模式
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
# SPDX-License-Identifier: CC0-1.0
|
||||
import pytest
|
||||
from pytest_embedded import Dut
|
||||
@ -19,13 +19,14 @@ from pytest_embedded import Dut
|
||||
def test_i2s_pdm_tx_example(dut: Dut) -> None:
|
||||
dut.expect(r'I2S PDM TX example start', timeout=5)
|
||||
dut.expect(r'---------------------------', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_pdm: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_pdm: The tx channel on I2S0 has been initialized to PDM TX mode successfully', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled', timeout=5)
|
||||
# TODO: IDF-10007, reopen
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_pdm: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_pdm: The tx channel on I2S0 has been initialized to PDM TX mode successfully', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled', timeout=5)
|
||||
dut.expect(r'Playing bass `twinkle twinkle little star`', timeout=5)
|
||||
|
||||
|
||||
@ -41,10 +42,11 @@ def test_i2s_pdm_tx_example(dut: Dut) -> None:
|
||||
def test_i2s_pdm_rx_example(dut: Dut) -> None:
|
||||
dut.expect(r'I2S PDM RX example start', timeout=5)
|
||||
dut.expect(r'---------------------------', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled', timeout=5)
|
||||
# TODO: IDF-10007, reopen
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled', timeout=5)
|
||||
dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5)
|
||||
dut.expect(r'-----------------------------------', timeout=5)
|
||||
dut.expect(r'\[0\] ([-]?[0-9]+) \[1\] ([-]?[0-9]+) \[2\] ([-]?[0-9]+) \[3\] ([-]?[0-9]+)', timeout=5)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
# SPDX-License-Identifier: CC0-1.0
|
||||
import pytest
|
||||
from pytest_embedded import Dut
|
||||
@ -14,24 +14,25 @@ from pytest_embedded import Dut
|
||||
@pytest.mark.generic
|
||||
def test_i2s_basic_example(dut: Dut) -> None:
|
||||
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_std: The tx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_std: The rx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
|
||||
chan_enable_pattern = [
|
||||
r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled',
|
||||
r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled'
|
||||
]
|
||||
dut.expect(chan_enable_pattern, timeout=5)
|
||||
dut.expect(chan_enable_pattern, timeout=5)
|
||||
# TODO: IDF-10007, reopen
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_std: The tx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_std: The rx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
|
||||
# chan_enable_pattern = [
|
||||
# r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled',
|
||||
# r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled'
|
||||
# ]
|
||||
# dut.expect(chan_enable_pattern, timeout=5)
|
||||
# dut.expect(chan_enable_pattern, timeout=5)
|
||||
dut.expect(r'Write Task: i2s write ([0-9]+) bytes', timeout=5)
|
||||
dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5)
|
||||
dut.expect(r'-----------------------------------', timeout=5)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
# SPDX-License-Identifier: CC0-1.0
|
||||
import pytest
|
||||
from pytest_embedded import Dut
|
||||
@ -12,24 +12,25 @@ from pytest_embedded import Dut
|
||||
@pytest.mark.generic
|
||||
def test_i2s_tdm_example(dut: Dut) -> None:
|
||||
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_tdm: The tx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
dut.expect(r'D \(([0-9]+)\) i2s_tdm: The rx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
|
||||
chan_enable_pattern = [
|
||||
r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled',
|
||||
r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled'
|
||||
]
|
||||
dut.expect(chan_enable_pattern, timeout=5)
|
||||
dut.expect(chan_enable_pattern, timeout=5)
|
||||
# TODO: IDF-10007, reopen
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: The tx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
|
||||
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
|
||||
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
|
||||
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: The rx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
|
||||
# chan_enable_pattern = [
|
||||
# r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled',
|
||||
# r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled'
|
||||
# ]
|
||||
# dut.expect(chan_enable_pattern, timeout=5)
|
||||
# dut.expect(chan_enable_pattern, timeout=5)
|
||||
dut.expect(r'Write Task: i2s write ([0-9]+) bytes', timeout=5)
|
||||
dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5)
|
||||
dut.expect(r'-----------------------------------', timeout=5)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user