diff --git a/components/esp_hw_support/port/esp32/rtc_time.c b/components/esp_hw_support/port/esp32/rtc_time.c
index 95b59789ee..8345c55d4a 100644
--- a/components/esp_hw_support/port/esp32/rtc_time.c
+++ b/components/esp_hw_support/port/esp32/rtc_time.c
@@ -135,8 +135,14 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
 uint64_t rtc_time_get(void)
 {
     SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
+    int attempts = 1000;
     while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
         esp_rom_delay_us(1); // might take 1 RTC slowclk period, don't flood RTC bus
+        if (attempts) {
+            if (--attempts == 0 && REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN)) {
+                SOC_LOGE(TAG, "rtc_time_get() 32kHz xtal has been stopped");
+            }
+        }
     }
     SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR);
     uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
@@ -155,8 +161,14 @@ void rtc_clk_wait_for_slow_cycle(void)
     REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0);
     REG_SET_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
     esp_rom_delay_us(1); /* RDY needs some time to go low */
+    int attempts = 1000;
     while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
         esp_rom_delay_us(1);
+        if (attempts) {
+            if (--attempts == 0 && REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN)) {
+                SOC_LOGE(TAG, "32kHz xtal has been stopped");
+            }
+        }
     }
 }