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doc(spi_flash): hide unsupported optional features
This commit is contained in:
Xiao Xufeng
parent
7bfc2b0418
commit
87182c9c76
@ -101,7 +101,6 @@ menu "Bootloader config"
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config BOOTLOADER_FLASH_XMC_SUPPORT
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config BOOTLOADER_FLASH_XMC_SUPPORT
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bool "Enable the support for flash chips of XMC (READ DOCS FIRST)"
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bool "Enable the support for flash chips of XMC (READ DOCS FIRST)"
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default y
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default y
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depends on !IDF_ENV_BRINGUP
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help
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help
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Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
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Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
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XMC chips will be forbidden to be used, when this option is disabled.
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XMC chips will be forbidden to be used, when this option is disabled.
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@ -119,7 +118,7 @@ menu "Bootloader config"
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config BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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config BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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bool
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bool
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default y if ESPTOOLPY_OCT_FLASH && SPI_FLASH_32BIT_ADDRESS
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default y if ESPTOOLPY_OCT_FLASH && BOOTLOADER_FLASH_32BIT_ADDR
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default n
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default n
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endmenu
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endmenu
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@ -24,6 +24,4 @@ CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE CONFIG_SECURE_FLASH_
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# Secure Boot Scheme
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# Secure Boot Scheme
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CONFIG_SECURE_BOOT_ENABLED CONFIG_SECURE_BOOT_V1_ENABLED
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CONFIG_SECURE_BOOT_ENABLED CONFIG_SECURE_BOOT_V1_ENABLED
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CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
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CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
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CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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@ -96,7 +96,7 @@ extern const bootloader_qio_info_t __attribute__((weak)) bootloader_flash_qe_sup
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*/
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*/
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esp_err_t IRAM_ATTR __attribute__((weak)) bootloader_flash_unlock(void);
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esp_err_t IRAM_ATTR __attribute__((weak)) bootloader_flash_unlock(void);
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#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
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#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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/**
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/**
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* @brief Enable 32bits address flash(larger than 16MB) can map to cache.
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* @brief Enable 32bits address flash(larger than 16MB) can map to cache.
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*
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*
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@ -487,7 +487,7 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
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return spi_to_esp_err(rc);
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return spi_to_esp_err(rc);
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}
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}
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#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
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#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode)
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void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode)
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{
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{
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esp_rom_opiflash_spi0rd_t cache_rd = {};
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esp_rom_opiflash_spi0rd_t cache_rd = {};
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@ -228,7 +228,7 @@ static esp_err_t bootloader_init_spi_flash(void)
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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bootloader_enable_qio_mode();
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bootloader_enable_qio_mode();
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#endif
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#endif
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#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
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#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
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bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
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#endif
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#endif
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print_flash_info(&bootloader_image_hdr);
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print_flash_info(&bootloader_image_hdr);
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@ -1,28 +1,6 @@
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menu "Main Flash configuration"
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menu "Main Flash configuration"
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depends on !APP_BUILD_TYPE_PURE_RAM_APP
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depends on !APP_BUILD_TYPE_PURE_RAM_APP
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menu "SPI Flash behavior when brownout"
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config SPI_FLASH_BROWNOUT_RESET_XMC
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bool "Enable sending reset when brownout for XMC flash chips"
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default y
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select SPI_FLASH_BROWNOUT_RESET
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help
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When this option is selected, the patch will be enabled for XMC.
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Follow the recommended flow by XMC for better stability.
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DO NOT DISABLE UNLESS YOU KNOW WHAT YOU ARE DOING.
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config SPI_FLASH_BROWNOUT_RESET
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bool
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default y
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select ESP_SYSTEM_BROWNOUT_INTR
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help
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When brownout happens during flash erase/write operations,
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send reset command to stop the flash operations to improve stability.
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endmenu
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menu "Optional and Experimental Features (READ DOCS FIRST)"
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menu "Optional and Experimental Features (READ DOCS FIRST)"
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comment "Features here require specific hardware (READ DOCS FIRST!)"
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comment "Features here require specific hardware (READ DOCS FIRST!)"
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@ -28,28 +28,29 @@ Some features are not supported on all ESP chips and Flash chips. You can check
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Auto Suspend & Resume
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Auto Suspend & Resume
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---------------------
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---------------------
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This feature is only supported on ESP32-C3 for now.
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The support for ESP32-S3 may be added in the future.
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.. only:: esp32c3
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.. only:: esp32c3
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You can refer to :ref:`auto-suspend` for more information about this feature. The support list is as follows.
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List of Flash chips that support this feature:
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ESP Chips List:
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1. XM25QxxC series.
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1. ESP32C3
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.. attention::
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Flash Chips List:
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There are multiple limitations about the auto-suspend feature, please do read :ref:`auto-suspend` for more information before you enable this feature.
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1. XM25QxxC series.
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Flash unique ID
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Flash unique ID
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---------------
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---------------
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This feature is supported on all Espressif chips.
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Unique ID is not flash id, which means flash has 64-Bit unique ID for each device. The instruction to read the unique ID (4Bh) accesses a factory-set read-only 64-bit number that is unique to each flash device. This ID number helps you to recognize each single device. Not all flash vendors support this feature. If you try to read the unique ID on a chip which does not have this feature, the behavior is not determined. The support list is as follows.
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Unique ID is not flash id, which means flash has 64-Bit unique ID for each device. The instruction to read the unique ID (4Bh) accesses a factory-set read-only 64-bit number that is unique to each flash device. This ID number helps you to recognize each single device. Not all flash vendors support this feature. If you try to read the unique ID on a chip which does not have this feature, the behavior is not determined. The support list is as follows.
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ESP Chips Lists:
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ALL
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List of Flash chips that support this feature:
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Flash Chips List:
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1. ISSI
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1. ISSI
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2. GD
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2. GD
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@ -62,72 +63,73 @@ Flash Chips List:
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High performance mode
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High performance mode
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---------------------
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---------------------
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.. note::
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This featuer is only supported on ESP32-S3 for now.
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This section is provided for Dual mode (DOUT/DIO) and Quad mode (QIO/QOUT) flash chips. Octal flash used on ESP-chips support High performance mode by default so far, you can refer to the octal flash support list below.
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The support for ESP32-S2, ESP32-C3 may be added in the future.
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High performance mode (HPM) means that the SPI1 and flash chip works under high frequency. Usually, when the operating frequency of the flash is greater than 80 MHz, it is considered that the flash works under HPM.
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.. only:: esp32s3
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As far as we acknowledged, there are more than three strategies for High Performance Mode (HPM) in typical SPI flash parts. For some flash chips, HPM is controlled by dummy cycle bit in the registers, while for other chips, it can be controlled by other bits (like HPM bit) in the register, or some special command. The difference in strategies requires the driver to explicitly add support for each chip.
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.. note::
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.. attention::
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This section is provided for Dual mode (DOUT/DIO) and Quad mode (QIO/QOUT) flash chips. Octal flash used on ESP-chips support High performance mode by default so far, you can refer to the octal flash support list below.
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It is hard to create several strategies to cover all situations, so all flash chips using HPM need to be supported explicitly. Therefore, if you try to use a flash not listed in :ref:`hpm_dc_support_list`, it might cause some error. So, when you try to use the flash chip beyond supported list, please test properly.
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High performance mode (HPM) means that the SPI1 and flash chip works under high frequency. Usually, when the operating frequency of the flash is greater than 80 MHz, it is considered that the flash works under HPM.
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Moreover, when the `Dummy Cycle adjustment` strategy is adopted by the flash chip, the flash remains in a state in which DC is different from the default value after a software reset. The sub mode of HPM that adjusts the dummy cycle to run at higher frequency in the application is called `HPM-DC`. `HPM-DC` feature needs a feature `DC Aware` to be enabled in the bootloader. Otherwise different DC value will forbid the 2nd bootloader from being boot up after reset.
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As far as we acknowledged, there are more than three strategies for High Performance Mode (HPM) in typical SPI flash parts. For some flash chips, HPM is controlled by dummy cycle bit in the registers, while for other chips, it can be controlled by other bits (like HPM bit) in the register, or some special command. The difference in strategies requires the driver to explicitly add support for each chip.
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To enable High Performance Mode:
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.. attention::
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1. De-select :ref:`CONFIG_ESPTOOLPY_OCT_FLASH`. HPM is not used for Octal flash, enabling related options may bypass HPM functions.
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It is hard to create several strategies to cover all situations, so all flash chips using HPM need to be supported explicitly. Therefore, if you try to use a flash not listed in :ref:`hpm_dc_support_list`, it might cause some error. So, when you try to use the flash chip beyond supported list, please test properly.
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2. Enable ``CONFIG_SPI_FLASH_HPM_ENA`` option.
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Moreover, when the `Dummy Cycle adjustment` strategy is adopted by the flash chip, the flash remains in a state in which DC is different from the default value after a software reset. The sub mode of HPM that adjusts the dummy cycle to run at higher frequency in the application is called `HPM-DC`. `HPM-DC` feature needs a feature `DC Aware` to be enabled in the bootloader. Otherwise different DC value will forbid the 2nd bootloader from being boot up after reset.
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3. Switch Flash frequency to HPM ones. For example, ``CONFIG_ESPTOOLPY_FLASHFREQ_120M``.
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To enable High Performance Mode:
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4. Make sure the config option for `HPM-DC` feature (under ``CONFIG_SPI_FLASH_HPM_DC`` choices) is selected correctly according to whether the bootloader supports `DC Aware`.
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1. De-select :ref:`CONFIG_ESPTOOLPY_OCT_FLASH`. HPM is not used for Octal flash, enabling related options may bypass HPM functions.
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- If bootloader supports `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_AUTO``. This allows the usage of flash chips that adopted `Dummy Cycle adjustment` strategy.
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2. Enable ``CONFIG_SPI_FLASH_HPM_ENA`` option.
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- If bootloader doesn't support `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_DISABLE``. It avoid consequences caused by running HPM-DC with non-DC-aware bootloaders. But please avoid using flash chips that adopts `Dummy Cycle adjustment` strategy if ``CONFIG_SPI_FLASH_HPM_DC_DISABLE`` is selected. See list of flash models that adpot DC strategy below.
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3. Switch Flash frequency to HPM ones. For example, ``CONFIG_ESPTOOLPY_FLASHFREQ_120M``.
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Check whether the bootloader supports `DC Aware` in the following way:
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4. Make sure the config option for `HPM-DC` feature (under ``CONFIG_SPI_FLASH_HPM_DC`` choices) is selected correctly according to whether the bootloader supports `DC Aware`.
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- If you are starting a new project, it's suggested to enable `DC Aware` by selecting :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` option in the bootloader menu. Please note that, you won't be able to modify this option via OTA, because the support is in the bootloader.
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- If bootloader supports `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_AUTO``. This allows the usage of flash chips that adopted `Dummy Cycle adjustment` strategy.
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- If you are working on an existing project and want to update `HPM-DC` config option in the app via OTA, check the sdkconfig file used to build your bootloader: (Upgrading ESP-IDF version may make this file different from the one used by bootloader to build.)
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- If bootloader doesn't support `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_DISABLE``. It avoid consequences caused by running HPM-DC with non-DC-aware bootloaders. But please avoid using flash chips that adopts `Dummy Cycle adjustment` strategy if ``CONFIG_SPI_FLASH_HPM_DC_DISABLE`` is selected. See list of flash models that adpot DC strategy below.
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- For latest version (ESP-IDF v4.4.7+, v5.2 and above), if :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` is selected, the bootloader supports `DC Aware`.
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Check whether the bootloader supports `DC Aware` in the following way:
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- For versions in this range: (v4.4.4-v4.4.6, v5.0+, and v5.1+), if ``CONFIG_ESPTOOLPY_FLASHFREQ_120M`` is selected, the bootloader supports `DC Aware`. In this case, enable :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` to confirm this (though it will not affect bootloader in devices in the field).
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- If you are starting a new project, it's suggested to enable `DC Aware` by selecting :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` option in the bootloader menu. Please note that, you won't be able to modify this option via OTA, because the support is in the bootloader.
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- For versions below v4.4.4, the bootloader doesn't support `DC Aware`.
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- If you are working on an existing project and want to update `HPM-DC` config option in the app via OTA, check the sdkconfig file used to build your bootloader: (Upgrading ESP-IDF version may make this file different from the one used by bootloader to build.)
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ESP Chips List:
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- For latest version (ESP-IDF v4.4.7+, v5.2 and above), if :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` is selected, the bootloader supports `DC Aware`.
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1. ESP32S3
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- For versions in this range: (v4.4.4-v4.4.6, v5.0+, and v5.1+), if ``CONFIG_ESPTOOLPY_FLASHFREQ_120M`` is selected, the bootloader supports `DC Aware`. In this case, enable :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` to confirm this (though it will not affect bootloader in devices in the field).
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(The SW support for other chips haven't been done yet)
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- For versions below v4.4.4, the bootloader doesn't support `DC Aware`.
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.. _hpm_dc_support_list:
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.. _hpm_dc_support_list:
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Quad Flash HPM support list
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Quad Flash HPM support list
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Flash chips that don't need HPM-DC:
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Flash chips that don't need HPM-DC:
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1. GD25Q64C (ID: 0xC84017)
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1. GD25Q64C (ID: 0xC84017)
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2. GD25Q32C (ID: 0xC84016)
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2. GD25Q32C (ID: 0xC84016)
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3. ZB25VQ32B (ID: 0x5E4016)
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3. ZB25VQ32B (ID: 0x5E4016)
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4. GD25LQ255E (ID: 0xC86019)
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Following flash chips also have HPM feature, but requires the bootloader to support `DC Aware`:
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Following flash chips also have HPM feature, but requires the bootloader to support `DC Aware`:
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1. GD25Q64E (ID: 0xC84017)
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1. GD25Q64E (ID: 0xC84017)
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2. GD25Q128E (ID: 0xC84018)
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2. GD25Q128E (ID: 0xC84018)
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OPI flash support
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OPI flash support
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-----------------
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-----------------
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This feature is only supporetd on ESP32-S3 for now.
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OPI flash means that the flash chip supports octal peripheral interface, which has octal I/O pins. Different octal flash has different configurations and different commands. Hence, it is necessary to carefully check the support list.
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OPI flash means that the flash chip supports octal peripheral interface, which has octal I/O pins. Different octal flash has different configurations and different commands. Hence, it is necessary to carefully check the support list.
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.. only:: esp32s3
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.. only:: esp32s3
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@ -136,28 +138,23 @@ OPI flash means that the flash chip supports octal peripheral interface, which h
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To know how to configure menuconfig for a board with different Flash and PSRAM, please refer to the :ref:`SPI Flash and External SPI RAM Configuration <flash-psram-configuration>`
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To know how to configure menuconfig for a board with different Flash and PSRAM, please refer to the :ref:`SPI Flash and External SPI RAM Configuration <flash-psram-configuration>`
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ESP Chips List:
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List of Flash chips that support this feature:
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1. ESP32S3
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1. MX25UM25645G
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2. MX25UM12345G
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Flash Chips List:
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1. MX25UM25645G
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32-bit Address Flash Chips
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32-bit Address Flash Chips
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--------------------------
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--------------------------
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This feature is supported on all Espressif chips (with various restrictions to application).
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Most NOR flash chips used by Espressif chips use 24-bits address, which can cover 16 MBytes memory. However, for larger memory (usually equal to or larger than 16 MBytes), flash uses a 32-bits address to address larger memory. Regretfully, 32-bits address chips have vendor-specific commands, so we need to support the chips one by one.
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Most NOR flash chips used by Espressif chips use 24-bits address, which can cover 16 MBytes memory. However, for larger memory (usually equal to or larger than 16 MBytes), flash uses a 32-bits address to address larger memory. Regretfully, 32-bits address chips have vendor-specific commands, so we need to support the chips one by one.
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ESP Chips List:
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List of Flash chips that support this feature:
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ALL ESP Chips support this.
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Flash Chips List:
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1. W25Q256
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1. W25Q256
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2. GD25Q256
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2. GD25Q256
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.. important::
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.. important::
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Over 16 MBytes space on flash mentioned above can be only used for ``data saving``, like file system. If your data/instructions over 16 MBytes spaces need to be mapped to MMU (so as to be accessed by the CPU), please upgrade to ESP-IDF v5.2 and read the latest docs.
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Over 16 MBytes space on flash mentioned above can be only used for ``data saving``, like file system. If your data/instructions over 16 MBytes spaces need to be mapped to MMU (so as to be accessed by the CPU), please upgrade to ESP-IDF v5.2 and read the latest docs.
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