From 80997d5860cbe14c4ca63ba24b7410840eab5a4a Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 25 Oct 2023 11:57:01 +0800 Subject: [PATCH] fix(i2c): read write FIFO memory by volatile --- components/hal/esp32c3/include/hal/i2c_ll.h | 28 +++------- components/hal/esp32c6/include/hal/i2c_ll.h | 14 ++--- components/hal/esp32h2/include/hal/i2c_ll.h | 22 +++----- components/hal/esp32p4/include/hal/i2c_ll.h | 26 ++++----- components/hal/esp32s3/include/hal/i2c_ll.h | 22 +++----- .../soc/esp32c3/include/soc/i2c_struct.h | 53 +++---------------- .../soc/esp32c6/include/soc/i2c_struct.h | 35 ++---------- .../soc/esp32h2/include/soc/i2c_struct.h | 35 ++---------- .../soc/esp32p4/include/soc/i2c_struct.h | 35 ++---------- .../soc/esp32s3/include/soc/i2c_struct.h | 36 ++----------- tools/ci/check_copyright_ignore.txt | 1 - 11 files changed, 53 insertions(+), 254 deletions(-) diff --git a/components/hal/esp32c3/include/hal/i2c_ll.h b/components/hal/esp32c3/include/hal/i2c_ll.h index f199940382..bce34f325f 100644 --- a/components/hal/esp32c3/include/hal/i2c_ll.h +++ b/components/hal/esp32c3/include/hal/i2c_ll.h @@ -24,7 +24,6 @@ extern "C" { #endif - /** * @brief I2C hardware cmd register fields. */ @@ -89,7 +88,7 @@ typedef enum { */ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal) { - uint32_t clkm_div = source_clk / (bus_freq * 1024) +1; + uint32_t clkm_div = source_clk / (bus_freq * 1024) + 1; uint32_t sclk_freq = source_clk / clkm_div; uint32_t half_cycle = sclk_freq / bus_freq / 2; //SCL @@ -98,7 +97,7 @@ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_f // default, scl_wait_high < scl_high // Make 80KHz as a boundary here, because when working at lower frequency, too much scl_wait_high will faster the frequency // according to some hardware behaviors. - clk_cal->scl_wait_high = (bus_freq >= 80*1000) ? (half_cycle / 2 - 2) : (half_cycle / 4); + clk_cal->scl_wait_high = (bus_freq >= 80 * 1000) ? (half_cycle / 2 - 2) : (half_cycle / 4); clk_cal->scl_high = half_cycle - clk_cal->scl_wait_high; clk_cal->sda_hold = half_cycle / 4; clk_cal->sda_sample = half_cycle / 2; @@ -305,8 +304,7 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e __attribute__((always_inline)) static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause) { - switch (hw->sr.stretch_cause) - { + switch (hw->sr.stretch_cause) { case 0: *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH; break; @@ -594,7 +592,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h __attribute__((always_inline)) static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { - for (int i = 0; i< len; i++) { + for (int i = 0; i < len; i++) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo_data, data, ptr[i]); } } @@ -611,7 +609,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_ __attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { - for(int i = 0; i < len; i++) { + for (int i = 0; i < len; i++) { ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo_data, data); } } @@ -623,14 +621,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs to be writen - * - * @return None. */ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr; for (int i = 0; i < len; i++) { - fifo_addr[i + ram_offset] = ptr[i]; + hw->txfifo_mem[i + ram_offset] = ptr[i]; } } @@ -641,15 +636,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs read - * - * @return None */ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr; - for (int i = 0; i < len; i++) { - ptr[i] = fifo_addr[i + ram_offset]; + ptr[i] = hw->rxfifo_mem[i + ram_offset]; } } @@ -700,8 +691,6 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf) *filter_conf = hw->filter_cfg.scl_thres; } - - /** * @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM * @@ -920,7 +909,7 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even *event = I2C_INTR_EVENT_ARBIT_LOST; } else if (int_sts.nack) { *event = I2C_INTR_EVENT_NACK; - } else if (int_sts.time_out||int_sts.scl_st_to||int_sts.scl_main_st_to) { + } else if (int_sts.time_out || int_sts.scl_st_to || int_sts.scl_main_st_to) { *event = I2C_INTR_EVENT_TOUT; } else if (int_sts.end_detect) { *event = I2C_INTR_EVENT_END_DET; @@ -1057,7 +1046,6 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); } - /** * @brief Configure I2C SCL timing * diff --git a/components/hal/esp32c6/include/hal/i2c_ll.h b/components/hal/esp32c6/include/hal/i2c_ll.h index 80e7738b69..b6dadfa477 100644 --- a/components/hal/esp32c6/include/hal/i2c_ll.h +++ b/components/hal/esp32c6/include/hal/i2c_ll.h @@ -310,8 +310,7 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e __attribute__((always_inline)) static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause) { - switch (hw->sr.stretch_cause) - { + switch (hw->sr.stretch_cause) { case 0: *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH; break; @@ -628,14 +627,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs to be writen - * - * @return None. */ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr; for (int i = 0; i < len; i++) { - fifo_addr[i + ram_offset] = ptr[i]; + hw->txfifo_mem[i + ram_offset] = ptr[i]; } } @@ -646,15 +642,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs read - * - * @return None */ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr; - for (int i = 0; i < len; i++) { - ptr[i] = fifo_addr[i + ram_offset]; + ptr[i] = hw->rxfifo_mem[i + ram_offset]; } } diff --git a/components/hal/esp32h2/include/hal/i2c_ll.h b/components/hal/esp32h2/include/hal/i2c_ll.h index 1ed9ecddc0..d6833dca44 100644 --- a/components/hal/esp32h2/include/hal/i2c_ll.h +++ b/components/hal/esp32h2/include/hal/i2c_ll.h @@ -89,7 +89,7 @@ typedef enum { */ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal) { - uint32_t clkm_div = source_clk / (bus_freq * 1024) +1; + uint32_t clkm_div = source_clk / (bus_freq * 1024) + 1; uint32_t sclk_freq = source_clk / clkm_div; uint32_t half_cycle = sclk_freq / bus_freq / 2; //SCL @@ -98,7 +98,7 @@ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_f // default, scl_wait_high < scl_high // Make 80KHz as a boundary here, because when working at lower frequency, too much scl_wait_high will faster the frequency // according to some hardware behaviors. - clk_cal->scl_wait_high = (bus_freq >= 80*1000) ? (half_cycle / 2 - 2) : (half_cycle / 4); + clk_cal->scl_wait_high = (bus_freq >= 80 * 1000) ? (half_cycle / 2 - 2) : (half_cycle / 4); clk_cal->scl_high = half_cycle - clk_cal->scl_wait_high; clk_cal->sda_hold = half_cycle / 4; clk_cal->sda_sample = half_cycle / 2; @@ -306,8 +306,7 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e __attribute__((always_inline)) static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause) { - switch (hw->sr.stretch_cause) - { + switch (hw->sr.stretch_cause) { case 0: *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH; break; @@ -595,7 +594,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h __attribute__((always_inline)) static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { - for (int i = 0; i< len; i++) { + for (int i = 0; i < len; i++) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]); } } @@ -612,7 +611,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_ __attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { - for(int i = 0; i < len; i++) { + for (int i = 0; i < len; i++) { ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->data, fifo_rdata); } } @@ -624,14 +623,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs to be writen - * - * @return None. */ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr; for (int i = 0; i < len; i++) { - fifo_addr[i + ram_offset] = ptr[i]; + hw->txfifo_mem[i + ram_offset] = ptr[i]; } } @@ -642,15 +638,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs read - * - * @return None */ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr; - for (int i = 0; i < len; i++) { - ptr[i] = fifo_addr[i + ram_offset]; + ptr[i] = hw->rxfifo_mem[i + ram_offset]; } } diff --git a/components/hal/esp32p4/include/hal/i2c_ll.h b/components/hal/esp32p4/include/hal/i2c_ll.h index 5888db147e..5983c5a930 100644 --- a/components/hal/esp32p4/include/hal/i2c_ll.h +++ b/components/hal/esp32p4/include/hal/i2c_ll.h @@ -94,7 +94,7 @@ typedef enum { */ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal) { - uint32_t clkm_div = source_clk / (bus_freq * 1024) +1; + uint32_t clkm_div = source_clk / (bus_freq * 1024) + 1; uint32_t sclk_freq = source_clk / clkm_div; uint32_t half_cycle = sclk_freq / bus_freq / 2; //SCL @@ -103,7 +103,7 @@ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_f // default, scl_wait_high < scl_high // Make 80KHz as a boundary here, because when working at lower frequency, too much scl_wait_high will faster the frequency // according to some hardware behaviors. - clk_cal->scl_wait_high = (bus_freq >= 80*1000) ? (half_cycle / 2 - 2) : (half_cycle / 4); + clk_cal->scl_wait_high = (bus_freq >= 80 * 1000) ? (half_cycle / 2 - 2) : (half_cycle / 4); clk_cal->scl_high = half_cycle - clk_cal->scl_wait_high; clk_cal->sda_hold = half_cycle / 4; clk_cal->sda_sample = half_cycle / 2; @@ -142,7 +142,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw) static inline void i2c_ll_master_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) { if (hw == &I2C0) { - HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl10, reg_i2c0_clk_div_num, bus_cfg->clkm_div - 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl10, reg_i2c0_clk_div_num, bus_cfg->clkm_div - 1); HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl10, reg_i2c0_clk_div_numerator, 0); HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl10, reg_i2c0_clk_div_denominator, 0); } else if (hw == &I2C1) { @@ -581,7 +581,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h __attribute__((always_inline)) static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { - for (int i = 0; i< len; i++) { + for (int i = 0; i < len; i++) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]); } } @@ -598,7 +598,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_ __attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { - for(int i = 0; i < len; i++) { + for (int i = 0; i < len; i++) { ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->data, fifo_rdata); } } @@ -610,14 +610,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs to be writen - * - * @return None. */ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr; for (int i = 0; i < len; i++) { - fifo_addr[i + ram_offset] = ptr[i]; + hw->txfifo_mem[i + ram_offset] = ptr[i]; } } @@ -628,15 +625,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs read - * - * @return None */ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr; - for (int i = 0; i < len; i++) { - ptr[i] = fifo_addr[i + ram_offset]; + ptr[i] = hw->rxfifo_mem[i + ram_offset]; } } @@ -748,9 +741,9 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c { // src_clk : (1) for RTC_CLK, (0) for XTAL if (hw == &I2C0) { - HP_SYS_CLKRST.peri_clk_ctrl10.reg_i2c0_clk_src_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1: 0; + HP_SYS_CLKRST.peri_clk_ctrl10.reg_i2c0_clk_src_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; } else if (hw == &I2C1) { - HP_SYS_CLKRST.peri_clk_ctrl10.reg_i2c1_clk_src_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1: 0; + HP_SYS_CLKRST.peri_clk_ctrl10.reg_i2c1_clk_src_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; } else if (hw == &LP_I2C) { // Do nothing return; @@ -835,7 +828,6 @@ static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev) return &dev->int_status; } - /** * @brief Enable I2C slave clock stretch. * diff --git a/components/hal/esp32s3/include/hal/i2c_ll.h b/components/hal/esp32s3/include/hal/i2c_ll.h index 374c8c6e04..b747db0009 100644 --- a/components/hal/esp32s3/include/hal/i2c_ll.h +++ b/components/hal/esp32s3/include/hal/i2c_ll.h @@ -88,7 +88,7 @@ typedef enum { */ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal) { - uint32_t clkm_div = source_clk / (bus_freq * 1024) +1; + uint32_t clkm_div = source_clk / (bus_freq * 1024) + 1; uint32_t sclk_freq = source_clk / clkm_div; uint32_t half_cycle = sclk_freq / bus_freq / 2; //SCL @@ -97,7 +97,7 @@ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_f // default, scl_wait_high < scl_high // Make 80KHz as a boundary here, because when working at lower frequency, too much scl_wait_high will faster the frequency // according to some hardware behaviors. - clk_cal->scl_wait_high = (bus_freq >= 80*1000) ? (half_cycle / 2 - 2) : (half_cycle / 4); + clk_cal->scl_wait_high = (bus_freq >= 80 * 1000) ? (half_cycle / 2 - 2) : (half_cycle / 4); clk_cal->scl_high = half_cycle - clk_cal->scl_wait_high; clk_cal->sda_hold = half_cycle / 4; clk_cal->sda_sample = half_cycle / 2; @@ -304,8 +304,7 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e __attribute__((always_inline)) static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause) { - switch (hw->sr.stretch_cause) - { + switch (hw->sr.stretch_cause) { case 0: *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH; break; @@ -593,7 +592,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h __attribute__((always_inline)) static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { - for (int i = 0; i< len; i++) { + for (int i = 0; i < len; i++) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]); } } @@ -610,7 +609,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_ __attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { - for(int i = 0; i < len; i++) { + for (int i = 0; i < len; i++) { ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->data, fifo_rdata); } } @@ -622,14 +621,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs to be writen - * - * @return None. */ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr; for (int i = 0; i < len; i++) { - fifo_addr[i + ram_offset] = ptr[i]; + hw->txfifo_mem[i + ram_offset] = ptr[i]; } } @@ -640,15 +636,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer * @param len Amount of data needs read - * - * @return None */ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len) { - uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr; - for (int i = 0; i < len; i++) { - ptr[i] = fifo_addr[i + ram_offset]; + ptr[i] = hw->rxfifo_mem[i + ram_offset]; } } diff --git a/components/soc/esp32c3/include/soc/i2c_struct.h b/components/soc/esp32c3/include/soc/i2c_struct.h index ccd5fdb5b0..1009fedd6e 100644 --- a/components/soc/esp32c3/include/soc/i2c_struct.h +++ b/components/soc/esp32c3/include/soc/i2c_struct.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_I2C_STRUCT_H_ #define _SOC_I2C_STRUCT_H_ @@ -363,39 +355,8 @@ typedef volatile struct i2c_dev_s { uint32_t reserved_f4; uint32_t date; uint32_t reserved_fc; - uint32_t txfifo_start_addr; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t rxfifo_start_addr; + uint32_t txfifo_mem[32]; + uint32_t rxfifo_mem[32]; } i2c_dev_t; extern i2c_dev_t I2C0; #ifdef __cplusplus diff --git a/components/soc/esp32c6/include/soc/i2c_struct.h b/components/soc/esp32c6/include/soc/i2c_struct.h index e6617dcf5e..dce4371af4 100644 --- a/components/soc/esp32c6/include/soc/i2c_struct.h +++ b/components/soc/esp32c6/include/soc/i2c_struct.h @@ -948,34 +948,6 @@ typedef union { } i2c_date_reg_t; -/** Group: Address register */ -/** Type of txfifo_start_addr register - * I2C TXFIFO base address register - */ -typedef union { - struct { - /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * This is the I2C txfifo first address. - */ - uint32_t txfifo_start_addr:32; - }; - uint32_t val; -} i2c_txfifo_start_addr_reg_t; - -/** Type of rxfifo_start_addr register - * I2C RXFIFO base address register - */ -typedef union { - struct { - /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * This is the I2C rxfifo first address. - */ - uint32_t rxfifo_start_addr:32; - }; - uint32_t val; -} i2c_rxfifo_start_addr_reg_t; - - typedef struct i2c_dev_t { volatile i2c_scl_low_period_reg_t scl_low_period; volatile i2c_ctr_reg_t ctr; @@ -1007,16 +979,15 @@ typedef struct i2c_dev_t { uint32_t reserved_088[28]; volatile i2c_date_reg_t date; uint32_t reserved_0fc; - volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; - uint32_t reserved_104[31]; - volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; + volatile uint32_t txfifo_mem[32]; + volatile uint32_t rxfifo_mem[32]; } i2c_dev_t; extern i2c_dev_t I2C0; extern i2c_dev_t LP_I2C; #ifndef __cplusplus -_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h2/include/soc/i2c_struct.h b/components/soc/esp32h2/include/soc/i2c_struct.h index c0d20904aa..eec5081e80 100644 --- a/components/soc/esp32h2/include/soc/i2c_struct.h +++ b/components/soc/esp32h2/include/soc/i2c_struct.h @@ -948,34 +948,6 @@ typedef union { } i2c_date_reg_t; -/** Group: Address register */ -/** Type of txfifo_start_addr register - * I2C TXFIFO base address register - */ -typedef union { - struct { - /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * This is the I2C txfifo first address. - */ - uint32_t txfifo_start_addr:32; - }; - uint32_t val; -} i2c_txfifo_start_addr_reg_t; - -/** Type of rxfifo_start_addr register - * I2C RXFIFO base address register - */ -typedef union { - struct { - /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * This is the I2C rxfifo first address. - */ - uint32_t rxfifo_start_addr:32; - }; - uint32_t val; -} i2c_rxfifo_start_addr_reg_t; - - typedef struct i2c_dev_t { volatile i2c_scl_low_period_reg_t scl_low_period; volatile i2c_ctr_reg_t ctr; @@ -1007,16 +979,15 @@ typedef struct i2c_dev_t { uint32_t reserved_088[28]; volatile i2c_date_reg_t date; uint32_t reserved_0fc; - volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; - uint32_t reserved_104[31]; - volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; + volatile uint32_t txfifo_mem[32]; + volatile uint32_t rxfifo_mem[32]; } i2c_dev_t; extern i2c_dev_t I2C0; extern i2c_dev_t I2C1; #ifndef __cplusplus -_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/i2c_struct.h b/components/soc/esp32p4/include/soc/i2c_struct.h index 876eba6a70..747686285a 100644 --- a/components/soc/esp32p4/include/soc/i2c_struct.h +++ b/components/soc/esp32p4/include/soc/i2c_struct.h @@ -1047,34 +1047,6 @@ typedef union { } i2c_date_reg_t; -/** Group: Address register */ -/** Type of txfifo_start_addr register - * I2C TXFIFO base address register - */ -typedef union { - struct { - /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * Represents the I2C txfifo first address. - */ - uint32_t txfifo_start_addr:32; - }; - uint32_t val; -} i2c_txfifo_start_addr_reg_t; - -/** Type of rxfifo_start_addr register - * I2C RXFIFO base address register - */ -typedef union { - struct { - /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * Represents the I2C rxfifo first address. - */ - uint32_t rxfifo_start_addr:32; - }; - uint32_t val; -} i2c_rxfifo_start_addr_reg_t; - - typedef struct { volatile i2c_scl_low_period_reg_t scl_low_period; volatile i2c_ctr_reg_t ctr; @@ -1106,9 +1078,8 @@ typedef struct { uint32_t reserved_088[28]; volatile i2c_date_reg_t date; uint32_t reserved_0fc; - volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; - uint32_t reserved_104[31]; - volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; + volatile uint32_t txfifo_mem[32]; + volatile uint32_t rxfifo_mem[32]; } i2c_dev_t; extern i2c_dev_t I2C0; @@ -1116,7 +1087,7 @@ extern i2c_dev_t I2C1; extern i2c_dev_t LP_I2C; #ifndef __cplusplus -_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32s3/include/soc/i2c_struct.h b/components/soc/esp32s3/include/soc/i2c_struct.h index 513f55770f..807ffa508d 100644 --- a/components/soc/esp32s3/include/soc/i2c_struct.h +++ b/components/soc/esp32s3/include/soc/i2c_struct.h @@ -941,35 +941,6 @@ typedef union { uint32_t val; } i2c_date_reg_t; - -/** Group: Address register */ -/** Type of txfifo_start_addr register - * I2C TXFIFO base address register - */ -typedef union { - struct { - /** txfifo_start_addr : RO; bitpos: [31:0]; default: 0; - * This is the I2C txfifo first address. - */ - uint32_t txfifo_start_addr:32; - }; - uint32_t val; -} i2c_txfifo_start_addr_reg_t; - -/** Type of rxfifo_start_addr register - * I2C RXFIFO base address register - */ -typedef union { - struct { - /** rxfifo_start_addr : RO; bitpos: [31:0]; default: 0; - * This is the I2C rxfifo first address. - */ - uint32_t rxfifo_start_addr:32; - }; - uint32_t val; -} i2c_rxfifo_start_addr_reg_t; - - typedef struct { volatile i2c_scl_low_period_reg_t scl_low_period; volatile i2c_ctr_reg_t ctr; @@ -1001,16 +972,15 @@ typedef struct { uint32_t reserved_088[28]; volatile i2c_date_reg_t date; uint32_t reserved_0fc; - volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; - uint32_t reserved_104[31]; - volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; + volatile uint32_t txfifo_mem[32]; + volatile uint32_t rxfifo_mem[32]; } i2c_dev_t; extern i2c_dev_t I2C0; extern i2c_dev_t I2C1; #ifndef __cplusplus -_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure"); #endif #ifdef __cplusplus diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index d50a18ca49..f7cb594c32 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -667,7 +667,6 @@ components/soc/esp32c3/include/soc/fe_reg.h components/soc/esp32c3/include/soc/gpio_reg.h components/soc/esp32c3/include/soc/gpio_struct.h components/soc/esp32c3/include/soc/i2c_reg.h -components/soc/esp32c3/include/soc/i2c_struct.h components/soc/esp32c3/include/soc/interrupt_core0_reg.h components/soc/esp32c3/include/soc/ledc_reg.h components/soc/esp32c3/include/soc/nrx_reg.h