mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
feat(efuse): Updates efuse table for esp32c61
This commit is contained in:
Konstantin Kondrashov
parent
599c14d8f0
commit
8539760e79
@ -30,7 +30,7 @@ int bootloader_clock_get_rated_freq_mhz(void)
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#elif CONFIG_IDF_TARGET_ESP32C6
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return 160;
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#elif CONFIG_IDF_TARGET_ESP32C61 //TODO: [ESP32C61] IDF-9282
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#elif CONFIG_IDF_TARGET_ESP32C61
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return 160;
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#elif CONFIG_IDF_TARGET_ESP32C5
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@ -9,7 +9,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table 604cf47a9075de209e7b488c4c6a3cd6
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// md5_digest_table 52aee23d9256003919a3d01945678355
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -35,6 +35,10 @@ static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = {
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{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD,
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};
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static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
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{EFUSE_BLK0, 2, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
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};
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static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = {
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{EFUSE_BLK0, 2, 1}, // [] wr_dis of JTAG_SEL_ENABLE,
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};
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@ -47,6 +51,14 @@ static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
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{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
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};
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static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = {
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{EFUSE_BLK0, 2, 1}, // [] wr_dis of HYS_EN_PAD,
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};
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static const esp_efuse_desc_t WR_DIS_DIS_WIFI6[] = {
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{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_WIFI6,
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};
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static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = {
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{EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL,
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};
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@ -95,6 +107,22 @@ static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = {
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{EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL,
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};
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static const esp_efuse_desc_t WR_DIS_XTS_DPA_CLK_ENABLE[] = {
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{EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_CLK_ENABLE,
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};
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static const esp_efuse_desc_t WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = {
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{EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_PSEUDO_LEVEL,
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};
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static const esp_efuse_desc_t WR_DIS_ECDSA_DISABLE_P192[] = {
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{EFUSE_BLK0, 14, 1}, // [] wr_dis of ECDSA_DISABLE_P192,
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};
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static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = {
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{EFUSE_BLK0, 14, 1}, // [] wr_dis of ECC_FORCE_CONST_TIME,
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};
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static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
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{EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN,
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};
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@ -103,10 +131,6 @@ static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
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{EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
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};
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static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
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{EFUSE_BLK0, 17, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
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};
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static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = {
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{EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW,
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};
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@ -144,7 +168,7 @@ static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = {
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};
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static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
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{EFUSE_BLK0, 19, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
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{EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
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};
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static const esp_efuse_desc_t WR_DIS_BLK1[] = {
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@ -155,12 +179,60 @@ static const esp_efuse_desc_t WR_DIS_MAC[] = {
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{EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
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};
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static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR,
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};
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static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR,
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};
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static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
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};
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static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
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};
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static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR,
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};
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static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR,
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};
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static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP,
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};
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static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR,
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};
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static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP,
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};
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static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR,
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};
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static const esp_efuse_desc_t WR_DIS_TEMP[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP,
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};
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static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION,
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};
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static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
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};
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static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK_SYS_DATA1,
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static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
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};
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static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
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@ -404,8 +476,56 @@ static const esp_efuse_desc_t MAC[] = {
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{EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address,
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};
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static const esp_efuse_desc_t BLOCK_SYS_DATA1[] = {
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{EFUSE_BLK2, 0, 256}, // [] System data part 1 (reserved),
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static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
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{EFUSE_BLK1, 64, 4}, // [] Minor chip version,
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};
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static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
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{EFUSE_BLK1, 68, 2}, // [] Major chip version,
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};
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static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
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{EFUSE_BLK1, 70, 1}, // [] Disables check of wafer version major,
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};
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static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
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{EFUSE_BLK1, 71, 1}, // [] Disables check of blk version major,
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};
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static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
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{EFUSE_BLK1, 72, 3}, // [] BLK_VERSION_MINOR of BLOCK2,
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};
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static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
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{EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2,
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};
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static const esp_efuse_desc_t FLASH_CAP[] = {
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{EFUSE_BLK1, 77, 3}, // [] Flash capacity,
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};
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static const esp_efuse_desc_t FLASH_VENDOR[] = {
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{EFUSE_BLK1, 80, 3}, // [] Flash vendor,
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};
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static const esp_efuse_desc_t PSRAM_CAP[] = {
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{EFUSE_BLK1, 83, 3}, // [] PSRAM capacity,
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};
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static const esp_efuse_desc_t PSRAM_VENDOR[] = {
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{EFUSE_BLK1, 86, 2}, // [] PSRAM vendor,
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};
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static const esp_efuse_desc_t TEMP[] = {
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{EFUSE_BLK1, 88, 2}, // [] Temperature,
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};
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static const esp_efuse_desc_t PKG_VERSION[] = {
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{EFUSE_BLK1, 90, 3}, // [] Package version,
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};
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static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
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};
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static const esp_efuse_desc_t USER_DATA[] = {
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@ -473,6 +593,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
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&WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = {
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&WR_DIS_JTAG_SEL_ENABLE[0], // [] wr_dis of JTAG_SEL_ENABLE
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NULL
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@ -488,6 +613,16 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = {
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&WR_DIS_HYS_EN_PAD[0], // [] wr_dis of HYS_EN_PAD
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WIFI6[] = {
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&WR_DIS_DIS_WIFI6[0], // [] wr_dis of DIS_WIFI6
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = {
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&WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL
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NULL
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@ -548,6 +683,26 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[] = {
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&WR_DIS_XTS_DPA_CLK_ENABLE[0], // [] wr_dis of XTS_DPA_CLK_ENABLE
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = {
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&WR_DIS_XTS_DPA_PSEUDO_LEVEL[0], // [] wr_dis of XTS_DPA_PSEUDO_LEVEL
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[] = {
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&WR_DIS_ECDSA_DISABLE_P192[0], // [] wr_dis of ECDSA_DISABLE_P192
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[] = {
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&WR_DIS_ECC_FORCE_CONST_TIME[0], // [] wr_dis of ECC_FORCE_CONST_TIME
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
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&WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN
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NULL
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@ -558,11 +713,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
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&WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = {
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&WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW
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NULL
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@ -623,13 +773,73 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = {
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&WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = {
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&WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
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&WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
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&WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = {
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&WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = {
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&WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = {
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&WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = {
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&WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = {
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&WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = {
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&WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = {
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&WR_DIS_TEMP[0], // [] wr_dis of TEMP
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = {
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&WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
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&WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[] = {
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&WR_DIS_BLOCK_SYS_DATA1[0], // [] wr_dis of BLOCK_SYS_DATA1
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
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&WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID
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NULL
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};
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@ -933,8 +1143,68 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[] = {
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&BLOCK_SYS_DATA1[0], // [] System data part 1 (reserved)
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const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
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&WAFER_VERSION_MINOR[0], // [] Minor chip version
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
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&WAFER_VERSION_MAJOR[0], // [] Major chip version
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
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&DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
|
||||
&DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
|
||||
&BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
|
||||
&BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
|
||||
&FLASH_CAP[0], // [] Flash capacity
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
|
||||
&FLASH_VENDOR[0], // [] Flash vendor
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
|
||||
&PSRAM_CAP[0], // [] PSRAM capacity
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = {
|
||||
&PSRAM_VENDOR[0], // [] PSRAM vendor
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = {
|
||||
&TEMP[0], // [] Temperature
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
|
||||
&PKG_VERSION[0], // [] Package version
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
|
||||
&OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
@ -9,16 +9,19 @@
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: beb6fa3bf4a43a464c3365fda28815f5
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: e564f8042b56a475a7714bb28ecdadfa
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
|
||||
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
|
||||
WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
|
||||
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 2, 1, [] wr_dis of HYS_EN_PAD
|
||||
WR_DIS.DIS_WIFI6, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_WIFI6
|
||||
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
|
||||
@ -31,9 +34,12 @@ WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.K
|
||||
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
|
||||
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
|
||||
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL
|
||||
WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE
|
||||
WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
|
||||
WR_DIS.ECDSA_DISABLE_P192, EFUSE_BLK0, 14, 1, [] wr_dis of ECDSA_DISABLE_P192
|
||||
WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 17, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
|
||||
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT
|
||||
@ -43,11 +49,23 @@ WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis
|
||||
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
|
||||
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
|
||||
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
|
||||
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
|
||||
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
|
||||
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
|
||||
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
|
||||
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
|
||||
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
|
||||
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
|
||||
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||
WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
|
||||
WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
|
||||
WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
|
||||
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
|
||||
WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.BLOCK_SYS_DATA1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK_SYS_DATA1
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
@ -97,7 +115,7 @@ DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 98, 1, [] Repres
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 99, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 100, 1, [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable\\
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 101, 2, [] Represents the types of UART printing
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 103, 1, [] Represents whether ROM code is forced to send a resume commmand during SPI boot
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 103, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 104, 16, [] Represents the version used by ESP-IDF anti-rollback feature
|
||||
SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 120, 1, [] Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is enable
|
||||
HYS_EN_PAD, EFUSE_BLK0, 121, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\
|
||||
@ -112,7 +130,19 @@ MAC, EFUSE_BLK1, 40, 8, [MAC_FACT
|
||||
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||
BLOCK_SYS_DATA1, EFUSE_BLK2, 0, 256, [] System data part 1 (reserved)
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 64, 4, [] Minor chip version
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 68, 2, [] Major chip version
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2
|
||||
FLASH_CAP, EFUSE_BLK1, 77, 3, [] Flash capacity
|
||||
FLASH_VENDOR, EFUSE_BLK1, 80, 3, [] Flash vendor
|
||||
PSRAM_CAP, EFUSE_BLK1, 83, 3, [] PSRAM capacity
|
||||
PSRAM_VENDOR, EFUSE_BLK1, 86, 2, [] PSRAM vendor
|
||||
TEMP, EFUSE_BLK1, 88, 2, [] Temperature
|
||||
PKG_VERSION, EFUSE_BLK1, 90, 3, [] Package version
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 604cf47a9075de209e7b488c4c6a3cd6
|
||||
// md5_digest_table 52aee23d9256003919a3d01945678355
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -22,9 +22,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WIFI6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
@ -43,9 +46,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
@ -59,8 +65,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
@ -144,7 +162,19 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
|
||||
@ -50,38 +50,38 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
|
||||
// use efuse_hal_get_major_chip_version() to get major chip version
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
|
||||
{
|
||||
return (uint32_t)0;
|
||||
return EFUSE0.rd_mac_sys2.wafer_version_major;
|
||||
}
|
||||
|
||||
// use efuse_hal_get_minor_chip_version() to get minor chip version
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
|
||||
{
|
||||
return (uint32_t)0;
|
||||
return EFUSE0.rd_mac_sys2.wafer_version_minor;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
|
||||
{
|
||||
return (uint32_t)0;
|
||||
return EFUSE0.rd_mac_sys2.disable_wafer_version_major;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
|
||||
{
|
||||
return (uint32_t)0;
|
||||
return EFUSE0.rd_mac_sys2.blk_version_major;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
|
||||
{
|
||||
return (uint32_t)0;
|
||||
return EFUSE0.rd_mac_sys2.blk_version_minor;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
|
||||
{
|
||||
return false;
|
||||
return EFUSE0.rd_mac_sys2.disable_blk_version_major;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
|
||||
{
|
||||
return (uint32_t)0;
|
||||
return EFUSE0.rd_mac_sys2.pkg_version;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk(void)
|
||||
|
||||
@ -233,14 +233,14 @@ extern "C" {
|
||||
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
|
||||
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 14
|
||||
/** EFUSE_USB_DREFH : RO; bitpos: [16:15]; default: 0;
|
||||
* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
#define EFUSE_USB_DREFH 0x00000003U
|
||||
#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
|
||||
#define EFUSE_USB_DREFH_V 0x00000003U
|
||||
#define EFUSE_USB_DREFH_S 15
|
||||
/** EFUSE_USB_DREFL : RO; bitpos: [18:17]; default: 0;
|
||||
* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
#define EFUSE_USB_DREFL 0x00000003U
|
||||
#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
|
||||
@ -441,7 +441,7 @@ extern "C" {
|
||||
#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U
|
||||
#define EFUSE_UART_PRINT_CONTROL_S 5
|
||||
/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [7]; default: 0;
|
||||
* Represents whether ROM code is forced to send a resume commmand during SPI boot.
|
||||
* Represents whether ROM code is forced to send a resume command during SPI boot.
|
||||
*/
|
||||
#define EFUSE_FORCE_SEND_RESUME (BIT(7))
|
||||
#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
|
||||
@ -557,32 +557,109 @@ extern "C" {
|
||||
#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
|
||||
#define EFUSE_MAC_1_V 0x0000FFFFU
|
||||
#define EFUSE_MAC_1_S 0
|
||||
/** EFUSE_RD_RESERVE_1_48 : RW; bitpos: [31:16]; default: 0;
|
||||
* Reserved, it was created by set_missed_fields_in_regs func
|
||||
/** EFUSE_C61_NO_EXTENTION : R; bitpos: [31:16]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define EFUSE_RD_RESERVE_1_48 0x0000FFFFU
|
||||
#define EFUSE_RD_RESERVE_1_48_M (EFUSE_RD_RESERVE_1_48_V << EFUSE_RD_RESERVE_1_48_S)
|
||||
#define EFUSE_RD_RESERVE_1_48_V 0x0000FFFFU
|
||||
#define EFUSE_RD_RESERVE_1_48_S 16
|
||||
#define EFUSE_C61_NO_EXTENTION 0x0000FFFFU
|
||||
#define EFUSE_C61_NO_EXTENTION_M (EFUSE_C61_NO_EXTENTION_V << EFUSE_C61_NO_EXTENTION_S)
|
||||
#define EFUSE_C61_NO_EXTENTION_V 0x0000FFFFU
|
||||
#define EFUSE_C61_NO_EXTENTION_S 16
|
||||
|
||||
/** EFUSE_RD_MAC_SYS2_REG register
|
||||
* Represents rd_mac_sys
|
||||
*/
|
||||
#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE0_BASE + 0x4c)
|
||||
/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0;
|
||||
* Reserved.
|
||||
/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
|
||||
* Minor chip version
|
||||
*/
|
||||
#define EFUSE_MAC_RESERVED_0 0x00003FFFU
|
||||
#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S)
|
||||
#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU
|
||||
#define EFUSE_MAC_RESERVED_0_S 0
|
||||
/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0;
|
||||
* Reserved.
|
||||
#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU
|
||||
#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
|
||||
#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU
|
||||
#define EFUSE_WAFER_VERSION_MINOR_S 0
|
||||
/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
|
||||
* Major chip version
|
||||
*/
|
||||
#define EFUSE_MAC_RESERVED_1 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S)
|
||||
#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_1_S 14
|
||||
#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_S 4
|
||||
/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
|
||||
* Disables check of wafer version major
|
||||
*/
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(6))
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 6
|
||||
/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
|
||||
* Disables check of blk version major
|
||||
*/
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7))
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7
|
||||
/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
|
||||
* BLK_VERSION_MINOR of BLOCK2
|
||||
*/
|
||||
#define EFUSE_BLK_VERSION_MINOR 0x00000007U
|
||||
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
|
||||
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
|
||||
#define EFUSE_BLK_VERSION_MINOR_S 8
|
||||
/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
|
||||
* BLK_VERSION_MAJOR of BLOCK2
|
||||
*/
|
||||
#define EFUSE_BLK_VERSION_MAJOR 0x00000003U
|
||||
#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
|
||||
#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U
|
||||
#define EFUSE_BLK_VERSION_MAJOR_S 11
|
||||
/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0;
|
||||
* Flash capacity
|
||||
*/
|
||||
#define EFUSE_FLASH_CAP 0x00000007U
|
||||
#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
|
||||
#define EFUSE_FLASH_CAP_V 0x00000007U
|
||||
#define EFUSE_FLASH_CAP_S 13
|
||||
/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0;
|
||||
* Flash vendor
|
||||
*/
|
||||
#define EFUSE_FLASH_VENDOR 0x00000007U
|
||||
#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
|
||||
#define EFUSE_FLASH_VENDOR_V 0x00000007U
|
||||
#define EFUSE_FLASH_VENDOR_S 16
|
||||
/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0;
|
||||
* PSRAM capacity
|
||||
*/
|
||||
#define EFUSE_PSRAM_CAP 0x00000007U
|
||||
#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
|
||||
#define EFUSE_PSRAM_CAP_V 0x00000007U
|
||||
#define EFUSE_PSRAM_CAP_S 19
|
||||
/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0;
|
||||
* PSRAM vendor
|
||||
*/
|
||||
#define EFUSE_PSRAM_VENDOR 0x00000003U
|
||||
#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
|
||||
#define EFUSE_PSRAM_VENDOR_V 0x00000003U
|
||||
#define EFUSE_PSRAM_VENDOR_S 22
|
||||
/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0;
|
||||
* Temperature
|
||||
*/
|
||||
#define EFUSE_TEMP 0x00000003U
|
||||
#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S)
|
||||
#define EFUSE_TEMP_V 0x00000003U
|
||||
#define EFUSE_TEMP_S 24
|
||||
/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0;
|
||||
* Package version
|
||||
*/
|
||||
#define EFUSE_PKG_VERSION 0x00000007U
|
||||
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
|
||||
#define EFUSE_PKG_VERSION_V 0x00000007U
|
||||
#define EFUSE_PKG_VERSION_S 26
|
||||
/** EFUSE_RESERVED_1_93 : R; bitpos: [31:29]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_93 0x00000007U
|
||||
#define EFUSE_RESERVED_1_93_M (EFUSE_RESERVED_1_93_V << EFUSE_RESERVED_1_93_S)
|
||||
#define EFUSE_RESERVED_1_93_V 0x00000007U
|
||||
#define EFUSE_RESERVED_1_93_S 29
|
||||
|
||||
/** EFUSE_RD_MAC_SYS3_REG register
|
||||
* Represents rd_mac_sys
|
||||
@ -631,49 +708,49 @@ extern "C" {
|
||||
* Represents rd_sys_part1_data0
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE0_BASE + 0x5c)
|
||||
/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
|
||||
#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_0_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA1_REG register
|
||||
* Represents rd_sys_part1_data1
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE0_BASE + 0x60)
|
||||
/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
|
||||
#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_1_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA2_REG register
|
||||
* Represents rd_sys_part1_data2
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE0_BASE + 0x64)
|
||||
/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
|
||||
#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_2_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA3_REG register
|
||||
* Represents rd_sys_part1_data3
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE0_BASE + 0x68)
|
||||
/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
|
||||
#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_3_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA4_REG register
|
||||
* Represents rd_sys_part1_data4
|
||||
@ -2071,7 +2148,7 @@ extern "C" {
|
||||
#define EFUSE_CLK_EN_S 16
|
||||
|
||||
/** EFUSE_CONF_REG register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
#define EFUSE_CONF_REG (DR_REG_EFUSE0_BASE + 0x1cc)
|
||||
/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
|
||||
|
||||
@ -223,11 +223,11 @@ typedef union {
|
||||
*/
|
||||
uint32_t dis_download_manual_encrypt:1;
|
||||
/** usb_drefh : RO; bitpos: [16:15]; default: 0;
|
||||
* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
uint32_t usb_drefh:2;
|
||||
/** usb_drefl : RO; bitpos: [18:17]; default: 0;
|
||||
* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
uint32_t usb_drefl:2;
|
||||
/** usb_exchg_pins : RO; bitpos: [19]; default: 0;
|
||||
@ -361,7 +361,7 @@ typedef union {
|
||||
*/
|
||||
uint32_t uart_print_control:2;
|
||||
/** force_send_resume : RO; bitpos: [7]; default: 0;
|
||||
* Represents whether ROM code is forced to send a resume commmand during SPI boot.
|
||||
* Represents whether ROM code is forced to send a resume command during SPI boot.
|
||||
*/
|
||||
uint32_t force_send_resume:1;
|
||||
/** secure_version : RO; bitpos: [23:8]; default: 0;
|
||||
@ -456,10 +456,10 @@ typedef union {
|
||||
* Represents MAC address. High 16-bit.
|
||||
*/
|
||||
uint32_t mac_1:16;
|
||||
/** rd_reserve_1_48 : RW; bitpos: [31:16]; default: 0;
|
||||
* Reserved, it was created by set_missed_fields_in_regs func
|
||||
/** c61_no_extention : R; bitpos: [31:16]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rd_reserve_1_48:16;
|
||||
uint32_t c61_no_extention:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys1_reg_t;
|
||||
@ -469,14 +469,58 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mac_reserved_0 : RO; bitpos: [13:0]; default: 0;
|
||||
* Reserved.
|
||||
/** wafer_version_minor : R; bitpos: [3:0]; default: 0;
|
||||
* Minor chip version
|
||||
*/
|
||||
uint32_t mac_reserved_0:14;
|
||||
/** mac_reserved_1 : RO; bitpos: [31:14]; default: 0;
|
||||
* Reserved.
|
||||
uint32_t wafer_version_minor:4;
|
||||
/** wafer_version_major : R; bitpos: [5:4]; default: 0;
|
||||
* Major chip version
|
||||
*/
|
||||
uint32_t mac_reserved_1:18;
|
||||
uint32_t wafer_version_major:2;
|
||||
/** disable_wafer_version_major : R; bitpos: [6]; default: 0;
|
||||
* Disables check of wafer version major
|
||||
*/
|
||||
uint32_t disable_wafer_version_major:1;
|
||||
/** disable_blk_version_major : R; bitpos: [7]; default: 0;
|
||||
* Disables check of blk version major
|
||||
*/
|
||||
uint32_t disable_blk_version_major:1;
|
||||
/** blk_version_minor : R; bitpos: [10:8]; default: 0;
|
||||
* BLK_VERSION_MINOR of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_minor:3;
|
||||
/** blk_version_major : R; bitpos: [12:11]; default: 0;
|
||||
* BLK_VERSION_MAJOR of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_major:2;
|
||||
/** flash_cap : R; bitpos: [15:13]; default: 0;
|
||||
* Flash capacity
|
||||
*/
|
||||
uint32_t flash_cap:3;
|
||||
/** flash_vendor : R; bitpos: [18:16]; default: 0;
|
||||
* Flash vendor
|
||||
*/
|
||||
uint32_t flash_vendor:3;
|
||||
/** psram_cap : R; bitpos: [21:19]; default: 0;
|
||||
* PSRAM capacity
|
||||
*/
|
||||
uint32_t psram_cap:3;
|
||||
/** psram_vendor : R; bitpos: [23:22]; default: 0;
|
||||
* PSRAM vendor
|
||||
*/
|
||||
uint32_t psram_vendor:2;
|
||||
/** temp : R; bitpos: [25:24]; default: 0;
|
||||
* Temperature
|
||||
*/
|
||||
uint32_t temp:2;
|
||||
/** pkg_version : R; bitpos: [28:26]; default: 0;
|
||||
* Package version
|
||||
*/
|
||||
uint32_t pkg_version:3;
|
||||
/** reserved_1_93 : R; bitpos: [31:29]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_93:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys2_reg_t;
|
||||
@ -531,10 +575,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_0:32;
|
||||
uint32_t optional_unique_id:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data0_reg_t;
|
||||
@ -544,10 +588,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_1:32;
|
||||
uint32_t optional_unique_id_1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data1_reg_t;
|
||||
@ -557,10 +601,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_2:32;
|
||||
uint32_t optional_unique_id_2:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data2_reg_t;
|
||||
@ -570,10 +614,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_3:32;
|
||||
uint32_t optional_unique_id_3:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data3_reg_t;
|
||||
@ -1893,7 +1937,7 @@ typedef union {
|
||||
|
||||
/** Group: EFUSE Configure Registers */
|
||||
/** Type of conf register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@ -4111,7 +4155,7 @@ typedef union {
|
||||
} efuse_apb2otp_blk10_w11_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE_APB2OTP Function Enable Singal */
|
||||
/** Group: EFUSE_APB2OTP Function Enable Signal */
|
||||
/** Type of apb2otp_en register
|
||||
* eFuse apb2otp enable configuration register.
|
||||
*/
|
||||
|
||||
@ -129,7 +129,6 @@ api-reference/system/sleep_modes.rst
|
||||
api-reference/system/mm_sync.rst
|
||||
api-reference/system/ota.rst
|
||||
api-reference/system/app_trace.rst
|
||||
api-reference/system/efuse.rst
|
||||
api-reference/system/chip_revision.rst
|
||||
api-reference/system/async_memcpy.rst
|
||||
api-reference/system/random.rst
|
||||
|
||||
Loading…
Reference in New Issue
Block a user