diff --git a/components/esp_system/port/soc/esp32c2/cache_err_int.c b/components/esp_system/port/soc/esp32c2/cache_err_int.c index 95fdff48c9..b101d81696 100644 --- a/components/esp_system/port/soc/esp32c2/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c2/cache_err_int.c @@ -12,10 +12,13 @@ */ #include "esp_rom_sys.h" #include "esp_attr.h" +#include "esp_log.h" #include "esp_intr_alloc.h" -#include "soc/extmem_reg.h" #include "soc/periph_defs.h" #include "riscv/interrupt.h" +#include "hal/cache_ll.h" + +static const char *TAG = "CACHE_ERR"; void esp_cache_err_int_init(void) { @@ -53,36 +56,17 @@ void esp_cache_err_int_init(void) esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); - /* On the hardware side, stat by clearing all the bits reponsible for - * enabling cache access error interrupts. */ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, - EXTMEM_CORE0_DBUS_WR_IC_INT_CLR | - EXTMEM_CORE0_DBUS_REJECT_INT_CLR | - EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR | - EXTMEM_CORE0_IBUS_REJECT_INT_CLR | - EXTMEM_CORE0_IBUS_WR_IC_INT_CLR | - EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR); - - /* Enable these interrupts. */ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, - EXTMEM_CORE0_DBUS_WR_IC_INT_ENA | - EXTMEM_CORE0_DBUS_REJECT_INT_ENA | - EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA | - EXTMEM_CORE0_IBUS_REJECT_INT_ENA | - EXTMEM_CORE0_IBUS_WR_IC_INT_ENA | - EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA); + ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); + /* On the hardware side, start by clearing all the bits reponsible for cache access error */ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + /* Then enable cache access error interrupts. */ + cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); /* Same goes for cache illegal error: start by clearing the bits and then * set them back. */ - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, - EXTMEM_MMU_ENTRY_FAULT_INT_CLR | - EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR | - EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR); - - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, - EXTMEM_MMU_ENTRY_FAULT_INT_ENA | - EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA | - EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA); + ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); + cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); + cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); /* Enable the interrupts for cache error. */ ESP_INTR_ENABLE(ETS_CACHEERR_INUM); diff --git a/components/esp_system/port/soc/esp32c3/cache_err_int.c b/components/esp_system/port/soc/esp32c3/cache_err_int.c index e33188068d..620af356e7 100644 --- a/components/esp_system/port/soc/esp32c3/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c3/cache_err_int.c @@ -12,10 +12,13 @@ */ #include "esp_rom_sys.h" #include "esp_attr.h" +#include "esp_log.h" #include "esp_intr_alloc.h" -#include "soc/extmem_reg.h" #include "soc/periph_defs.h" #include "riscv/interrupt.h" +#include "hal/cache_ll.h" + +static const char *TAG = "CACHE_ERR"; void esp_cache_err_int_init(void) { @@ -53,36 +56,17 @@ void esp_cache_err_int_init(void) esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); - /* On the hardware side, stat by clearing all the bits reponsible for - * enabling cache access error interrupts. */ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, - EXTMEM_CORE0_DBUS_WR_IC_INT_CLR | - EXTMEM_CORE0_DBUS_REJECT_INT_CLR | - EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR | - EXTMEM_CORE0_IBUS_REJECT_INT_CLR | - EXTMEM_CORE0_IBUS_WR_IC_INT_CLR | - EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR); - - /* Enable these interrupts. */ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, - EXTMEM_CORE0_DBUS_WR_IC_INT_ENA | - EXTMEM_CORE0_DBUS_REJECT_INT_ENA | - EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA | - EXTMEM_CORE0_IBUS_REJECT_INT_ENA | - EXTMEM_CORE0_IBUS_WR_IC_INT_ENA | - EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA); + ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); + /* On the hardware side, start by clearing all the bits reponsible for cache access error */ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + /* Then enable cache access error interrupts. */ + cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); /* Same goes for cache illegal error: start by clearing the bits and then * set them back. */ - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, - EXTMEM_MMU_ENTRY_FAULT_INT_CLR | - EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR | - EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR); - - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, - EXTMEM_MMU_ENTRY_FAULT_INT_ENA | - EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA | - EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA); + ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); + cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); + cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); /* Enable the interrupts for cache error. */ ESP_INTR_ENABLE(ETS_CACHEERR_INUM); diff --git a/components/esp_system/port/soc/esp32h2/cache_err_int.c b/components/esp_system/port/soc/esp32h2/cache_err_int.c index 9cde239fae..e145b460b3 100644 --- a/components/esp_system/port/soc/esp32h2/cache_err_int.c +++ b/components/esp_system/port/soc/esp32h2/cache_err_int.c @@ -12,10 +12,13 @@ */ #include "esp_rom_sys.h" #include "esp_attr.h" +#include "esp_log.h" #include "esp_intr_alloc.h" -#include "soc/extmem_reg.h" #include "soc/periph_defs.h" #include "riscv/interrupt.h" +#include "hal/cache_ll.h" + +static const char *TAG = "CACHE_ERR"; void esp_cache_err_int_init(void) { @@ -53,36 +56,17 @@ void esp_cache_err_int_init(void) esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); - /* On the hardware side, stat by clearing all the bits reponsible for - * enabling cache access error interrupts. */ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, - EXTMEM_CORE0_DBUS_WR_IC_INT_CLR | - EXTMEM_CORE0_DBUS_REJECT_INT_CLR | - EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR | - EXTMEM_CORE0_IBUS_REJECT_INT_CLR | - EXTMEM_CORE0_IBUS_WR_IC_INT_CLR | - EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR); - - /* Enable these interrupts. */ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, - EXTMEM_CORE0_DBUS_WR_IC_INT_ENA | - EXTMEM_CORE0_DBUS_REJECT_INT_ENA | - EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA | - EXTMEM_CORE0_IBUS_REJECT_INT_ENA | - EXTMEM_CORE0_IBUS_WR_IC_INT_ENA | - EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA); + ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); + /* On the hardware side, start by clearing all the bits reponsible for cache access error */ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + /* Then enable cache access error interrupts. */ + cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); /* Same goes for cache illegal error: start by clearing the bits and then * set them back. */ - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, - EXTMEM_MMU_ENTRY_FAULT_INT_CLR | - EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR | - EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR); - - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, - EXTMEM_MMU_ENTRY_FAULT_INT_ENA | - EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA | - EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA); + ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); + cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); + cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); /* Enable the interrupts for cache error. */ ESP_INTR_ENABLE(ETS_CACHEERR_INUM); diff --git a/components/esp_system/port/soc/esp32s3/cache_err_int.c b/components/esp_system/port/soc/esp32s3/cache_err_int.c index 0da146588b..13fcd103ba 100644 --- a/components/esp_system/port/soc/esp32s3/cache_err_int.c +++ b/components/esp_system/port/soc/esp32s3/cache_err_int.c @@ -15,14 +15,16 @@ #include #include "sdkconfig.h" #include "esp_err.h" +#include "esp_log.h" #include "esp_attr.h" #include "esp_intr_alloc.h" #include "soc/soc.h" -#include "soc/extmem_reg.h" #include "soc/periph_defs.h" #include "hal/cpu_hal.h" -#include "esp32s3/dport_access.h" #include "esp_rom_sys.h" +#include "hal/cache_ll.h" + +static const char *TAG = "CACHE_ERR"; void esp_cache_err_int_init(void) { @@ -42,58 +44,27 @@ void esp_cache_err_int_init(void) // For this reason, panic handler backtrace will not be correct if the // interrupt is connected to PRO CPU and invalid access happens on the APP CPU. - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, - EXTMEM_MMU_ENTRY_FAULT_INT_CLR | - EXTMEM_DCACHE_WRITE_FLASH_INT_CLR | - EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR | - EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR | - EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR | - EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR); - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, - EXTMEM_MMU_ENTRY_FAULT_INT_ENA | - EXTMEM_DCACHE_WRITE_FLASH_INT_ENA | - EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA | - EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA | - EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA | - EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA); + ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); + //illegal error intr doesn't depend on cache_id + cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); + cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); if (core_id == PRO_CPU_NUM) { esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); + /* On the hardware side, stat by clearing all the bits reponsible for * enabling cache access error interrupts. */ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, - EXTMEM_CORE0_DBUS_REJECT_INT_CLR | - EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR | - EXTMEM_CORE0_IBUS_REJECT_INT_CLR | - EXTMEM_CORE0_IBUS_WR_IC_INT_CLR | - EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR); - - /* Enable cache access error interrupts */ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, - EXTMEM_CORE0_DBUS_REJECT_INT_ENA | - EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA | - EXTMEM_CORE0_IBUS_REJECT_INT_ENA | - EXTMEM_CORE0_IBUS_WR_IC_INT_ENA | - EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA); + ESP_DRAM_LOGV(TAG, "core 0 access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); } else { esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); /* On the hardware side, stat by clearing all the bits reponsible for * enabling cache access error interrupts. */ - SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG, - EXTMEM_CORE1_DBUS_REJECT_INT_CLR | - EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR | - EXTMEM_CORE1_IBUS_REJECT_INT_CLR | - EXTMEM_CORE1_IBUS_WR_IC_INT_CLR | - EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR); - - /* Enable cache access error interrupts */ - SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG, - EXTMEM_CORE1_DBUS_REJECT_INT_ENA | - EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA | - EXTMEM_CORE1_IBUS_REJECT_INT_ENA | - EXTMEM_CORE1_IBUS_WR_IC_INT_ENA | - EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA); + ESP_DRAM_LOGV(TAG, "core 1 access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); + cache_ll_l1_clear_access_error_intr(1, CACHE_LL_L1_ACCESS_EVENT_MASK); + cache_ll_l1_enable_access_error_intr(1, CACHE_LL_L1_ACCESS_EVENT_MASK); } ESP_INTR_ENABLE(ETS_CACHEERR_INUM); @@ -101,23 +72,11 @@ void esp_cache_err_int_init(void) int IRAM_ATTR esp_cache_err_get_cpuid(void) { - const uint32_t pro_mask = EXTMEM_CORE0_DBUS_REJECT_ST | - EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST | - EXTMEM_CORE0_IBUS_REJECT_ST | - EXTMEM_CORE0_IBUS_WR_ICACHE_ST | - EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST; - - if (GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, pro_mask)) { + if (cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK)) { return PRO_CPU_NUM; } - const uint32_t app_mask = EXTMEM_CORE1_DBUS_REJECT_ST | - EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST | - EXTMEM_CORE1_IBUS_REJECT_ST | - EXTMEM_CORE1_IBUS_WR_ICACHE_ST | - EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST; - - if (GET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ST_REG, app_mask)) { + if (cache_ll_l1_get_access_error_intr_status(1, CACHE_LL_L1_ACCESS_EVENT_MASK)) { return APP_CPU_NUM; } diff --git a/components/hal/esp32c2/include/hal/cache_ll.h b/components/hal/esp32c2/include/hal/cache_ll.h index 531f81edf9..ff4631fddf 100644 --- a/components/hal/esp32c2/include/hal/cache_ll.h +++ b/components/hal/esp32c2/include/hal/cache_ll.h @@ -18,9 +18,21 @@ extern "C" { #endif -#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 -#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 +#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 +#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 +#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0) + +#define CACHE_LL_L1_ILG_EVENT_MASK (0x23) +#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5) +#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1) +#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0) /** * @brief Get the buses of a particular cache that are mapped to a virtual address range @@ -98,6 +110,79 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); } +/*------------------------------------------------------------------------------ + * Interrupt + *----------------------------------------------------------------------------*/ +/** + * @brief Enable Cache access error interrupt + * + * @param cache_id Cache ID, not used on C2. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C2. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C2. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); +} + +/** + * @brief Enable Cache illegal error interrupt + * + * @param cache_id Cache ID, not used on C2. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache illegal error interrupt status + * + * @param cache_id Cache ID, not used on C2. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache illegal error interrupt status + * + * @param cache_id Cache ID, not used on C2. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/cache_ll.h b/components/hal/esp32c3/include/hal/cache_ll.h index aa5d1bfc72..659b689fcf 100644 --- a/components/hal/esp32c3/include/hal/cache_ll.h +++ b/components/hal/esp32c3/include/hal/cache_ll.h @@ -18,8 +18,21 @@ extern "C" { #endif -#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 -#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 +#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 +#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 + +#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0) + +#define CACHE_LL_L1_ILG_EVENT_MASK (0x23) +#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5) +#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1) +#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0) /** @@ -98,6 +111,79 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); } +/*------------------------------------------------------------------------------ + * Interrupt + *----------------------------------------------------------------------------*/ +/** + * @brief Enable Cache access error interrupt + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); +} + +/** + * @brief Enable Cache illegal error interrupt + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache illegal error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache illegal error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/cache_ll.h b/components/hal/esp32h2/include/hal/cache_ll.h index 91317392c5..1a7b353ef9 100644 --- a/components/hal/esp32h2/include/hal/cache_ll.h +++ b/components/hal/esp32h2/include/hal/cache_ll.h @@ -18,9 +18,21 @@ extern "C" { #endif -#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 -#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 +#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 +#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 +#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0) + +#define CACHE_LL_L1_ILG_EVENT_MASK (0x23) +#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5) +#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1) +#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0) /** * @brief Get the buses of a particular cache that are mapped to a virtual address range @@ -98,6 +110,80 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); } + +/*------------------------------------------------------------------------------ + * Interrupt + *----------------------------------------------------------------------------*/ +/** + * @brief Enable Cache access error interrupt + * + * @param cache_id Cache ID, not used on H2. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache access error interrupt status + * + * @param cache_id Cache ID, not used on H2. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache access error interrupt status + * + * @param cache_id Cache ID, not used on H2. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); +} + +/** + * @brief Enable Cache illegal error interrupt + * + * @param cache_id Cache ID, not used on H2. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache illegal error interrupt status + * + * @param cache_id Cache ID, not used on H2. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache illegal error interrupt status + * + * @param cache_id Cache ID, not used on H2. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/cache_ll.h b/components/hal/esp32s3/include/hal/cache_ll.h index 6831b872b9..89638e1ed0 100644 --- a/components/hal/esp32s3/include/hal/cache_ll.h +++ b/components/hal/esp32s3/include/hal/cache_ll.h @@ -19,8 +19,23 @@ extern "C" { #endif -#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 -#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 +#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 +#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 + +#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x1f) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_DC_INT (1<<3) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0) + +#define CACHE_LL_L1_ILG_EVENT_MASK (0x3f) +#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5) +#define CACHE_LL_L1_ILG_EVENT_DCACHE_WRITE_FLASH (1<<4) +#define CACHE_LL_L1_ILG_EVENT_DCACHE_PRELOAD_OP_FAULT (1<<3) +#define CACHE_LL_L1_ILG_EVENT_DCACHE_SYNC_OP_FAULT (1<<2) +#define CACHE_LL_L1_ILG_EVENT_ICACHE_PRELOAD_OP_FAULT (1<<1) +#define CACHE_LL_L1_ILG_EVENT_ICACHE_SYNC_OP_FAULT (1<<0) /** @@ -115,6 +130,91 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m REG_SET_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask); } +/*------------------------------------------------------------------------------ + * Interrupt + *----------------------------------------------------------------------------*/ +/** + * @brief Enable Cache access error interrupt + * + * @param cache_id Cache ID + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + if (cache_id == 0) { + SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask); + } else { + SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG, mask); + } +} + +/** + * @brief Clear Cache access error interrupt status + * + * @param cache_id Cache ID + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + if (cache_id == 0) { + SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask); + } else { + SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG, mask); + } +} + +/** + * @brief Get Cache access error interrupt status + * + * @param cache_id Cache ID + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + if (cache_id == 0) { + return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); + } else { + return GET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ST_REG, mask); + } +} + +/** + * @brief Enable Cache illegal error interrupt + * + * @param cache_id Cache ID + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache illegal error interrupt status + * + * @param cache_id Cache ID + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache illegal error interrupt status + * + * @param cache_id Cache ID + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); +} + #ifdef __cplusplus } #endif diff --git a/components/spi_flash/test/test_cache_disabled.c b/components/spi_flash/test/test_cache_disabled.c index 5be458b47e..c9d51c2139 100644 --- a/components/spi_flash/test/test_cache_disabled.c +++ b/components/spi_flash/test/test_cache_disabled.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -79,12 +79,12 @@ static void IRAM_ATTR cache_access_test_func(void* arg) vTaskDelete(NULL); } -#ifdef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32 +#define CACHE_ERROR_REASON "Cache disabled,SW_RESET" +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 #define CACHE_ERROR_REASON "Cache error,RTC_SW_CPU_RST" #elif CONFIG_IDF_TARGET_ESP32S3 #define CACHE_ERROR_REASON "Cache disabled,RTC_SW_CPU_RST" -#else -#define CACHE_ERROR_REASON "Cache disabled,SW_RESET" #endif // These tests works properly if they resets the chip with the