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Merge branch 'feature/update_efuse_doc' into 'master'
doc/efuse: Adds efuse doc for ESP32-C3 Closes IDF-2328 See merge request espressif/esp-idf!12365
This commit is contained in:
Angus Gratton
commit
84b33b9dba
@ -18,17 +18,28 @@ For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Co
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.. only:: esp32
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ESP32 has 4 eFuse blocks each of the size of 256 bits (not all bits are available):
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{IDF_TARGET_NAME} has 4 eFuse blocks each of the size of 256 bits (not all bits are available):
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* EFUSE_BLK0 is used entirely for system purposes;
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* EFUSE_BLK1 is used for flash encrypt key. If not using that Flash Encryption feature, they can be used for another purpose;
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* EFUSE_BLK2 is used for security boot key. If not using that Secure Boot feature, they can be used for another purpose;
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* EFUSE_BLK3 can be partially reserved for the custom MAC address, or used entirely for user application. Note that some bits are already used in IDF.
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* EFUSE_BLK0 is used entirely for system purposes;
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* EFUSE_BLK1 is used for flash encrypt key. If not using that Flash Encryption feature, they can be used for another purpose;
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* EFUSE_BLK2 is used for security boot key. If not using that Secure Boot feature, they can be used for another purpose;
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* EFUSE_BLK3 can be partially reserved for the custom MAC address, or used entirely for user application. Note that some bits are already used in IDF.
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.. only:: esp32s2
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.. only:: not esp32
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{IDF_TARGET_NAME} has 11 eFuse blocks each of the size of 256 bits (not all bits are available):
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{IDF_TARGET_NAME} has 11 eFuse blocks each of the size of 256 bits (not all bits are available):
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* EFUSE_BLK0 is used entirely for system purposes;
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* EFUSE_BLK1 is used entirely for system purposes;
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* EFUSE_BLK2 is used entirely for system purposes;
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* EFUSE_BLK3 or EFUSE_BLK_USER_DATA can be used for user purposes;
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* EFUSE_BLK4 or EFUSE_BLK_KEY0 can be used as key (for secure_boot or flash_encryption) or for user purposes;
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* EFUSE_BLK5 or EFUSE_BLK_KEY1 can be used as key (for secure_boot or flash_encryption) or for user purposes;
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* EFUSE_BLK6 or EFUSE_BLK_KEY2 can be used as key (for secure_boot or flash_encryption) or for user purposes;
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* EFUSE_BLK7 or EFUSE_BLK_KEY3 can be used as key (for secure_boot or flash_encryption) or for user purposes;
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* EFUSE_BLK8 or EFUSE_BLK_KEY4 can be used as key (for secure_boot or flash_encryption) or for user purposes;
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* EFUSE_BLK9 or EFUSE_BLK_KEY5 can be used as key (for secure_boot or flash_encryption) or for user purposes;
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* EFUSE_BLK10 or EFUSE_BLK_SYS_DATA_PART2 is reseved for system purposes.
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Each block is divided into 8 32-bits registers.
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@ -42,7 +53,7 @@ The component has API functions for reading and writing fields. Access to the fi
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CSV files:
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* common (`esp_efuse_table.csv`) - contains eFuse fields which are used inside the IDF. C-source generation should be done manually when changing this file (run command ``idf.py efuse_common_table``). Note that changes in this file can lead to incorrect operation.
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* custom - (optional and can be enabled by :envvar:`CONFIG_EFUSE_CUSTOM_TABLE`) contains eFuse fields that are used by the user in their application. C-source generation should be done manually when changing this file and running ``idf.py efuse_custom_table``.
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* custom - (optional and can be enabled by :ref:`CONFIG_EFUSE_CUSTOM_TABLE`) contains eFuse fields that are used by the user in their application. C-source generation should be done manually when changing this file and running ``idf.py efuse_custom_table``.
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Description CSV file
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@ -51,10 +62,11 @@ Description CSV file
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The CSV file contains a description of the eFuse fields. In the simple case, one field has one line of description.
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Table header:
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::
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{IDF_TARGET_MAX_EFUSE_BLK:default = "EFUSE_BLK10", esp32 = "EFUSE_BLK3"}
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# field_name, efuse_block(EFUSE_BLK0..EFUSE_BLK3), bit_start(0..255), bit_count(1..256), comment
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.. code-block:: none
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# field_name, efuse_block(EFUSE_BLK0..{IDF_TARGET_MAX_EFUSE_BLK}), bit_start(0..255), bit_count(1..256), comment
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Individual params in CSV file the following meanings:
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@ -62,30 +74,37 @@ field_name
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Name of field. The prefix `ESP_EFUSE_` will be added to the name, and this field name will be available in the code. This name will be used to access the fields. The name must be unique for all fields. If the line has an empty name, then this line is combined with the previous field. This allows you to set an arbitrary order of bits in the field, and expand the field as well (see ``MAC_FACTORY`` field in the common table).
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efuse_block
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Block number. It determines where the eFuse bits will be placed for this field. Available EFUSE_BLK0..EFUSE_BLK3.
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Block number. It determines where the eFuse bits will be placed for this field. Available EFUSE_BLK0..{IDF_TARGET_MAX_EFUSE_BLK}.
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bit_start
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Start bit number (0..255). The bit_start field can be omitted. In this case, it will be set to bit_start + bit_count from the previous record, if it has the same efuse_block. Otherwise (if efuse_block is different, or this is the first entry), an error will be generated.
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bit_count
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The number of bits to use in this field (1..-). This parameter can not be omitted. This field also may be ``MAX_BLK_LEN`` in this case, the field length will have the maximum block length, taking into account the coding scheme (applicable for ``ESP_EFUSE_SECURE_BOOT_KEY`` and ``ESP_EFUSE_ENCRYPT_FLASH_KEY`` fields). The value ``MAX_BLK_LEN`` depends on :envvar:`CONFIG_EFUSE_MAX_BLK_LEN`, will be replaced with "None" - 256, "3/4" - 192, "REPEAT" - 128.
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.. only:: esp32
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bit_count
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The number of bits to use in this field (1..-). This parameter can not be omitted. This field also may be ``MAX_BLK_LEN`` in this case, the field length will have the maximum block length, taking into account the coding scheme (applicable for ``ESP_EFUSE_SECURE_BOOT_KEY`` and ``ESP_EFUSE_ENCRYPT_FLASH_KEY`` fields). The value ``MAX_BLK_LEN`` depends on :ref:`CONFIG_EFUSE_CODE_SCHEME_SELECTOR`, will be replaced with "None" - 256, "3/4" - 192, "REPEAT" - 128.
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.. only:: not esp32
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bit_count
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The number of bits to use in this field (1..-). This parameter can not be omitted. This field also may be ``MAX_BLK_LEN`` in this case, the field length will have the maximum block length.
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comment
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This param is using for comment field, it also move to C-header file. The comment field can be omitted.
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If a non-sequential bit order is required to describe a field, then the field description in the following lines should be continued without specifying a name, this will indicate that it belongs to one field. For example two fields MAC_FACTORY and MAC_FACTORY_CRC:
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::
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.. code-block:: none
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# Factory MAC address #
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#######################
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MAC_FACTORY, EFUSE_BLK0, 72, 8, Factory MAC addr [0]
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, EFUSE_BLK0, 64, 8, Factory MAC addr [1]
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, EFUSE_BLK0, 56, 8, Factory MAC addr [2]
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, EFUSE_BLK0, 48, 8, Factory MAC addr [3]
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, EFUSE_BLK0, 40, 8, Factory MAC addr [4]
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, EFUSE_BLK0, 32, 8, Factory MAC addr [5]
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MAC_FACTORY_CRC, EFUSE_BLK0, 80, 8, CRC8 for factory MAC address
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# Factory MAC address #
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#######################
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MAC_FACTORY, EFUSE_BLK0, 72, 8, Factory MAC addr [0]
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, EFUSE_BLK0, 64, 8, Factory MAC addr [1]
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, EFUSE_BLK0, 56, 8, Factory MAC addr [2]
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, EFUSE_BLK0, 48, 8, Factory MAC addr [3]
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, EFUSE_BLK0, 40, 8, Factory MAC addr [4]
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, EFUSE_BLK0, 32, 8, Factory MAC addr [5]
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MAC_FACTORY_CRC, EFUSE_BLK0, 80, 8, CRC8 for factory MAC address
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This field will available in code as ESP_EFUSE_MAC_FACTORY and ESP_EFUSE_MAC_FACTORY_CRC.
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@ -96,22 +115,22 @@ The tool is designed to generate C-source files from CSV file and validate field
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To generate a `common` files, use the following command ``idf.py efuse_common_table`` or:
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::
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.. code-block:: bash
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cd $IDF_PATH/components/efuse/
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./efuse_table_gen.py {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv
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cd $IDF_PATH/components/efuse/
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./efuse_table_gen.py {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv
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After generation in the folder `{IDF_TARGET_PATH_NAME}` create:
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After generation in the folder $IDF_PATH/components/efuse/`{IDF_TARGET_PATH_NAME}` create:
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* `esp_efuse_table.c` file.
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* In `include` folder `esp_efuse_table.c` file.
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To generate a `custom` files, use the following command ``idf.py efuse_custom_table`` or:
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::
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.. code-block:: bash
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cd $IDF_PATH/components/efuse/
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./efuse_table_gen.py {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv PROJECT_PATH/main/esp_efuse_custom_table.csv
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cd $IDF_PATH/components/efuse/
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./efuse_table_gen.py {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv PROJECT_PATH/main/esp_efuse_custom_table.csv
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After generation in the folder PROJECT_PATH/main create:
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@ -120,47 +139,58 @@ After generation in the folder PROJECT_PATH/main create:
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To use the generated fields, you need to include two files:
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::
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.. code-block:: c
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#include "esp_efuse.h"
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#include "esp_efuse_table.h" or "esp_efuse_custom_table.h"
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#include "esp_efuse.h"
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#include "esp_efuse_table.h" or "esp_efuse_custom_table.h"
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Support coding scheme
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---------------------
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eFuse have three coding schemes:
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Supported coding scheme
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-----------------------
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* ``None`` (value 0).
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* ``3/4`` (value 1).
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* ``Repeat`` (value 2).
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.. only:: esp32
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The coding scheme affects only EFUSE_BLK1, EFUSE_BLK2 and EFUSE_BLK3 blocks. EUSE_BLK0 block always has a coding scheme ``None``.
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Coding changes the number of bits that can be written into a block, the block length is constant 256, some of these bits are used for encoding and are not used.
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eFuse have three coding schemes:
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When using a coding scheme, the length of the payload that can be written is limited (for more details ``20.3.1.3 System Parameter coding_scheme``):
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* ``None`` (value 0).
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* ``3/4`` (value 1).
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* ``Repeat`` (value 2).
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* None 256 bits.
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* 3/4 192 bits.
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* Repeat 128 bits.
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The coding scheme affects only EFUSE_BLK1, EFUSE_BLK2 and EFUSE_BLK3 blocks. EUSE_BLK0 block always has a coding scheme ``None``.
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Coding changes the number of bits that can be written into a block, the block length is constant 256, some of these bits are used for encoding and not avaliable for the user.
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You can find out the coding scheme of your chip:
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When using a coding scheme, the length of the payload that can be written is limited (for more details ``20.3.1.3 System Parameter coding_scheme``):
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* run a ``espefuse.py -p COM4 summary`` command.
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* from ``esptool`` utility logs (during flashing).
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* calling the function in the code :cpp:func:`esp_efuse_get_coding_scheme` for the EFUSE_BLK3 block.
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* None 256 bits.
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* 3/4 192 bits.
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* Repeat 128 bits.
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eFuse tables must always comply with the coding scheme in the chip. There is an :envvar:`EFUSE_CODE_SCHEME_SELECTOR` option to select the coding type for tables in a Kconfig. When generating source files, if your tables do not follow the coding scheme, an error message will be displayed. Adjust the length or offset fields.
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If your program was compiled with ``None`` encoding and ``3/4`` is used in the chip, then the ``ESP_ERR_CODING`` error may occur when calling the eFuse API (the field is outside the block boundaries). If the field matches the new block boundaries, then the API will work without errors.
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You can find out the coding scheme of your chip:
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Also, 3/4 coding scheme imposes restrictions on writing bits belonging to one coding unit. The whole block with a length of 256 bits is divided into 4 coding units, and in each coding unit there are 6 bytes of useful data and 2 service bytes. These 2 service bytes contain the checksum of the previous 6 data bytes.
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* run a ``espefuse.py -p PORT summary`` command.
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* from ``esptool`` utility logs (during flashing).
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* calling the function in the code :cpp:func:`esp_efuse_get_coding_scheme` for the EFUSE_BLK3 block.
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It turns out that only one field can be written into one coding unit. Repeated rewriting in one coding unit is prohibited. But if the record was made in advance or through a :cpp:func:`esp_efuse_write_block` function, then reading the fields belonging to one coding unit is possible.
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eFuse tables must always comply with the coding scheme in the chip. There is an :ref:`CONFIG_EFUSE_CODE_SCHEME_SELECTOR` option to select the coding type for tables in a Kconfig. When generating source files, if your tables do not follow the coding scheme, an error message will be displayed. Adjust the length or offset fields.
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If your program was compiled with ``None`` encoding and ``3/4`` is used in the chip, then the ``ESP_ERR_CODING`` error may occur when calling the eFuse API (the field is outside the block boundaries). If the field matches the new block boundaries, then the API will work without errors.
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In case ``3/4`` coding scheme, the writing process is divided into the coding units and we can not use the usual mode of writing some fields. We can prepare all the data for writing and burn it in one time. You can also use this mode for ``None`` coding scheme but it is not necessary. It is important for ``3/4`` coding scheme.
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To write some fields in one time need to use ``the batch writing mode``. Firstly set this mode through :cpp:func:`esp_efuse_batch_write_begin` function then write some fields as usual use the ``esp_efuse_write_...`` functions. At the end to burn they, need to call the :cpp:func:`esp_efuse_batch_write_commit` function. It burns prepared data to the efuse blocks and disable the ``batch recording mode``.
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``The batch writing mode`` blocks ``esp_efuse_read_...`` operations.
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Also, 3/4 coding scheme imposes restrictions on writing bits belonging to one coding unit. The whole block with a length of 256 bits is divided into 4 coding units, and in each coding unit there are 6 bytes of useful data and 2 service bytes. These 2 service bytes contain the checksum of the previous 6 data bytes.
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After changing the coding scheme, run ``efuse_common_table`` and ``efuse_custom_table`` commands to check the tables of the new coding scheme.
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It turns out that only one field can be written into one coding unit. Repeated rewriting in one coding unit is prohibited. But if the record was made in advance or through a :cpp:func:`esp_efuse_write_block` function, then reading the fields belonging to one coding unit is possible.
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In case ``3/4`` coding scheme, the writing process is divided into the coding units and we can not use the usual mode of writing some fields. We can prepare all the data for writing and burn it in one time. You can also use this mode for ``None`` coding scheme but it is not necessary. It is important for ``3/4`` coding scheme.
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``The batch writing mode`` blocks ``esp_efuse_read_...`` operations.
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After changing the coding scheme, run ``efuse_common_table`` and ``efuse_custom_table`` commands to check the tables of the new coding scheme.
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.. only:: not esp32
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Coding schemes are used to protect against data corruption. {IDF_TARGET_NAME} supports two coding schemes:
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* ``None``. EFUSE_BLK0 is stored with four backups, meaning each bit is stored four times. This backup scheme is automatically applied by the hardware and is not visible to software. EFUSE_BLK0 can be written many times.
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* ``RS``. EFUSE_BLK1 - EFUSE_BLK10 use Reed-Solomon coding scheme that supports up to 5 bytes of automatic error correction. Software will encode the 32-byte EFUSE_BLKx using RS (44, 32) to generate a 12-byte check code, and then burn the EFUSE_BLKx and the check code into eFuse at the same time. The eFuse Controller automatically decodes the RS encoding and applies error correction when reading back the eFuse block. Because the RS check codes are generated across the entire 256-bit eFuse block, each block can only be written to one time.
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To write some fields into one block, or different blocks in one time, you need to use ``the batch writing mode``. Firstly set this mode through :cpp:func:`esp_efuse_batch_write_begin` function then write some fields as usual using the ``esp_efuse_write_...`` functions. At the end to burn them, call the :cpp:func:`esp_efuse_batch_write_commit` function. It burns prepared data to the eFuse blocks and disables the ``batch recording mode``.
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eFuse API
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---------
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@ -183,77 +213,111 @@ Access to the fields is via a pointer to the description structure. API function
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For frequently used fields, special functions are made, like this :cpp:func:`esp_efuse_get_chip_ver`, :cpp:func:`esp_efuse_get_pkg_ver`.
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.. only:: not esp32
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How add a new field
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-------------------
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eFuse API for keys
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------------------
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EFUSE_BLK_KEY0 - EFUSE_BLK_KEY5 are intended to keep up to 6 keys with a length of 256-bits. Each key has an ``ESP_EFUSE_KEY_PURPOSE_x`` field which defines the purpose of these keys. The purpose field is described in :cpp:type:`esp_efuse_purpose_t`.
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The purposes like ``ESP_EFUSE_KEY_PURPOSE_XTS_AES_...`` are used for flash encryption.
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The purposes like ``ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST...`` are used for secure boot.
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There are some eFuse APIs useful to work with states of keys.
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* :cpp:func:`esp_efuse_get_purpose_field` - Returns a pointer to a key purpose for an eFuse key block.
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* :cpp:func:`esp_efuse_get_key` - Returns a pointer to a key block.
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* :cpp:func:`esp_efuse_get_key_dis_read` - Returns a read protection for the key block.
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* :cpp:func:`esp_efuse_set_key_dis_read` - Sets a read protection for the key block.
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* :cpp:func:`esp_efuse_get_key_dis_write` - Returns a write protection for the key block.
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* :cpp:func:`esp_efuse_set_key_dis_write` - Sets a write protection for the key block.
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* :cpp:func:`esp_efuse_get_key_purpose` - Returns the current purpose set for an eFuse key block.
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* :cpp:func:`esp_efuse_set_key_purpose` - Sets a key purpose for an eFuse key block.
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* :cpp:func:`esp_efuse_get_keypurpose_dis_write` - Returns a write protection of the key purpose field for an eFuse key block.
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* :cpp:func:`esp_efuse_set_keypurpose_dis_write` - Sets a write protection of the key purpose field for an eFuse key block.
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* :cpp:func:`esp_efuse_find_purpose` - Finds a key block with the particular purpose set.
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* :cpp:func:`esp_efuse_find_unused_key_block` - Search for an unused key block and return the first one found.
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* :cpp:func:`esp_efuse_count_unused_key_blocks` - Returns the number of unused eFuse key blocks in the range EFUSE_BLK_KEY0..EFUSE_BLK_KEY_MAX
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* :cpp:func:`esp_efuse_key_block_unused` - Returns true if the key block is unused, false otherwise.
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* :cpp:func:`esp_efuse_get_digest_revoke` - Returns the status of the Secure Boot public key digest revocation bit.
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* :cpp:func:`esp_efuse_set_digest_revoke` - Sets the Secure Boot public key digest revocation bit.
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* :cpp:func:`esp_efuse_get_write_protect_of_digest_revoke` - Returns a write protection of the Secure Boot public key digest revocation bit.
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* :cpp:func:`esp_efuse_set_write_protect_of_digest_revoke` - Sets a write protection of the Secure Boot public key digest revocation bit.
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* :cpp:func:`esp_efuse_write_key` - Programs a block of key data to an eFuse block
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* :cpp:func:`esp_efuse_write_keys` - Programs keys to unused eFuse blocks
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How to add a new field
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----------------------
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1. Find a free bits for field. Show `esp_efuse_table.csv` file or run ``idf.py show_efuse_table`` or the next command:
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::
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.. code-block:: none
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$ ./efuse_table_gen.py {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv --info
|
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eFuse coding scheme: NONE
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# field_name efuse_block bit_start bit_count
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1 WR_DIS_FLASH_CRYPT_CNT EFUSE_BLK0 2 1
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2 WR_DIS_BLK1 EFUSE_BLK0 7 1
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3 WR_DIS_BLK2 EFUSE_BLK0 8 1
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4 WR_DIS_BLK3 EFUSE_BLK0 9 1
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5 RD_DIS_BLK1 EFUSE_BLK0 16 1
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6 RD_DIS_BLK2 EFUSE_BLK0 17 1
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7 RD_DIS_BLK3 EFUSE_BLK0 18 1
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8 FLASH_CRYPT_CNT EFUSE_BLK0 20 7
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9 MAC_FACTORY EFUSE_BLK0 32 8
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10 MAC_FACTORY EFUSE_BLK0 40 8
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11 MAC_FACTORY EFUSE_BLK0 48 8
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12 MAC_FACTORY EFUSE_BLK0 56 8
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13 MAC_FACTORY EFUSE_BLK0 64 8
|
||||
14 MAC_FACTORY EFUSE_BLK0 72 8
|
||||
15 MAC_FACTORY_CRC EFUSE_BLK0 80 8
|
||||
16 CHIP_VER_DIS_APP_CPU EFUSE_BLK0 96 1
|
||||
17 CHIP_VER_DIS_BT EFUSE_BLK0 97 1
|
||||
18 CHIP_VER_PKG EFUSE_BLK0 105 3
|
||||
19 CHIP_CPU_FREQ_LOW EFUSE_BLK0 108 1
|
||||
20 CHIP_CPU_FREQ_RATED EFUSE_BLK0 109 1
|
||||
21 CHIP_VER_REV1 EFUSE_BLK0 111 1
|
||||
22 ADC_VREF_AND_SDIO_DREF EFUSE_BLK0 136 6
|
||||
23 XPD_SDIO_REG EFUSE_BLK0 142 1
|
||||
24 SDIO_TIEH EFUSE_BLK0 143 1
|
||||
25 SDIO_FORCE EFUSE_BLK0 144 1
|
||||
26 ENCRYPT_CONFIG EFUSE_BLK0 188 4
|
||||
27 CONSOLE_DEBUG_DISABLE EFUSE_BLK0 194 1
|
||||
28 ABS_DONE_0 EFUSE_BLK0 196 1
|
||||
29 DISABLE_JTAG EFUSE_BLK0 198 1
|
||||
30 DISABLE_DL_ENCRYPT EFUSE_BLK0 199 1
|
||||
31 DISABLE_DL_DECRYPT EFUSE_BLK0 200 1
|
||||
32 DISABLE_DL_CACHE EFUSE_BLK0 201 1
|
||||
33 ENCRYPT_FLASH_KEY EFUSE_BLK1 0 256
|
||||
34 SECURE_BOOT_KEY EFUSE_BLK2 0 256
|
||||
35 MAC_CUSTOM_CRC EFUSE_BLK3 0 8
|
||||
36 MAC_CUSTOM EFUSE_BLK3 8 48
|
||||
37 ADC1_TP_LOW EFUSE_BLK3 96 7
|
||||
38 ADC1_TP_HIGH EFUSE_BLK3 103 9
|
||||
39 ADC2_TP_LOW EFUSE_BLK3 112 7
|
||||
40 ADC2_TP_HIGH EFUSE_BLK3 119 9
|
||||
41 SECURE_VERSION EFUSE_BLK3 128 32
|
||||
42 MAC_CUSTOM_VER EFUSE_BLK3 184 8
|
||||
$ ./efuse_table_gen.py {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv --info
|
||||
eFuse coding scheme: NONE
|
||||
# field_name efuse_block bit_start bit_count
|
||||
1 WR_DIS_FLASH_CRYPT_CNT EFUSE_BLK0 2 1
|
||||
2 WR_DIS_BLK1 EFUSE_BLK0 7 1
|
||||
3 WR_DIS_BLK2 EFUSE_BLK0 8 1
|
||||
4 WR_DIS_BLK3 EFUSE_BLK0 9 1
|
||||
5 RD_DIS_BLK1 EFUSE_BLK0 16 1
|
||||
6 RD_DIS_BLK2 EFUSE_BLK0 17 1
|
||||
7 RD_DIS_BLK3 EFUSE_BLK0 18 1
|
||||
8 FLASH_CRYPT_CNT EFUSE_BLK0 20 7
|
||||
9 MAC_FACTORY EFUSE_BLK0 32 8
|
||||
10 MAC_FACTORY EFUSE_BLK0 40 8
|
||||
11 MAC_FACTORY EFUSE_BLK0 48 8
|
||||
12 MAC_FACTORY EFUSE_BLK0 56 8
|
||||
13 MAC_FACTORY EFUSE_BLK0 64 8
|
||||
14 MAC_FACTORY EFUSE_BLK0 72 8
|
||||
15 MAC_FACTORY_CRC EFUSE_BLK0 80 8
|
||||
16 CHIP_VER_DIS_APP_CPU EFUSE_BLK0 96 1
|
||||
17 CHIP_VER_DIS_BT EFUSE_BLK0 97 1
|
||||
18 CHIP_VER_PKG EFUSE_BLK0 105 3
|
||||
19 CHIP_CPU_FREQ_LOW EFUSE_BLK0 108 1
|
||||
20 CHIP_CPU_FREQ_RATED EFUSE_BLK0 109 1
|
||||
21 CHIP_VER_REV1 EFUSE_BLK0 111 1
|
||||
22 ADC_VREF_AND_SDIO_DREF EFUSE_BLK0 136 6
|
||||
23 XPD_SDIO_REG EFUSE_BLK0 142 1
|
||||
24 SDIO_TIEH EFUSE_BLK0 143 1
|
||||
25 SDIO_FORCE EFUSE_BLK0 144 1
|
||||
26 ENCRYPT_CONFIG EFUSE_BLK0 188 4
|
||||
27 CONSOLE_DEBUG_DISABLE EFUSE_BLK0 194 1
|
||||
28 ABS_DONE_0 EFUSE_BLK0 196 1
|
||||
29 DISABLE_JTAG EFUSE_BLK0 198 1
|
||||
30 DISABLE_DL_ENCRYPT EFUSE_BLK0 199 1
|
||||
31 DISABLE_DL_DECRYPT EFUSE_BLK0 200 1
|
||||
32 DISABLE_DL_CACHE EFUSE_BLK0 201 1
|
||||
33 ENCRYPT_FLASH_KEY EFUSE_BLK1 0 256
|
||||
34 SECURE_BOOT_KEY EFUSE_BLK2 0 256
|
||||
35 MAC_CUSTOM_CRC EFUSE_BLK3 0 8
|
||||
36 MAC_CUSTOM EFUSE_BLK3 8 48
|
||||
37 ADC1_TP_LOW EFUSE_BLK3 96 7
|
||||
38 ADC1_TP_HIGH EFUSE_BLK3 103 9
|
||||
39 ADC2_TP_LOW EFUSE_BLK3 112 7
|
||||
40 ADC2_TP_HIGH EFUSE_BLK3 119 9
|
||||
41 SECURE_VERSION EFUSE_BLK3 128 32
|
||||
42 MAC_CUSTOM_VER EFUSE_BLK3 184 8
|
||||
|
||||
Used bits in eFuse table:
|
||||
EFUSE_BLK0
|
||||
[2 2] [7 9] [16 18] [20 27] [32 87] [96 97] [105 109] [111 111] [136 144] [188 191] [194 194] [196 196] [198 201]
|
||||
Used bits in eFuse table:
|
||||
EFUSE_BLK0
|
||||
[2 2] [7 9] [16 18] [20 27] [32 87] [96 97] [105 109] [111 111] [136 144] [188 191] [194 194] [196 196] [198 201]
|
||||
|
||||
EFUSE_BLK1
|
||||
[0 255]
|
||||
EFUSE_BLK1
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK2
|
||||
[0 255]
|
||||
EFUSE_BLK2
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK3
|
||||
[0 55] [96 159] [184 191]
|
||||
EFUSE_BLK3
|
||||
[0 55] [96 159] [184 191]
|
||||
|
||||
Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif)
|
||||
Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif)
|
||||
|
||||
Parsing eFuse CSV input file $IDF_PATH/components/efuse/{IDF_TARGET_PATH_NAME}/esp_efuse_table.csv ...
|
||||
Verifying eFuse table...
|
||||
Parsing eFuse CSV input file $IDF_PATH/components/efuse/{IDF_TARGET_PATH_NAME}/esp_efuse_table.csv ...
|
||||
Verifying eFuse table...
|
||||
|
||||
|
||||
The number of bits not included in square brackets is free (bits in EFUSE_BLK0 are reserved for Espressif). All fields are checked for overlapping.
|
||||
@ -268,87 +332,14 @@ Debug eFuse & Unit tests
|
||||
Virtual eFuses
|
||||
^^^^^^^^^^^^^^
|
||||
|
||||
The Kconfig option :envvar:`CONFIG_EFUSE_VIRTUAL` will virtualize eFuse values inside the eFuse Manager, so writes are emulated and no eFuse values are permanently changed. This can be useful for debugging app and unit tests.
|
||||
The Kconfig option :ref:`CONFIG_EFUSE_VIRTUAL` will virtualize eFuse values inside the eFuse Manager, so writes are emulated and no eFuse values are permanently changed. This can be useful for debugging app and unit tests.
|
||||
|
||||
espefuse.py
|
||||
^^^^^^^^^^^
|
||||
|
||||
esptool includes a useful tool for reading/writing {IDF_TARGET_NAME} eFuse bits - `espefuse.py <https://github.com/espressif/esptool/wiki/espefuse>`_.
|
||||
|
||||
::
|
||||
|
||||
espefuse.py -p COM4 summary
|
||||
|
||||
espefuse.py v2.3.1
|
||||
Connecting........_
|
||||
Security fuses:
|
||||
FLASH_CRYPT_CNT Flash encryption mode counter = 0 R/W (0x0)
|
||||
FLASH_CRYPT_CONFIG Flash encryption config (key tweak bits) = 0 R/W (0x0)
|
||||
CONSOLE_DEBUG_DISABLE Disable ROM BASIC interpreter fallback = 1 R/W (0x1)
|
||||
ABS_DONE_0 secure boot enabled for bootloader = 0 R/W (0x0)
|
||||
ABS_DONE_1 secure boot abstract 1 locked = 0 R/W (0x0)
|
||||
JTAG_DISABLE Disable JTAG = 0 R/W (0x0)
|
||||
DISABLE_DL_ENCRYPT Disable flash encryption in UART bootloader = 0 R/W (0x0)
|
||||
DISABLE_DL_DECRYPT Disable flash decryption in UART bootloader = 0 R/W (0x0)
|
||||
DISABLE_DL_CACHE Disable flash cache in UART bootloader = 0 R/W (0x0)
|
||||
BLK1 Flash encryption key
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLK2 Secure boot key
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLK3 Variable Block 3
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa 87 02 91 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Efuse fuses:
|
||||
WR_DIS Efuse write disable mask = 0 R/W (0x0)
|
||||
RD_DIS Efuse read disablemask = 0 R/W (0x0)
|
||||
CODING_SCHEME Efuse variable block length scheme = 1 R/W (0x1) (3/4)
|
||||
KEY_STATUS Usage of efuse block 3 (reserved) = 0 R/W (0x0)
|
||||
|
||||
Config fuses:
|
||||
XPD_SDIO_FORCE Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = 0 R/W (0x0)
|
||||
XPD_SDIO_REG If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = 0 R/W (0x0)
|
||||
XPD_SDIO_TIEH If XPD_SDIO_FORCE & XPD_SDIO_REG, 1=3.3V 0=1.8V = 0 R/W (0x0)
|
||||
SPI_PAD_CONFIG_CLK Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0x0)
|
||||
SPI_PAD_CONFIG_Q Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0x0)
|
||||
SPI_PAD_CONFIG_D Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0x0)
|
||||
SPI_PAD_CONFIG_HD Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0x0)
|
||||
SPI_PAD_CONFIG_CS0 Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0x0)
|
||||
DISABLE_SDIO_HOST Disable SDIO host = 0 R/W (0x0)
|
||||
|
||||
Identity fuses:
|
||||
MAC MAC Address
|
||||
= 84:0d:8e:18:8e:44 (CRC ad OK) R/W
|
||||
CHIP_VER_REV1 Silicon Revision 1 = 1 R/W (0x1)
|
||||
CHIP_VERSION Reserved for future chip versions = 2 R/W (0x2)
|
||||
CHIP_PACKAGE Chip package identifier = 0 R/W (0x0)
|
||||
|
||||
Calibration fuses:
|
||||
BLK3_PART_RESERVE BLOCK3 partially served for ADC calibration data = 1 R/W (0x1)
|
||||
ADC_VREF Voltage reference calibration = 1114 R/W (0x2)
|
||||
ADC1_TP_LOW ADC1 150mV reading = 346 R/W (0x11)
|
||||
ADC1_TP_HIGH ADC1 850mV reading = 3285 R/W (0x5)
|
||||
ADC2_TP_LOW ADC2 150mV reading = 449 R/W (0x7)
|
||||
ADC2_TP_HIGH ADC2 850mV reading = 3362 R/W (0x1f5)
|
||||
|
||||
Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).
|
||||
|
||||
To get a dump for all eFuse registers.
|
||||
|
||||
::
|
||||
|
||||
espefuse.py -p COM4 dump
|
||||
|
||||
$ espefuse.py -p COM4 dump
|
||||
espefuse.py v2.3.1
|
||||
Connecting........__
|
||||
EFUSE block 0:
|
||||
00000000 c403bb68 0082240a 00000000 00000035 00000000 00000000
|
||||
EFUSE block 1:
|
||||
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
EFUSE block 2:
|
||||
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
EFUSE block 3:
|
||||
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
.. include:: inc/espefuse_summary_{IDF_TARGET_NAME}.rst
|
||||
|
||||
|
||||
.. include-build-file:: inc/esp_efuse.inc
|
||||
|
||||
158
docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst
Normal file
158
docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst
Normal file
@ -0,0 +1,158 @@
|
||||
.. code-block:: none
|
||||
|
||||
espefuse.py -p PORT summary
|
||||
|
||||
Connecting....
|
||||
Detecting chip type... ESP32-C3
|
||||
espefuse.py v3.1-dev
|
||||
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
|
||||
----------------------------------------------------------------------------------------
|
||||
Config fuses:
|
||||
DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0)
|
||||
DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0)
|
||||
DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0)
|
||||
DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0)
|
||||
DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0)
|
||||
VDD_SPI_AS_GPIO (BLOCK0) Set this bit to vdd spi pin function as gpio = False R/W (0b0)
|
||||
BTLC_GPIO_ENABLE (BLOCK0) Enable btlc gpio = 0 R/W (0b00)
|
||||
POWERGLITCH_EN (BLOCK0) Set this bit to enable power glitch function = False R/W (0b0)
|
||||
POWER_GLITCH_DSENSE (BLOCK0) Sample delay configuration of power glitch = 0 R/W (0b00)
|
||||
DIS_LEGACY_SPI_BOOT (BLOCK0) Disables Legacy SPI boot mode = False R/W (0b0)
|
||||
UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0)
|
||||
UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00)
|
||||
FORCE_SEND_RESUME (BLOCK0) Force ROM code to send a resume command during SPI = False R/W (0b0)
|
||||
bootduring SPI boot
|
||||
BLOCK_USR_DATA (BLOCK3) User data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Efuse fuses:
|
||||
WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000)
|
||||
RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000)
|
||||
|
||||
Flash Config fuses:
|
||||
FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0)
|
||||
unit is (ms/2). When the value is 15, delay is 7.
|
||||
5 ms
|
||||
FLASH_ECC_MODE (BLOCK0) Set this bit to set flsah ecc mode.
|
||||
= flash ecc 16to18 byte mode R/W (0b0)
|
||||
FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0)
|
||||
FLASH_PAGE_SIZE (BLOCK0) Flash page size = 0 R/W (0b00)
|
||||
FLASH_ECC_EN (BLOCK0) Enable ECC for flash boot = False R/W (0b0)
|
||||
|
||||
Identity fuses:
|
||||
SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000)
|
||||
ure)
|
||||
MAC (BLOCK1) Factory MAC Address
|
||||
= 7c:df:a1:40:40:08: (OK) R/W
|
||||
WAFER_VERSION (BLOCK1) WAFER version = (revision 0) R/W (0b000)
|
||||
PKG_VERSION (BLOCK1) Package version = ESP32-C3 R/W (0x0)
|
||||
BLOCK1_VERSION (BLOCK1) BLOCK1 efuse version = 0 R/W (0b000)
|
||||
OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors): Optional unique 128-bit ID
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK2_VERSION (BLOCK2) Version of BLOCK2 = No calibration R/W (0b000)
|
||||
|
||||
Jtag Config fuses:
|
||||
JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0)
|
||||
ag and pad_to_jtag through strapping gpio10 when b
|
||||
oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa
|
||||
l to 0.
|
||||
SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = 0 R/W (0b00)
|
||||
AG can be activated temporarily by HMAC peripheral
|
||||
DIS_PAD_JTAG (BLOCK0) Permanently disable JTAG access via pads. USB JTAG = False R/W (0b0)
|
||||
is controlled separately.
|
||||
|
||||
Security fuses:
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0)
|
||||
des
|
||||
SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000)
|
||||
t mode is set. Enabled when 1 or 3 bits are set,di
|
||||
sabled otherwise
|
||||
SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0)
|
||||
KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0)
|
||||
SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0)
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0)
|
||||
DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0)
|
||||
ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0)
|
||||
h only)
|
||||
BLOCK_KEY0 (BLOCK4)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key0 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY1 (BLOCK5)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key1 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY2 (BLOCK6)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key2 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY3 (BLOCK7)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key3 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY4 (BLOCK8)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key4 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY5 (BLOCK9)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key5 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_SYS_DATA2 (BLOCK10)(0 errors): System data (part 2)
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Spi_Pad_Config fuses:
|
||||
SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000)
|
||||
|
||||
Usb Config fuses:
|
||||
DIS_USB_JTAG (BLOCK0) Disables USB JTAG. JTAG access via pads is control = False R/W (0b0)
|
||||
led separately
|
||||
DIS_USB_DEVICE (BLOCK0) Disables USB DEVICE = False R/W (0b0)
|
||||
DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0)
|
||||
USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0)
|
||||
DIS_USB_DOWNLOAD_MODE (BLOCK0) Disables use of USB in UART download boot mode = False R/W (0b0)
|
||||
|
||||
Vdd_Spi Config fuses:
|
||||
PIN_POWER_SELECTION (BLOCK0) GPIO33-GPIO37 power supply selection in ROM code = VDD3P3_CPU R/W (0b0)
|
||||
|
||||
Wdt Config fuses:
|
||||
WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = False R/W (0b0)
|
||||
|
||||
|
||||
To get a dump for all eFuse registers.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
espefuse.py -p PORT dump
|
||||
|
||||
Connecting....
|
||||
Detecting chip type... ESP32-C3
|
||||
BLOCK0 ( ) [0 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: a1404008 00007cdf 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_USR_DATA (BLOCK3 ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY0 (BLOCK4 ) [4 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY1 (BLOCK5 ) [5 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY2 (BLOCK6 ) [6 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY3 (BLOCK7 ) [7 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY4 (BLOCK8 ) [8 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY5 (BLOCK9 ) [9 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA2 (BLOCK10 ) [10] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
espefuse.py v3.1-dev
|
||||
172
docs/en/api-reference/system/inc/espefuse_summary_ESP32-S2.rst
Normal file
172
docs/en/api-reference/system/inc/espefuse_summary_ESP32-S2.rst
Normal file
@ -0,0 +1,172 @@
|
||||
.. code-block:: none
|
||||
|
||||
espefuse.py -p PORT summary
|
||||
|
||||
Connecting....
|
||||
Detecting chip type... ESP32-S2
|
||||
espefuse.py v3.1-dev
|
||||
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
|
||||
----------------------------------------------------------------------------------------
|
||||
Calibration fuses:
|
||||
TEMP_SENSOR_CAL (BLOCK2) Temperature calibration = -9.200000000000001 R/W (0b101011100)
|
||||
ADC1_MODE0_D2 (BLOCK2) ADC1 calibration 1 = -28 R/W (0x87)
|
||||
ADC1_MODE1_D2 (BLOCK2) ADC1 calibration 2 = -28 R/W (0x87)
|
||||
ADC1_MODE2_D2 (BLOCK2) ADC1 calibration 3 = -28 R/W (0x87)
|
||||
ADC1_MODE3_D2 (BLOCK2) ADC1 calibration 4 = -24 R/W (0x86)
|
||||
ADC2_MODE0_D2 (BLOCK2) ADC2 calibration 5 = 12 R/W (0x03)
|
||||
ADC2_MODE1_D2 (BLOCK2) ADC2 calibration 6 = 8 R/W (0x02)
|
||||
ADC2_MODE2_D2 (BLOCK2) ADC2 calibration 7 = 12 R/W (0x03)
|
||||
ADC2_MODE3_D2 (BLOCK2) ADC2 calibration 8 = 16 R/W (0x04)
|
||||
ADC1_MODE0_D1 (BLOCK2) ADC1 calibration 9 = -20 R/W (0b100101)
|
||||
ADC1_MODE1_D1 (BLOCK2) ADC1 calibration 10 = -12 R/W (0b100011)
|
||||
ADC1_MODE2_D1 (BLOCK2) ADC1 calibration 11 = -12 R/W (0b100011)
|
||||
ADC1_MODE3_D1 (BLOCK2) ADC1 calibration 12 = -4 R/W (0b100001)
|
||||
ADC2_MODE0_D1 (BLOCK2) ADC2 calibration 13 = -12 R/W (0b100011)
|
||||
ADC2_MODE1_D1 (BLOCK2) ADC2 calibration 14 = -8 R/W (0b100010)
|
||||
ADC2_MODE2_D1 (BLOCK2) ADC2 calibration 15 = -8 R/W (0b100010)
|
||||
ADC2_MODE3_D1 (BLOCK2) ADC2 calibration 16 = -4 R/W (0b100001)
|
||||
|
||||
Config fuses:
|
||||
DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0)
|
||||
DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0)
|
||||
DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0)
|
||||
DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0)
|
||||
DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0)
|
||||
DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0)
|
||||
DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0)
|
||||
DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0)
|
||||
ace
|
||||
FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0)
|
||||
unit is (ms/2). When the value is 15, delay is 7.
|
||||
5 ms
|
||||
DIS_LEGACY_SPI_BOOT (BLOCK0) Disables Legacy SPI boot mode = False R/W (0b0)
|
||||
UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0)
|
||||
DIS_USB_DOWNLOAD_MODE (BLOCK0) Disables use of USB in UART download boot mode = False R/W (0b0)
|
||||
UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00)
|
||||
FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0)
|
||||
FORCE_SEND_RESUME (BLOCK0) Forces ROM code to send an SPI flash resume comman = False R/W (0b0)
|
||||
d during SPI boot
|
||||
BLOCK_USR_DATA (BLOCK3) User data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Efuse fuses:
|
||||
WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000)
|
||||
RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000)
|
||||
|
||||
Identity fuses:
|
||||
BLOCK0_VERSION (BLOCK0) BLOCK0 efuse version = 0 R/W (0b00)
|
||||
SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000)
|
||||
ure)
|
||||
MAC (BLOCK1) Factory MAC Address
|
||||
= 7c:df:a1:00:3a:6e: (OK) R/W
|
||||
WAFER_VERSION (BLOCK1) WAFER version = A R/W (0b000)
|
||||
PKG_VERSION (BLOCK1) Package version
|
||||
= ESP32-S2, QFN 7x7 56 pins R/W (0x0)
|
||||
BLOCK1_VERSION (BLOCK1) BLOCK1 efuse version = 0 R/W (0b000)
|
||||
OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors): Optional unique 128-bit ID
|
||||
= 7d 33 b8 bb 0b 13 b3 c8 71 37 0e e8 7c ab d5 92 R/W
|
||||
BLOCK2_VERSION (BLOCK2) Version of BLOCK2 = With calibration R/W (0b001)
|
||||
|
||||
Security fuses:
|
||||
SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = False R/W (0b0)
|
||||
AG can be activated temporarily by HMAC peripheral
|
||||
HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0)
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0)
|
||||
des
|
||||
SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000)
|
||||
t mode is set. Enabled when 1 or 3 bits are set,di
|
||||
sabled otherwise
|
||||
SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0)
|
||||
KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0)
|
||||
SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0)
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0)
|
||||
DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0)
|
||||
ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0)
|
||||
h only)
|
||||
BLOCK_KEY0 (BLOCK4)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key0 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY1 (BLOCK5)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key1 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY2 (BLOCK6)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key2 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY3 (BLOCK7)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key3 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY4 (BLOCK8)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key4 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY5 (BLOCK9)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key5 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_SYS_DATA2 (BLOCK10) System data (part 2)
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Spi_Pad_Config fuses:
|
||||
SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000)
|
||||
|
||||
Usb Config fuses:
|
||||
DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0)
|
||||
USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0)
|
||||
EXT_PHY_ENABLE (BLOCK0) Enables external USB PHY = False R/W (0b0)
|
||||
USB_FORCE_NOPERSIST (BLOCK0) Forces to set USB BVALID to 1 = False R/W (0b0)
|
||||
|
||||
Vdd_Spi Config fuses:
|
||||
VDD_SPI_FORCE (BLOCK0) Force using VDD_SPI_XPD and VDD_SPI_TIEH to config = False R/W (0b0)
|
||||
ure VDD_SPI LDO
|
||||
VDD_SPI_XPD (BLOCK0) The VDD_SPI regulator is powered on = False R/W (0b0)
|
||||
VDD_SPI_TIEH (BLOCK0) The VDD_SPI power supply voltage at reset = Connect to 1.8V LDO R/W (0b0)
|
||||
PIN_POWER_SELECTION (BLOCK0) Sets default power supply for GPIO33..37, set when = VDD3P3_CPU R/W (0b0)
|
||||
SPI flash is initialized
|
||||
|
||||
Wdt Config fuses:
|
||||
WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = 0 R/W (0b00)
|
||||
|
||||
Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO
|
||||
GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V).
|
||||
|
||||
To get a dump for all eFuse registers.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
espefuse.py -p PORT dump
|
||||
|
||||
Connecting....
|
||||
Detecting chip type... ESP32-S2
|
||||
BLOCK0 ( ) [0 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: a1003a6e 00007cdf 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: bbb8337d c8b3130b e80e3771 92d5ab7c 8787ae10 02038687 38e50403 8628a386
|
||||
BLOCK_USR_DATA (BLOCK3 ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY0 (BLOCK4 ) [4 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY1 (BLOCK5 ) [5 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY2 (BLOCK6 ) [6 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY3 (BLOCK7 ) [7 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY4 (BLOCK8 ) [8 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY5 (BLOCK9 ) [9 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA2 (BLOCK10 ) [10] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
espefuse.py v3.1-dev
|
||||
172
docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst
Normal file
172
docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst
Normal file
@ -0,0 +1,172 @@
|
||||
.. code-block:: none
|
||||
|
||||
espefuse.py -p PORT summary
|
||||
|
||||
Connecting....
|
||||
Detecting chip type... ESP32-S3
|
||||
espefuse.py v3.1-dev
|
||||
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
|
||||
----------------------------------------------------------------------------------------
|
||||
Calibration fuses:
|
||||
TEMP_SENSOR_CAL (BLOCK2) Temperature calibration = -9.200000000000001 R/W (0b101011100)
|
||||
ADC1_MODE0_D2 (BLOCK2) ADC1 calibration 1 = -28 R/W (0x87)
|
||||
ADC1_MODE1_D2 (BLOCK2) ADC1 calibration 2 = -28 R/W (0x87)
|
||||
ADC1_MODE2_D2 (BLOCK2) ADC1 calibration 3 = -28 R/W (0x87)
|
||||
ADC1_MODE3_D2 (BLOCK2) ADC1 calibration 4 = -24 R/W (0x86)
|
||||
ADC2_MODE0_D2 (BLOCK2) ADC2 calibration 5 = 12 R/W (0x03)
|
||||
ADC2_MODE1_D2 (BLOCK2) ADC2 calibration 6 = 8 R/W (0x02)
|
||||
ADC2_MODE2_D2 (BLOCK2) ADC2 calibration 7 = 12 R/W (0x03)
|
||||
ADC2_MODE3_D2 (BLOCK2) ADC2 calibration 8 = 16 R/W (0x04)
|
||||
ADC1_MODE0_D1 (BLOCK2) ADC1 calibration 9 = -20 R/W (0b100101)
|
||||
ADC1_MODE1_D1 (BLOCK2) ADC1 calibration 10 = -12 R/W (0b100011)
|
||||
ADC1_MODE2_D1 (BLOCK2) ADC1 calibration 11 = -12 R/W (0b100011)
|
||||
ADC1_MODE3_D1 (BLOCK2) ADC1 calibration 12 = -4 R/W (0b100001)
|
||||
ADC2_MODE0_D1 (BLOCK2) ADC2 calibration 13 = -12 R/W (0b100011)
|
||||
ADC2_MODE1_D1 (BLOCK2) ADC2 calibration 14 = -8 R/W (0b100010)
|
||||
ADC2_MODE2_D1 (BLOCK2) ADC2 calibration 15 = -8 R/W (0b100010)
|
||||
ADC2_MODE3_D1 (BLOCK2) ADC2 calibration 16 = -4 R/W (0b100001)
|
||||
|
||||
Config fuses:
|
||||
DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0)
|
||||
DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0)
|
||||
DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0)
|
||||
DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0)
|
||||
DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0)
|
||||
DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0)
|
||||
DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0)
|
||||
DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0)
|
||||
ace
|
||||
FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0)
|
||||
unit is (ms/2). When the value is 15, delay is 7.
|
||||
5 ms
|
||||
DIS_LEGACY_SPI_BOOT (BLOCK0) Disables Legacy SPI boot mode = False R/W (0b0)
|
||||
UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0)
|
||||
DIS_USB_DOWNLOAD_MODE (BLOCK0) Disables use of USB in UART download boot mode = False R/W (0b0)
|
||||
UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00)
|
||||
FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0)
|
||||
FORCE_SEND_RESUME (BLOCK0) Forces ROM code to send an SPI flash resume comman = False R/W (0b0)
|
||||
d during SPI boot
|
||||
BLOCK_USR_DATA (BLOCK3) User data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Efuse fuses:
|
||||
WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000)
|
||||
RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000)
|
||||
|
||||
Identity fuses:
|
||||
BLOCK0_VERSION (BLOCK0) BLOCK0 efuse version = 0 R/W (0b00)
|
||||
SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000)
|
||||
ure)
|
||||
MAC (BLOCK1) Factory MAC Address
|
||||
= 7c:df:a1:00:3a:6e: (OK) R/W
|
||||
WAFER_VERSION (BLOCK1) WAFER version = A R/W (0b000)
|
||||
PKG_VERSION (BLOCK1) Package version
|
||||
= ESP32-S3, QFN 7x7 56 pins R/W (0x0)
|
||||
BLOCK1_VERSION (BLOCK1) BLOCK1 efuse version = 0 R/W (0b000)
|
||||
OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors): Optional unique 128-bit ID
|
||||
= 7d 33 b8 bb 0b 13 b3 c8 71 37 0e e8 7c ab d5 92 R/W
|
||||
BLOCK2_VERSION (BLOCK2) Version of BLOCK2 = With calibration R/W (0b001)
|
||||
|
||||
Security fuses:
|
||||
SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = False R/W (0b0)
|
||||
AG can be activated temporarily by HMAC peripheral
|
||||
HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0)
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0)
|
||||
des
|
||||
SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000)
|
||||
t mode is set. Enabled when 1 or 3 bits are set,di
|
||||
sabled otherwise
|
||||
SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0)
|
||||
KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0)
|
||||
KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0)
|
||||
SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0)
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0)
|
||||
DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0)
|
||||
ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0)
|
||||
h only)
|
||||
BLOCK_KEY0 (BLOCK4)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key0 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY1 (BLOCK5)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key1 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY2 (BLOCK6)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key2 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY3 (BLOCK7)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key3 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY4 (BLOCK8)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key4 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY5 (BLOCK9)(0 errors):
|
||||
Purpose: USER
|
||||
Encryption key5 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_SYS_DATA2 (BLOCK10) System data (part 2)
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Spi_Pad_Config fuses:
|
||||
SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000)
|
||||
SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000)
|
||||
|
||||
Usb Config fuses:
|
||||
DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0)
|
||||
USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0)
|
||||
EXT_PHY_ENABLE (BLOCK0) Enables external USB PHY = False R/W (0b0)
|
||||
USB_FORCE_NOPERSIST (BLOCK0) Forces to set USB BVALID to 1 = False R/W (0b0)
|
||||
|
||||
Vdd_Spi Config fuses:
|
||||
VDD_SPI_FORCE (BLOCK0) Force using VDD_SPI_XPD and VDD_SPI_TIEH to config = False R/W (0b0)
|
||||
ure VDD_SPI LDO
|
||||
VDD_SPI_XPD (BLOCK0) The VDD_SPI regulator is powered on = False R/W (0b0)
|
||||
VDD_SPI_TIEH (BLOCK0) The VDD_SPI power supply voltage at reset = Connect to 1.8V LDO R/W (0b0)
|
||||
PIN_POWER_SELECTION (BLOCK0) Sets default power supply for GPIO33..37, set when = VDD3P3_CPU R/W (0b0)
|
||||
SPI flash is initialized
|
||||
|
||||
Wdt Config fuses:
|
||||
WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = 0 R/W (0b00)
|
||||
|
||||
Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO
|
||||
GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V).
|
||||
|
||||
To get a dump for all eFuse registers.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
espefuse.py -p PORT dump
|
||||
|
||||
Connecting....
|
||||
Detecting chip type... ESP32-S3
|
||||
BLOCK0 ( ) [0 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: a1003a6e 00007cdf 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: bbb8337d c8b3130b e80e3771 92d5ab7c 8787ae10 02038687 38e50403 8628a386
|
||||
BLOCK_USR_DATA (BLOCK3 ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY0 (BLOCK4 ) [4 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY1 (BLOCK5 ) [5 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY2 (BLOCK6 ) [6 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY3 (BLOCK7 ) [7 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY4 (BLOCK8 ) [8 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY5 (BLOCK9 ) [9 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA2 (BLOCK10 ) [10] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
espefuse.py v3.1-dev
|
||||
79
docs/en/api-reference/system/inc/espefuse_summary_ESP32.rst
Normal file
79
docs/en/api-reference/system/inc/espefuse_summary_ESP32.rst
Normal file
@ -0,0 +1,79 @@
|
||||
.. code-block:: none
|
||||
|
||||
espefuse.py -p PORT summary
|
||||
|
||||
Connecting........__
|
||||
Detecting chip type... ESP32
|
||||
espefuse.py v3.1-dev
|
||||
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
|
||||
----------------------------------------------------------------------------------------
|
||||
Calibration fuses:
|
||||
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = True R/W (0b1)
|
||||
ADC_VREF (BLOCK0): Voltage reference calibration = 1114 R/W (0b00010)
|
||||
ADC1_TP_LOW (BLOCK3): ADC1 150mV reading = 346 R/W (0b0010001)
|
||||
ADC1_TP_HIGH (BLOCK3): ADC1 850mV reading = 3285 R/W (0b000000101)
|
||||
ADC2_TP_LOW (BLOCK3): ADC2 150mV reading = 449 R/W (0b0000111)
|
||||
ADC2_TP_HIGH (BLOCK3): ADC2 850mV reading = 3362 R/W (0b111110101)
|
||||
|
||||
Config fuses:
|
||||
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0)
|
||||
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
|
||||
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
|
||||
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 53 R/W (0x35)
|
||||
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000)
|
||||
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000)
|
||||
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000)
|
||||
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000)
|
||||
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000)
|
||||
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
|
||||
|
||||
Efuse fuses:
|
||||
WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000)
|
||||
RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0)
|
||||
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
|
||||
= 3/4 (BLK1-3 len=192 bits) R/W (0b01)
|
||||
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
|
||||
|
||||
Identity fuses:
|
||||
MAC (BLOCK0): Factory MAC Address
|
||||
= 84:0d:8e:18:8e:44 (CRC 0xad OK) R/W
|
||||
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 173 R/W (0xad)
|
||||
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
|
||||
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
|
||||
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
|
||||
CHIP_PACKAGE (BLOCK0): Chip package identifier = 0 R/W (0b000)
|
||||
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
|
||||
|
||||
Security fuses:
|
||||
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000)
|
||||
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
|
||||
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0)
|
||||
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
|
||||
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
|
||||
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
|
||||
JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0)
|
||||
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
|
||||
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0)
|
||||
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0)
|
||||
BLOCK1 (BLOCK1): Flash encryption key
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK2 (BLOCK2): Secure boot key
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK3 (BLOCK3): Variable Block 3
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 91 02 87 fa 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).
|
||||
|
||||
To get a dump for all eFuse registers.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
espefuse.py -p PORT dump
|
||||
|
||||
Connecting........_
|
||||
Detecting chip type... ESP32
|
||||
BLOCK0 ( ) [0 ] read_regs: 00000000 8e188e44 00ad840d 0000e000 00000235 00000000 00000005
|
||||
BLOCK1 (flash_encryption) [1 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK2 (secure_boot_v1 s) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK3 ( ) [3 ] read_regs: 00000000 00000000 00000000 fa870291 00000000 00000000
|
||||
espefuse.py v3.1-dev
|
||||
@ -0,0 +1 @@
|
||||
.. include:: ../../../en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst
|
||||
@ -0,0 +1 @@
|
||||
.. include:: ../../../en/api-reference/system/inc/espefuse_summary_ESP32-S2.rst
|
||||
@ -0,0 +1 @@
|
||||
.. include:: ../../../en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst
|
||||
@ -0,0 +1 @@
|
||||
.. include:: ../../../en/api-reference/system/inc/espefuse_summary_ESP32.rst
|
||||
Loading…
Reference in New Issue
Block a user