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fix(soc): Cleanup inaccessible SHA registers from the header files
This commit is contained in:
harshal.patil
parent
e207b08e28
commit
8445486303
@ -172,150 +172,6 @@ extern "C" {
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#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
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#define SHA_M_MEM_SIZE_BYTES 64
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/** SHA_3_MODE_REG register
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* Initial configuration register 0.
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*/
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#define SHA_3_MODE_REG (DR_REG_SHA_BASE + 0x800)
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/** SHA_3_MODE : R/W; bitpos: [2:0]; default: 0;
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* Sha3 mode
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*/
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#define SHA_3_MODE 0x00000007U
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#define SHA_3_MODE_M (SHA_3_MODE_V << SHA_3_MODE_S)
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#define SHA_3_MODE_V 0x00000007U
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#define SHA_3_MODE_S 0
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/** SHA_3_CLEAN_M_REG register
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* Initial configuration register 1.
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*/
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#define SHA_3_CLEAN_M_REG (DR_REG_SHA_BASE + 0x804)
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/** SHA_3_CLEAN_M : WO; bitpos: [0]; default: 0;
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* Clean Message.
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*/
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#define SHA_3_CLEAN_M (BIT(0))
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#define SHA_3_CLEAN_M_M (SHA_3_CLEAN_M_V << SHA_3_CLEAN_M_S)
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#define SHA_3_CLEAN_M_V 0x00000001U
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#define SHA_3_CLEAN_M_S 0
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/** SHA_3_DMA_BLOCK_NUM_REG register
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* DMA configuration register 0.
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*/
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#define SHA_3_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0x80c)
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/** SHA_3_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
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* DMA-SHA3 block number.
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*/
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#define SHA_3_DMA_BLOCK_NUM 0x0000003FU
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#define SHA_3_DMA_BLOCK_NUM_M (SHA_3_DMA_BLOCK_NUM_V << SHA_3_DMA_BLOCK_NUM_S)
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#define SHA_3_DMA_BLOCK_NUM_V 0x0000003FU
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#define SHA_3_DMA_BLOCK_NUM_S 0
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/** SHA_3_START_REG register
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* Typical SHA3 configuration register 0.
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*/
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#define SHA_3_START_REG (DR_REG_SHA_BASE + 0x810)
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/** SHA_3_START : WO; bitpos: [0]; default: 0;
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* Start typical sha3.
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*/
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#define SHA_3_START (BIT(0))
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#define SHA_3_START_M (SHA_3_START_V << SHA_3_START_S)
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#define SHA_3_START_V 0x00000001U
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#define SHA_3_START_S 0
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/** SHA_3_CONTINUE_REG register
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* Typical SHA3 configuration register 1.
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*/
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#define SHA_3_CONTINUE_REG (DR_REG_SHA_BASE + 0x814)
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/** SHA_3_CONTINUE : WO; bitpos: [0]; default: 0;
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* Continue typical sha3.
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*/
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#define SHA_3_CONTINUE (BIT(0))
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#define SHA_3_CONTINUE_M (SHA_3_CONTINUE_V << SHA_3_CONTINUE_S)
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#define SHA_3_CONTINUE_V 0x00000001U
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#define SHA_3_CONTINUE_S 0
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/** SHA_3_BUSY_REG register
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* Busy register.
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*/
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#define SHA_3_BUSY_REG (DR_REG_SHA_BASE + 0x818)
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/** SHA_3_BUSY_REG : RO; bitpos: [0]; default: 0;
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* Sha3 busy state. 1'b0: idle. 1'b1: busy.
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*/
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#define SHA_3_BUSY_REG (BIT(0))
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#define SHA_3_BUSY_REG_M (SHA_3_BUSY_REG_V << SHA_3_BUSY_REG_S)
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#define SHA_3_BUSY_REG_V 0x00000001U
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#define SHA_3_BUSY_REG_S 0
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/** SHA_3_DMA_START_REG register
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* DMA configuration register 1.
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*/
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#define SHA_3_DMA_START_REG (DR_REG_SHA_BASE + 0x81c)
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/** SHA_3_DMA_START : WO; bitpos: [0]; default: 0;
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* Start dma-sha3.
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*/
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#define SHA_3_DMA_START (BIT(0))
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#define SHA_3_DMA_START_M (SHA_3_DMA_START_V << SHA_3_DMA_START_S)
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#define SHA_3_DMA_START_V 0x00000001U
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#define SHA_3_DMA_START_S 0
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/** SHA_3_DMA_CONTINUE_REG register
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* DMA configuration register 2.
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*/
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#define SHA_3_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x820)
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/** SHA_3_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
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* Continue dma-sha3.
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*/
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#define SHA_3_DMA_CONTINUE (BIT(0))
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#define SHA_3_DMA_CONTINUE_M (SHA_3_DMA_CONTINUE_V << SHA_3_DMA_CONTINUE_S)
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#define SHA_3_DMA_CONTINUE_V 0x00000001U
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#define SHA_3_DMA_CONTINUE_S 0
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/** SHA_3_CLEAR_INT_REG register
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* Interrupt clear register.
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*/
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#define SHA_3_CLEAR_INT_REG (DR_REG_SHA_BASE + 0x824)
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/** SHA_3_CLEAR_INT : WO; bitpos: [0]; default: 0;
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* Clear sha3 interrupt.
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*/
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#define SHA_3_CLEAR_INT (BIT(0))
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#define SHA_3_CLEAR_INT_M (SHA_3_CLEAR_INT_V << SHA_3_CLEAR_INT_S)
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#define SHA_3_CLEAR_INT_V 0x00000001U
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#define SHA_3_CLEAR_INT_S 0
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/** SHA_3_INT_ENA_REG register
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* Interrupt enable register.
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*/
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#define SHA_3_INT_ENA_REG (DR_REG_SHA_BASE + 0x828)
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/** SHA_3_INT_ENA : R/W; bitpos: [0]; default: 0;
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* Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable
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*/
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#define SHA_3_INT_ENA (BIT(0))
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#define SHA_3_INT_ENA_M (SHA_3_INT_ENA_V << SHA_3_INT_ENA_S)
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#define SHA_3_INT_ENA_V 0x00000001U
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#define SHA_3_INT_ENA_S 0
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/** SHA_3_SHAKE_LENGTH_REG register
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* DMA configuration register 3.
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*/
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#define SHA_3_SHAKE_LENGTH_REG (DR_REG_SHA_BASE + 0x82c)
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/** SHA_3_SHAKE_LENGTH : WO; bitpos: [10:0]; default: 50;
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* SHAKE output hash word length
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*/
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#define SHA_3_SHAKE_LENGTH 0x000007FFU
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#define SHA_3_SHAKE_LENGTH_M (SHA_3_SHAKE_LENGTH_V << SHA_3_SHAKE_LENGTH_S)
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#define SHA_3_SHAKE_LENGTH_V 0x000007FFU
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#define SHA_3_SHAKE_LENGTH_S 0
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/** SHA_3_M_OUT_MEM register
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* Sha3 hash reg which contains intermediate hash or finial hash.
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*/
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#define SHA_3_M_OUT_MEM (DR_REG_SHA_BASE + 0x900)
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#define SHA_3_M_OUT_MEM_SIZE_BYTES 200
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/** SHA_3_M_MEM register
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* Sha3 message reg which contains message.
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*/
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#define SHA_3_M_MEM (DR_REG_SHA_BASE + 0xa00)
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#define SHA_3_M_MEM_SIZE_BYTES 200
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#ifdef __cplusplus
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}
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#endif
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@ -127,118 +127,6 @@ typedef union {
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uint32_t val;
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} sha_t_length_reg_t;
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/** Type of mode register
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* Initial configuration register 0.
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*/
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typedef union {
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struct {
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/** mode : R/W; bitpos: [2:0]; default: 0;
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* Sha3 mode
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*/
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uint32_t mode:3;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} sha_3_mode_reg_t;
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/** Type of clean_m register
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* Initial configuration register 1.
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*/
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typedef union {
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struct {
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/** clean_m : WO; bitpos: [0]; default: 0;
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* Clean Message.
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*/
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uint32_t clean_m:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_clean_m_reg_t;
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/** Type of dma_block_num register
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* DMA configuration register 0.
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*/
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typedef union {
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struct {
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/** dma_block_num : R/W; bitpos: [5:0]; default: 0;
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* DMA-SHA3 block number.
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*/
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uint32_t dma_block_num:6;
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} sha_3_dma_block_num_reg_t;
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/** Type of start register
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* Typical SHA3 configuration register 0.
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*/
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typedef union {
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struct {
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/** start : WO; bitpos: [0]; default: 0;
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* Start typical sha3.
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*/
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uint32_t start:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_start_reg_t;
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/** Type of continue register
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* Typical SHA3 configuration register 1.
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*/
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typedef union {
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struct {
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/** conti : WO; bitpos: [0]; default: 0;
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* Continue typical sha3.
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*/
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uint32_t conti:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_continue_reg_t;
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/** Type of dma_start register
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* DMA configuration register 1.
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*/
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typedef union {
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struct {
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/** dma_start : WO; bitpos: [0]; default: 0;
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* Start dma-sha3.
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*/
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uint32_t dma_start:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_dma_start_reg_t;
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/** Type of dma_continue register
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* DMA configuration register 2.
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*/
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typedef union {
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struct {
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/** dma_continue : WO; bitpos: [0]; default: 0;
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* Continue dma-sha3.
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*/
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uint32_t dma_continue:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_dma_continue_reg_t;
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/** Type of shake_length register
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* DMA configuration register 3.
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*/
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typedef union {
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struct {
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/** shake_length : WO; bitpos: [10:0]; default: 50;
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* SHAKE output hash word length
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*/
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uint32_t shake_length:11;
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uint32_t reserved_11:21;
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};
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uint32_t val;
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} sha_3_shake_length_reg_t;
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/** Group: Status Registers */
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/** Type of busy register
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@ -306,52 +194,6 @@ typedef union {
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/** Group: memory type */
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/** Group: Status Register */
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/** Type of busy register
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* Busy register.
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*/
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typedef union {
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struct {
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/** busy_reg : RO; bitpos: [0]; default: 0;
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* Sha3 busy state. 1'b0: idle. 1'b1: busy.
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*/
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uint32_t busy_reg:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_busy_reg_t;
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/** Group: Interrupt Register */
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/** Type of clear_int register
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* Interrupt clear register.
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*/
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typedef union {
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struct {
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/** clear_int : WO; bitpos: [0]; default: 0;
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* Clear sha3 interrupt.
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*/
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uint32_t clear_int:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_clear_int_reg_t;
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/** Type of int_ena register
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* Interrupt enable register.
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*/
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typedef union {
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struct {
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/** int_ena : R/W; bitpos: [0]; default: 0;
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* Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable
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*/
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uint32_t int_ena:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_int_ena_reg_t;
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typedef struct {
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volatile sha_mode_reg_t mode;
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volatile sha_t_string_reg_t t_string;
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@ -368,29 +210,12 @@ typedef struct {
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uint32_t reserved_030[4];
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volatile uint32_t h[16];
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volatile uint32_t m[16];
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uint32_t reserved_0c0[464];
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volatile sha_3_mode_reg_t mode_3;
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volatile sha_3_clean_m_reg_t clean_m_3;
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uint32_t reserved_808;
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volatile sha_3_dma_block_num_reg_t dma_block_num_3;
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volatile sha_3_start_reg_t start_3;
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volatile sha_3_continue_reg_t continue_3;
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volatile sha_3_busy_reg_t busy_3;
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volatile sha_3_dma_start_reg_t dma_start_3;
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volatile sha_3_dma_continue_reg_t dma_continue_3;
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volatile sha_3_clear_int_reg_t clear_int_3;
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volatile sha_3_int_ena_reg_t int_ena_3;
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volatile sha_3_shake_length_reg_t shake_length_3;
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uint32_t reserved_830[52];
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volatile uint32_t m_out_3[50];
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uint32_t reserved_9c8[14];
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volatile uint32_t m_3[50];
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} sha_dev_t;
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extern sha_dev_t SHA;
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#ifndef __cplusplus
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_Static_assert(sizeof(sha_dev_t) == 0xac8, "Invalid size of sha_dev_t structure");
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_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
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#endif
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#ifdef __cplusplus
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@ -172,150 +172,6 @@ extern "C" {
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#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
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#define SHA_M_MEM_SIZE_BYTES 64
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/** SHA_3_MODE_REG register
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* Initial configuration register 0.
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*/
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#define SHA_3_MODE_REG (DR_REG_SHA_BASE + 0x800)
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/** SHA_3_MODE : R/W; bitpos: [2:0]; default: 0;
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* Sha3 mode
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*/
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#define SHA_3_MODE 0x00000007U
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#define SHA_3_MODE_M (SHA_3_MODE_V << SHA_3_MODE_S)
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#define SHA_3_MODE_V 0x00000007U
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#define SHA_3_MODE_S 0
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/** SHA_3_CLEAN_M_REG register
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* Initial configuration register 1.
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*/
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#define SHA_3_CLEAN_M_REG (DR_REG_SHA_BASE + 0x804)
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/** SHA_3_CLEAN_M : WO; bitpos: [0]; default: 0;
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* Clean Message.
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*/
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#define SHA_3_CLEAN_M (BIT(0))
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#define SHA_3_CLEAN_M_M (SHA_3_CLEAN_M_V << SHA_3_CLEAN_M_S)
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#define SHA_3_CLEAN_M_V 0x00000001U
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#define SHA_3_CLEAN_M_S 0
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/** SHA_3_DMA_BLOCK_NUM_REG register
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* DMA configuration register 0.
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*/
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#define SHA_3_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0x80c)
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/** SHA_3_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
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* DMA-SHA3 block number.
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*/
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#define SHA_3_DMA_BLOCK_NUM 0x0000003FU
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#define SHA_3_DMA_BLOCK_NUM_M (SHA_3_DMA_BLOCK_NUM_V << SHA_3_DMA_BLOCK_NUM_S)
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#define SHA_3_DMA_BLOCK_NUM_V 0x0000003FU
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#define SHA_3_DMA_BLOCK_NUM_S 0
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/** SHA_3_START_REG register
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* Typical SHA3 configuration register 0.
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*/
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#define SHA_3_START_REG (DR_REG_SHA_BASE + 0x810)
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/** SHA_3_START : WO; bitpos: [0]; default: 0;
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* Start typical sha3.
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*/
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#define SHA_3_START (BIT(0))
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#define SHA_3_START_M (SHA_3_START_V << SHA_3_START_S)
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#define SHA_3_START_V 0x00000001U
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#define SHA_3_START_S 0
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/** SHA_3_CONTINUE_REG register
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* Typical SHA3 configuration register 1.
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*/
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#define SHA_3_CONTINUE_REG (DR_REG_SHA_BASE + 0x814)
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/** SHA_3_CONTINUE : WO; bitpos: [0]; default: 0;
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* Continue typical sha3.
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*/
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#define SHA_3_CONTINUE (BIT(0))
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#define SHA_3_CONTINUE_M (SHA_3_CONTINUE_V << SHA_3_CONTINUE_S)
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#define SHA_3_CONTINUE_V 0x00000001U
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#define SHA_3_CONTINUE_S 0
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/** SHA_3_BUSY_REG register
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* Busy register.
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*/
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#define SHA_3_BUSY_REG (DR_REG_SHA_BASE + 0x818)
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/** SHA_3_BUSY_REG : RO; bitpos: [0]; default: 0;
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* Sha3 busy state. 1'b0: idle. 1'b1: busy.
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*/
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#define SHA_3_BUSY_REG (BIT(0))
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#define SHA_3_BUSY_REG_M (SHA_3_BUSY_REG_V << SHA_3_BUSY_REG_S)
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#define SHA_3_BUSY_REG_V 0x00000001U
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#define SHA_3_BUSY_REG_S 0
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/** SHA_3_DMA_START_REG register
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* DMA configuration register 1.
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*/
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#define SHA_3_DMA_START_REG (DR_REG_SHA_BASE + 0x81c)
|
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/** SHA_3_DMA_START : WO; bitpos: [0]; default: 0;
|
||||
* Start dma-sha3.
|
||||
*/
|
||||
#define SHA_3_DMA_START (BIT(0))
|
||||
#define SHA_3_DMA_START_M (SHA_3_DMA_START_V << SHA_3_DMA_START_S)
|
||||
#define SHA_3_DMA_START_V 0x00000001U
|
||||
#define SHA_3_DMA_START_S 0
|
||||
|
||||
/** SHA_3_DMA_CONTINUE_REG register
|
||||
* DMA configuration register 2.
|
||||
*/
|
||||
#define SHA_3_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x820)
|
||||
/** SHA_3_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
|
||||
* Continue dma-sha3.
|
||||
*/
|
||||
#define SHA_3_DMA_CONTINUE (BIT(0))
|
||||
#define SHA_3_DMA_CONTINUE_M (SHA_3_DMA_CONTINUE_V << SHA_3_DMA_CONTINUE_S)
|
||||
#define SHA_3_DMA_CONTINUE_V 0x00000001U
|
||||
#define SHA_3_DMA_CONTINUE_S 0
|
||||
|
||||
/** SHA_3_CLEAR_INT_REG register
|
||||
* Interrupt clear register.
|
||||
*/
|
||||
#define SHA_3_CLEAR_INT_REG (DR_REG_SHA_BASE + 0x824)
|
||||
/** SHA_3_CLEAR_INT : WO; bitpos: [0]; default: 0;
|
||||
* Clear sha3 interrupt.
|
||||
*/
|
||||
#define SHA_3_CLEAR_INT (BIT(0))
|
||||
#define SHA_3_CLEAR_INT_M (SHA_3_CLEAR_INT_V << SHA_3_CLEAR_INT_S)
|
||||
#define SHA_3_CLEAR_INT_V 0x00000001U
|
||||
#define SHA_3_CLEAR_INT_S 0
|
||||
|
||||
/** SHA_3_INT_ENA_REG register
|
||||
* Interrupt enable register.
|
||||
*/
|
||||
#define SHA_3_INT_ENA_REG (DR_REG_SHA_BASE + 0x828)
|
||||
/** SHA_3_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable
|
||||
*/
|
||||
#define SHA_3_INT_ENA (BIT(0))
|
||||
#define SHA_3_INT_ENA_M (SHA_3_INT_ENA_V << SHA_3_INT_ENA_S)
|
||||
#define SHA_3_INT_ENA_V 0x00000001U
|
||||
#define SHA_3_INT_ENA_S 0
|
||||
|
||||
/** SHA_3_SHAKE_LENGTH_REG register
|
||||
* DMA configuration register 3.
|
||||
*/
|
||||
#define SHA_3_SHAKE_LENGTH_REG (DR_REG_SHA_BASE + 0x82c)
|
||||
/** SHA_3_SHAKE_LENGTH : WO; bitpos: [10:0]; default: 50;
|
||||
* SHAKE output hash word length
|
||||
*/
|
||||
#define SHA_3_SHAKE_LENGTH 0x000007FFU
|
||||
#define SHA_3_SHAKE_LENGTH_M (SHA_3_SHAKE_LENGTH_V << SHA_3_SHAKE_LENGTH_S)
|
||||
#define SHA_3_SHAKE_LENGTH_V 0x000007FFU
|
||||
#define SHA_3_SHAKE_LENGTH_S 0
|
||||
|
||||
/** SHA_3_M_OUT_MEM register
|
||||
* Sha3 hash reg which contains intermediate hash or finial hash.
|
||||
*/
|
||||
#define SHA_3_M_OUT_MEM (DR_REG_SHA_BASE + 0x900)
|
||||
#define SHA_3_M_OUT_MEM_SIZE_BYTES 200
|
||||
|
||||
/** SHA_3_M_MEM register
|
||||
* Sha3 message reg which contains message.
|
||||
*/
|
||||
#define SHA_3_M_MEM (DR_REG_SHA_BASE + 0xa00)
|
||||
#define SHA_3_M_MEM_SIZE_BYTES 200
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -127,118 +127,6 @@ typedef union {
|
||||
uint32_t val;
|
||||
} sha_t_length_reg_t;
|
||||
|
||||
/** Type of mode_3 register
|
||||
* Initial configuration register 0.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mode_3 : R/W; bitpos: [2:0]; default: 0;
|
||||
* Sha3 mode
|
||||
*/
|
||||
uint32_t mode_3:3;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_mode_reg_t;
|
||||
|
||||
/** Type of clean_m_3 register
|
||||
* Initial configuration register 1.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clean_m_3 : WO; bitpos: [0]; default: 0;
|
||||
* Clean Message.
|
||||
*/
|
||||
uint32_t clean_m_3:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_clean_m_reg_t;
|
||||
|
||||
/** Type of dma_block_num_3 register
|
||||
* DMA configuration register 0.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_block_num_3 : R/W; bitpos: [5:0]; default: 0;
|
||||
* DMA-SHA3 block number.
|
||||
*/
|
||||
uint32_t dma_block_num_3:6;
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_dma_block_num_reg_t;
|
||||
|
||||
/** Type of start_3 register
|
||||
* Typical SHA3 configuration register 0.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** start_3 : WO; bitpos: [0]; default: 0;
|
||||
* Start typical sha3.
|
||||
*/
|
||||
uint32_t start_3:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_start_reg_t;
|
||||
|
||||
/** Type of continue_3 register
|
||||
* Typical SHA3 configuration register 1.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** continue_3 : WO; bitpos: [0]; default: 0;
|
||||
* Continue typical sha3.
|
||||
*/
|
||||
uint32_t continue_3:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_continue_reg_t;
|
||||
|
||||
/** Type of dma_start_3 register
|
||||
* DMA configuration register 1.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_start_3 : WO; bitpos: [0]; default: 0;
|
||||
* Start dma-sha3.
|
||||
*/
|
||||
uint32_t dma_start_3:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_dma_start_reg_t;
|
||||
|
||||
/** Type of dma_continue_3 register
|
||||
* DMA configuration register 2.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_continue_3 : WO; bitpos: [0]; default: 0;
|
||||
* Continue dma-sha3.
|
||||
*/
|
||||
uint32_t dma_continue_3:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_dma_continue_reg_t;
|
||||
|
||||
/** Type of shake_length_3 register
|
||||
* DMA configuration register 3.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** shake_length_3 : WO; bitpos: [10:0]; default: 50;
|
||||
* SHAKE output hash word length
|
||||
*/
|
||||
uint32_t shake_length_3:11;
|
||||
uint32_t reserved_11:21;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_shake_length_reg_t;
|
||||
|
||||
|
||||
/** Group: Status Registers */
|
||||
/** Type of busy register
|
||||
@ -306,52 +194,6 @@ typedef union {
|
||||
|
||||
/** Group: memory type */
|
||||
|
||||
/** Group: Status Register */
|
||||
/** Type of busy_3 register
|
||||
* Busy register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** busy_reg_3 : RO; bitpos: [0]; default: 0;
|
||||
* Sha3 busy state. 1'b0: idle. 1'b1: busy.
|
||||
*/
|
||||
uint32_t busy_reg_3:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_busy_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt Register */
|
||||
/** Type of clear_int_3 register
|
||||
* Interrupt clear register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clear_int_3 : WO; bitpos: [0]; default: 0;
|
||||
* Clear sha3 interrupt.
|
||||
*/
|
||||
uint32_t clear_int_3:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_clear_int_reg_t;
|
||||
|
||||
/** Type of int_ena_3 register
|
||||
* Interrupt enable register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** int_ena_3 : R/W; bitpos: [0]; default: 0;
|
||||
* Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable
|
||||
*/
|
||||
uint32_t int_ena_3:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sha_3_int_ena_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile sha_mode_reg_t mode;
|
||||
volatile sha_t_string_reg_t t_string;
|
||||
@ -368,29 +210,12 @@ typedef struct {
|
||||
uint32_t reserved_030[4];
|
||||
volatile uint32_t h[16];
|
||||
volatile uint32_t m[16];
|
||||
uint32_t reserved_0c0[464];
|
||||
volatile sha_3_mode_reg_t mode_3;
|
||||
volatile sha_3_clean_m_reg_t clean_m_3;
|
||||
uint32_t reserved_808;
|
||||
volatile sha_3_dma_block_num_reg_t dma_block_num_3;
|
||||
volatile sha_3_start_reg_t start_3;
|
||||
volatile sha_3_continue_reg_t continue_3;
|
||||
volatile sha_3_busy_reg_t busy_3;
|
||||
volatile sha_3_dma_start_reg_t dma_start_3;
|
||||
volatile sha_3_dma_continue_reg_t dma_continue_3;
|
||||
volatile sha_3_clear_int_reg_t clear_int_3;
|
||||
volatile sha_3_int_ena_reg_t int_ena_3;
|
||||
volatile sha_3_shake_length_reg_t shake_length_3;
|
||||
uint32_t reserved_830[52];
|
||||
volatile uint32_t m_out_3[50];
|
||||
uint32_t reserved_9c8[14];
|
||||
volatile uint32_t m_3[50];
|
||||
} sha_dev_t;
|
||||
|
||||
extern sha_dev_t SHA;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(sha_dev_t) == 0xac8, "Invalid size of sha_dev_t structure");
|
||||
_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
Loading…
Reference in New Issue
Block a user