mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-19 14:26:01 -04:00
rgb_lcd: support fractional clock divisor
This commit is contained in:
morris
parent
8dd26e9e9f
commit
843279d287
@ -248,7 +248,7 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p
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ESP_GOTO_ON_FALSE(!bus_exclusive, ESP_ERR_INVALID_STATE, err, TAG, "bus has been exclusively owned by device");
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// check if pixel clock setting is valid
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uint32_t pclk_prescale = bus->resolution_hz / io_config->pclk_hz;
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ESP_GOTO_ON_FALSE(pclk_prescale > 0 && pclk_prescale <= LCD_LL_CLOCK_PRESCALE_MAX, ESP_ERR_NOT_SUPPORTED, err, TAG,
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ESP_GOTO_ON_FALSE(pclk_prescale > 0 && pclk_prescale <= LCD_LL_PCLK_DIV_MAX, ESP_ERR_NOT_SUPPORTED, err, TAG,
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"prescaler can't satisfy PCLK clock %u", io_config->pclk_hz);
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i80_device = heap_caps_calloc(1, sizeof(lcd_panel_io_i80_t) + io_config->trans_queue_depth * sizeof(lcd_i80_trans_descriptor_t), LCD_I80_MEM_ALLOC_CAPS);
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ESP_GOTO_ON_FALSE(i80_device, ESP_ERR_NO_MEM, err, TAG, "no mem for i80 panel io");
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@ -472,7 +472,8 @@ static esp_err_t lcd_i80_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c
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{
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esp_err_t ret = ESP_OK;
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// force to use integer division, as fractional division might lead to clock jitter
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lcd_ll_set_group_clock_src(bus->hal.dev, clk_src, LCD_PERIPH_CLOCK_PRE_SCALE, 0, 0);
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lcd_ll_select_clk_src(bus->hal.dev, clk_src);
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lcd_ll_set_group_clock_coeff(bus->hal.dev, LCD_PERIPH_CLOCK_PRE_SCALE, 0, 0);
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switch (clk_src) {
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case LCD_CLK_SRC_PLL160M:
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bus->resolution_hz = 160000000 / LCD_PERIPH_CLOCK_PRE_SCALE;
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@ -61,7 +61,7 @@ static esp_err_t rgb_panel_mirror(esp_lcd_panel_t *panel, bool mirror_x, bool mi
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static esp_err_t rgb_panel_swap_xy(esp_lcd_panel_t *panel, bool swap_axes);
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static esp_err_t rgb_panel_set_gap(esp_lcd_panel_t *panel, int x_gap, int y_gap);
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static esp_err_t rgb_panel_disp_on_off(esp_lcd_panel_t *panel, bool off);
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static esp_err_t lcd_rgb_panel_select_periph_clock(esp_rgb_panel_t *panel, lcd_clock_source_t clk_src);
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static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *panel, lcd_clock_source_t clk_src);
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static esp_err_t lcd_rgb_panel_create_trans_link(esp_rgb_panel_t *panel);
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static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_lcd_rgb_panel_config_t *panel_config);
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static void lcd_rgb_panel_start_transmission(esp_rgb_panel_t *rgb_panel);
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@ -81,7 +81,7 @@ struct esp_rgb_panel_t {
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uint8_t *fb; // Frame buffer
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size_t fb_size; // Size of frame buffer
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int data_gpio_nums[SOC_LCD_RGB_DATA_WIDTH]; // GPIOs used for data lines, we keep these GPIOs for action like "invert_color"
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size_t resolution_hz; // Peripheral clock resolution
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uint32_t src_clk_hz; // Peripheral source clock resolution
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esp_lcd_rgb_timing_t timings; // RGB timing parameters (e.g. pclk, sync pulse, porch width)
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gdma_channel_handle_t dma_chan; // DMA channel handle
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esp_lcd_rgb_panel_frame_trans_done_cb_t on_frame_trans_done; // Callback, invoked after frame trans done
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@ -159,9 +159,11 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
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rgb_panel->flags.fb_in_psram = alloc_from_psram;
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// initialize HAL layer, so we can call LL APIs later
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lcd_hal_init(&rgb_panel->hal, panel_id);
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// set peripheral clock resolution
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ret = lcd_rgb_panel_select_periph_clock(rgb_panel, rgb_panel_config->clk_src);
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ESP_GOTO_ON_ERROR(ret, err, TAG, "select periph clock failed");
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// enable clock gating
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lcd_ll_enable_clock(rgb_panel->hal.dev, true);
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// set clock source
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ret = lcd_rgb_panel_select_clock_src(rgb_panel, rgb_panel_config->clk_src);
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ESP_GOTO_ON_ERROR(ret, err, TAG, "set source clock failed");
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// install interrupt service, (LCD peripheral shares the interrupt source with Camera by different mask)
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int isr_flags = LCD_RGB_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED;
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ret = esp_intr_alloc_intrstatus(lcd_periph_signals.panels[panel_id].irq_id, isr_flags,
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@ -232,6 +234,7 @@ static esp_err_t rgb_panel_del(esp_lcd_panel_t *panel)
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gdma_disconnect(rgb_panel->dma_chan);
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gdma_del_channel(rgb_panel->dma_chan);
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esp_intr_free(rgb_panel->intr);
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lcd_ll_enable_clock(rgb_panel->hal.dev, false);
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periph_module_disable(lcd_periph_signals.panels[panel_id].module);
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lcd_com_remove_device(LCD_COM_DEVICE_TYPE_RGB, rgb_panel->panel_id);
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free(rgb_panel->fb);
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@ -256,14 +259,8 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel)
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{
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esp_err_t ret = ESP_OK;
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esp_rgb_panel_t *rgb_panel = __containerof(panel, esp_rgb_panel_t, base);
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// configure clock
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lcd_ll_enable_clock(rgb_panel->hal.dev, true);
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// set PCLK frequency
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uint32_t pclk_prescale = rgb_panel->resolution_hz / rgb_panel->timings.pclk_hz;
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ESP_GOTO_ON_FALSE(pclk_prescale <= LCD_LL_CLOCK_PRESCALE_MAX, ESP_ERR_NOT_SUPPORTED, err, TAG,
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"prescaler can't satisfy PCLK clock %uHz", rgb_panel->timings.pclk_hz);
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lcd_ll_set_pixel_clock_prescale(rgb_panel->hal.dev, pclk_prescale);
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rgb_panel->timings.pclk_hz = rgb_panel->resolution_hz / pclk_prescale;
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// set pixel clock frequency
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rgb_panel->timings.pclk_hz = lcd_hal_cal_pclk_freq(&rgb_panel->hal, rgb_panel->src_clk_hz, rgb_panel->timings.pclk_hz);
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// pixel clock phase and polarity
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lcd_ll_set_clock_idle_level(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_idle_high);
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lcd_ll_set_pixel_clock_edge(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_active_neg);
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@ -299,7 +296,6 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel)
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lcd_rgb_panel_start_transmission(rgb_panel);
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}
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ESP_LOGD(TAG, "rgb panel(%d) start, pclk=%uHz", rgb_panel->panel_id, rgb_panel->timings.pclk_hz);
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err:
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return ret;
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}
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@ -442,14 +438,12 @@ static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_
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return ESP_OK;
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}
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static esp_err_t lcd_rgb_panel_select_periph_clock(esp_rgb_panel_t *panel, lcd_clock_source_t clk_src)
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static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *panel, lcd_clock_source_t clk_src)
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{
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esp_err_t ret = ESP_OK;
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// force to use integer division, as fractional division might lead to clock jitter
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lcd_ll_set_group_clock_src(panel->hal.dev, clk_src, LCD_PERIPH_CLOCK_PRE_SCALE, 0, 0);
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switch (clk_src) {
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case LCD_CLK_SRC_PLL160M:
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panel->resolution_hz = 160000000 / LCD_PERIPH_CLOCK_PRE_SCALE;
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panel->src_clk_hz = 160000000;
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#if CONFIG_PM_ENABLE
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ret = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "rgb_panel", &panel->pm_lock);
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ESP_RETURN_ON_ERROR(ret, TAG, "create ESP_PM_APB_FREQ_MAX lock failed");
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@ -459,12 +453,13 @@ static esp_err_t lcd_rgb_panel_select_periph_clock(esp_rgb_panel_t *panel, lcd_c
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#endif
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break;
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case LCD_CLK_SRC_XTAL:
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panel->resolution_hz = esp_clk_xtal_freq() / LCD_PERIPH_CLOCK_PRE_SCALE;
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panel->src_clk_hz = esp_clk_xtal_freq();
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break;
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default:
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ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "unsupported clock source: %d", clk_src);
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break;
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}
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lcd_ll_select_clk_src(panel->hal.dev, clk_src);
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return ret;
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}
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@ -23,8 +23,9 @@ extern "C" {
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#define LCD_LL_EVENT_VSYNC_END (1 << 0)
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#define LCD_LL_EVENT_TRANS_DONE (1 << 1)
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// Maximum coefficient of clock prescaler
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#define LCD_LL_CLOCK_PRESCALE_MAX (64)
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#define LCD_LL_CLK_FRAC_DIV_N_MAX 256 // LCD_CLK = LCD_CLK_S / (N + b/a), the N register is 8 bit-width
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#define LCD_LL_CLK_FRAC_DIV_AB_MAX 64 // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width
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#define LCD_LL_PCLK_DIV_MAX 64 // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width
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/**
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* @brief Enable clock gating
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@ -38,25 +39,13 @@ static inline void lcd_ll_enable_clock(lcd_cam_dev_t *dev, bool en)
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}
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/**
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* @brief Set clock source for LCD peripheral
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* @brief Select clock source for LCD peripheral
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*
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* @param dev LCD register base address
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* @param src Clock source
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* @param div_num Integer part of the divider
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* @param div_a denominator of the divider
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* @param div_b numerator of the divider
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*/
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static inline void lcd_ll_set_group_clock_src(lcd_cam_dev_t *dev, lcd_clock_source_t src, int div_num, int div_a, int div_b)
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static inline void lcd_ll_select_clk_src(lcd_cam_dev_t *dev, lcd_clock_source_t src)
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{
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// lcd_clk = module_clock_src / (div_num + div_b / div_a)
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HAL_ASSERT(div_num >= 2 && div_num <= 256);
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// dic_num == 0 means 256 divider in hardware
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if (div_num >= 256) {
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div_num = 0;
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lcd_clock, lcd_clkm_div_num, div_num);
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dev->lcd_clock.lcd_clkm_div_a = div_a;
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dev->lcd_clock.lcd_clkm_div_b = div_b;
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switch (src) {
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case LCD_CLK_SRC_PLL160M:
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dev->lcd_clock.lcd_clk_sel = 3;
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@ -68,13 +57,34 @@ static inline void lcd_ll_set_group_clock_src(lcd_cam_dev_t *dev, lcd_clock_sour
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dev->lcd_clock.lcd_clk_sel = 1;
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break;
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default:
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// disble LCD clock source
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// disable LCD clock source
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dev->lcd_clock.lcd_clk_sel = 0;
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HAL_ASSERT(false && "unsupported clock source");
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HAL_ASSERT(false);
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break;
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}
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}
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/**
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* @brief Set clock coefficient of LCD peripheral
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*
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* @param dev LCD register base address
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* @param div_num Integer part of the divider
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* @param div_a denominator of the divider
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* @param div_b numerator of the divider
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*/
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static inline void lcd_ll_set_group_clock_coeff(lcd_cam_dev_t *dev, int div_num, int div_a, int div_b)
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{
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// lcd_clk = module_clock_src / (div_num + div_b / div_a)
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HAL_ASSERT(div_num >= 2 && div_num <= LCD_LL_CLK_FRAC_DIV_N_MAX);
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// dic_num == 0 means LCD_LL_CLK_FRAC_DIV_N_MAX divider in hardware
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if (div_num >= LCD_LL_CLK_FRAC_DIV_N_MAX) {
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div_num = 0;
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lcd_clock, lcd_clkm_div_num, div_num);
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dev->lcd_clock.lcd_clkm_div_a = div_a;
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dev->lcd_clock.lcd_clkm_div_b = div_b;
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}
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/**
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* @brief Set the PCLK clock level state when there's no transaction undergoing
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@ -109,6 +119,7 @@ static inline void lcd_ll_set_pixel_clock_edge(lcd_cam_dev_t *dev, bool active_o
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__attribute__((always_inline))
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static inline void lcd_ll_set_pixel_clock_prescale(lcd_cam_dev_t *dev, uint32_t prescale)
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{
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HAL_ASSERT(prescale <= LCD_LL_PCLK_DIV_MAX);
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// Formula: pixel_clk = lcd_clk / (1 + clkcnt_n)
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// clkcnt_n can't be zero
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uint32_t scale = 1;
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@ -1,23 +1,48 @@
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief LCD peripheral SOC layer handle
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*/
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typedef struct lcd_cam_dev_t *lcd_soc_handle_t;
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/**
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* @brief LCD HAL layer context
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*/
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typedef struct {
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lcd_soc_handle_t dev;
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lcd_soc_handle_t dev; // SOC layer handle
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} lcd_hal_context_t;
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/**
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* @brief LCD HAL layer initialization
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*
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* @param hal LCD HAL layer context
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* @param id LCD peripheral ID
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*/
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void lcd_hal_init(lcd_hal_context_t *hal, int id);
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/**
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* @brief LCD PCLK clock calculation
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* @note Currently this function is only used by RGB LCD driver, I80 driver still uses a fixed clock division
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*
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* @param hal LCD HAL layer context
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* @param src_freq_hz LCD source clock frequency in Hz
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* @param expect_pclk_freq_hz Expected LCD PCLK frequency in Hz
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* @return Actual LCD PCLK frequency in Hz
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*/
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uint32_t lcd_hal_cal_pclk_freq(lcd_hal_context_t *hal, uint32_t src_freq_hz, uint32_t expect_pclk_freq_hz);
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#ifdef __cplusplus
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}
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#endif
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@ -1,13 +1,65 @@
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/lcd_hal.h"
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#include "hal/lcd_ll.h"
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#include "hal/log.h"
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void lcd_hal_init(lcd_hal_context_t *hal, int id)
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{
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hal->dev = LCD_LL_GET_HW(id);
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}
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/**
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* @brief helper function, calculate the Greatest Common Divisor
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* @note gcd(a, b) = gcd(b, a % b)
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* @param a bigger value
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* @param b smaller value
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* @return result of gcd(a, b)
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*/
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static inline uint32_t _gcd(uint32_t a, uint32_t b)
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{
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uint32_t c = a % b;
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while (c != 0) {
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a = b;
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b = c;
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c = a % b;
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}
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return b;
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}
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uint32_t lcd_hal_cal_pclk_freq(lcd_hal_context_t *hal, uint32_t src_freq_hz, uint32_t expect_pclk_freq_hz)
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{
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// lcd_clk = module_clock_src / (n + b / a)
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// pixel_clk = lcd_clk / mo
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uint32_t mo = src_freq_hz / expect_pclk_freq_hz / LCD_LL_CLK_FRAC_DIV_N_MAX + 1;
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uint32_t n = src_freq_hz / expect_pclk_freq_hz / mo;
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uint32_t a = 0;
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uint32_t b = 0;
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// delta_hz / expect_pclk_freq_hz <==> b / a
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uint32_t delta_hz = src_freq_hz - expect_pclk_freq_hz * mo * n;
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// fractional divider
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if (delta_hz) {
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uint32_t gcd = _gcd(expect_pclk_freq_hz, delta_hz);
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a = expect_pclk_freq_hz / gcd;
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b = delta_hz / gcd;
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// normalize div_a and div_b
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uint32_t d = a / LCD_LL_CLK_FRAC_DIV_AB_MAX + 1;
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a /= d;
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b /= d;
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}
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HAL_LOGD("lcd_hal", "n=%d,a=%d,b=%d,mo=%d", n, a, b, mo);
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lcd_ll_set_group_clock_coeff(hal->dev, n, a, b);
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lcd_ll_set_pixel_clock_prescale(hal->dev, mo);
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if (delta_hz) {
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return ((uint64_t)src_freq_hz * a) / (n * a + b) / mo;
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} else {
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return src_freq_hz / n / mo;
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}
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}
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