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fix(soc): fix wrong freq definition for 26Mhz version esp32c2 soc

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This commit is contained in:
wuzhenghui 2023-07-15 01:54:48 +08:00
parent 2b600df4ee
commit 842ff10777
2 changed files with 4 additions and 2 deletions
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2
components/soc/CMakeLists.txt
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@ -131,6 +131,8 @@ idf_component_register(SRCS ${srcs}
# Replace this value in an adaptive way, if Kconfig isn't available on your platform
target_compile_definitions(${COMPONENT_LIB} INTERFACE SOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE)
target_compile_definitions(${COMPONENT_LIB} INTERFACE SOC_XTAL_FREQ_MHZ=CONFIG_XTAL_FREQ)
if(target STREQUAL "esp32")
# esp_dport_access_reg_read is added as an undefined symbol because otherwise
# the linker can ignore dport_access.c as it would no other files depending on any symbols in it.

4
components/soc/esp32c2/include/soc/soc.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -145,7 +145,7 @@
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 40*1000000 )
#define APB_CLK_FREQ (SOC_XTAL_FREQ_MHZ * 1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
#define REF_CLK_FREQ ( 1000000 )
#define UART_CLK_FREQ APB_CLK_FREQ