Merge branch 'feature/update_efuses_for_esp32s2' into 'master'

efuse(esp32s2): Added flash_ver, psram_ver, pkg_ver efuses

Closes IDF-3263

See merge request espressif/esp-idf!13644
This commit is contained in:
Mahavir Jain 2021-08-06 14:24:20 +00:00
commit 83956ebbae
5 changed files with 55 additions and 37 deletions

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@ -19,5 +19,5 @@ uint8_t bootloader_common_get_chip_revision(void)
uint32_t bootloader_common_get_chip_ver_pkg(void)
{
// should return the same value as esp_efuse_get_pkg_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_4_REG, EFUSE_PKG_VERSION);
}

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@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 2590bb432c70411ba365bce92ac37032
// md5_digest_table 614c862c2cfa8ccda3a79183ce767255
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -388,16 +388,20 @@ static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK1, 114, 3}, // WAFER version 0:A,
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 117, 4}, // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32,
static const esp_efuse_desc_t FLASH_VERSION[] = {
{EFUSE_BLK1, 117, 4}, // Flash_version,
};
static const esp_efuse_desc_t BLOCK1_VERSION[] = {
{EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version 0:No calibration 1:With calibration,
{EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version,
};
static const esp_efuse_desc_t SYS_DATA_PART0[] = {
{EFUSE_BLK1, 126, 66}, // System configuration,
static const esp_efuse_desc_t PSRAM_VERSION[] = {
{EFUSE_BLK1, 124, 4}, // PSRAM version,
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 128, 4}, // Package version,
};
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
@ -405,7 +409,7 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
};
static const esp_efuse_desc_t BLOCK2_VERSION[] = {
{EFUSE_BLK2, 132, 3}, // Version of BLOCK2,
{EFUSE_BLK2, 132, 3}, // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2,
};
static const esp_efuse_desc_t USER_DATA[] = {
@ -913,18 +917,23 @@ const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
&PKG_VERSION[0], // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32
const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[] = {
&FLASH_VERSION[0], // Flash_version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
&BLOCK1_VERSION[0], // BLOCK1 efuse version 0:No calibration 1:With calibration
&BLOCK1_VERSION[0], // BLOCK1 efuse version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[] = {
&SYS_DATA_PART0[0], // System configuration
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[] = {
&PSRAM_VERSION[0], // PSRAM version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
&PKG_VERSION[0], // Package version
NULL
};
@ -934,7 +943,7 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
&BLOCK2_VERSION[0], // Version of BLOCK2
&BLOCK2_VERSION[0], // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
NULL
};

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@ -124,14 +124,16 @@
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A
PKG_VERSION, EFUSE_BLK1, 117, 4, Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32
BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version 0:No calibration 1:With calibration
SYS_DATA_PART0, EFUSE_BLK1, 126, 66, System configuration
FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version
BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version
PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version
PKG_VERSION, EFUSE_BLK1, 128, 4, Package version
# SYS_DATA_PART0, EFUSE_BLK1, 132, 60, System configuration (Reserve)
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2
BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
################
USER_DATA, EFUSE_BLK3, 0, 256, User data

Can't render this file because it contains an unexpected character in line 7 and column 87.

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@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 2590bb432c70411ba365bce92ac37032
// md5_digest_table 614c862c2cfa8ccda3a79183ce767255
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -108,9 +108,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];

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@ -917,18 +917,18 @@ extern "C" {
#define EFUSE_SPI_PAD_CONF_1_S 0
#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050)
/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:25] ;default: 7'h0 ; */
/*description: Stores the fist 7 bits of the zeroth part of system data.*/
#define EFUSE_SYS_DATA_PART0_0 0x0000007F
#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
#define EFUSE_SYS_DATA_PART0_0_V 0x7F
#define EFUSE_SYS_DATA_PART0_0_S 25
/* EFUSE_PKG_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */
/*description: Package version 0:ESP32-S2, 1:ESP32-S2FH16, 2:ESP32-S2FH32 */
#define EFUSE_PKG_VERSION 0x0000000F
#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
#define EFUSE_PKG_VERSION_V 0xF
#define EFUSE_PKG_VERSION_S 21
/* EFUSE_PSRAM_VERSION : RO ;bitpos:[31:28] ;default: 4'h0 ; */
/*description: PSRAM version */
#define EFUSE_PSRAM_VERSION 0x0000000F
#define EFUSE_PSRAM_VERSION_M ((EFUSE_PSRAM_VERSION_V)<<(EFUSE_PSRAM_VERSION_S))
#define EFUSE_PSRAM_VERSION_V 0xF
#define EFUSE_PSRAM_VERSION_S 28
/* EFUSE_FLASH_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */
/*description: Flash version */
#define EFUSE_FLASH_VERSION 0x0000000F
#define EFUSE_FLASH_VERSION_M ((EFUSE_FLASH_VERSION_V)<<(EFUSE_FLASH_VERSION_S))
#define EFUSE_FLASH_VERSION_V 0xF
#define EFUSE_FLASH_VERSION_S 21
/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */
/*description: WAFER version 0:A */
#define EFUSE_WAFER_VERSION 0x00000007
@ -943,12 +943,18 @@ extern "C" {
#define EFUSE_SPI_PAD_CONF_2_S 0
#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054)
/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:4] ;default: 28'h0 ; */
/*description: Stores the fist 32 bits of the zeroth part of system data.*/
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF
#define EFUSE_SYS_DATA_PART0_1 0x0FFFFFFF
#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF
#define EFUSE_SYS_DATA_PART0_1_S 0
#define EFUSE_SYS_DATA_PART0_1_V 0x0FFFFFFF
#define EFUSE_SYS_DATA_PART0_1_S 4
/* EFUSE_PKG_VERSION : RO ;bitpos:[3:0] ;default: 4'h0 ; */
/*description: Package version */
#define EFUSE_PKG_VERSION 0x0000000F
#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
#define EFUSE_PKG_VERSION_V 0xF
#define EFUSE_PKG_VERSION_S 0
#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058)
/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */