From 8337f0afa2e87c8f33132836919628feb25399ed Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Sat, 10 Oct 2020 15:53:44 +0800 Subject: [PATCH] spi_flash: fix LL of esp32s3 and add 32-bit support --- .../hal/esp32s3/include/hal/gpspi_flash_ll.h | 44 ++++++++++++++----- .../hal/esp32s3/include/hal/spi_flash_ll.h | 9 ++-- .../hal/esp32s3/include/hal/spimem_flash_ll.h | 25 +++++++++-- components/hal/spi_flash_hal_common.inc | 1 + components/soc/esp32s3/include/soc/spi_caps.h | 3 +- 5 files changed, 65 insertions(+), 17 deletions(-) diff --git a/components/hal/esp32s3/include/hal/gpspi_flash_ll.h b/components/hal/esp32s3/include/hal/gpspi_flash_ll.h index 3b4b70ecb3..67030b4de6 100644 --- a/components/hal/esp32s3/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32s3/include/hal/gpspi_flash_ll.h @@ -57,7 +57,7 @@ typedef typeof(GPSPI2.clock) gpspi_flash_ll_clock_reg_t; * Control *----------------------------------------------------------------------------*/ /** - * Reset peripheral registers before configuration and starting control + * Reset peripheral registers before configuration and starting control. * * @param dev Beginning address of the peripheral registers. */ @@ -65,6 +65,15 @@ static inline void gpspi_flash_ll_reset(spi_dev_t *dev) { dev->user.val = 0; dev->ctrl.val = 0; + + dev->clk_gate.clk_en = 1; + dev->clk_gate.mst_clk_active = 1; + dev->clk_gate.mst_clk_sel = 1; + + dev->dma_conf.val = 0; + dev->dma_conf.tx_seg_trans_clr_en = 1; + dev->dma_conf.rx_seg_trans_clr_en = 1; + dev->dma_conf.dma_seg_trans_en = 0; } /** @@ -144,6 +153,8 @@ static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *bu */ static inline void gpspi_flash_ll_user_start(spi_dev_t *dev) { + dev->cmd.update = 1; + while (dev->cmd.update); dev->cmd.usr = 1; } @@ -156,7 +167,7 @@ static inline void gpspi_flash_ll_user_start(spi_dev_t *dev) */ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) { - return false; + return dev->cmd.usr == 0; } /** @@ -203,10 +214,10 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M); - // ctrl.val |= SPI_FAST_RD_MODE_M; switch (read_mode) { case SPI_FLASH_FASTRD: //the default option + case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: ctrl.fread_quad = 1; @@ -226,9 +237,6 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod ctrl.fread_dual = 1; user.fwrite_dual = 1; break; - // case SPI_FLASH_SLOWRD: - // ctrl.fast_rd_mode = 0; - // break; default: abort(); } @@ -257,6 +265,9 @@ static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen) { dev->user.usr_miso = bitlen > 0; + if (bitlen) { + dev->ms_dlen.ms_data_bitlen = bitlen - 1; + } } /** @@ -269,20 +280,24 @@ static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen) { dev->user.usr_mosi = bitlen > 0; + if (bitlen) { + dev->ms_dlen.ms_data_bitlen = bitlen - 1; + } } /** - * Set the command with fixed length (8 bits). + * Set the command. * * @param dev Beginning address of the peripheral registers. * @param command Command to send + * @param bitlen Length of the command */ -static inline void gpspi_flash_ll_set_command8(spi_dev_t *dev, uint8_t command) +static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen) { dev->user.usr_command = 1; typeof(dev->user2) user2 = { .usr_command_value = command, - .usr_command_bitlen = (8 - 1), + .usr_command_bitlen = (bitlen - 1), }; dev->user2 = user2; } @@ -318,9 +333,12 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle */ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { - dev->addr = (addr << (32 - bitlen)); + // The blank region should be all ones + uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + dev->addr = (addr << (32 - bitlen)) | padding_ones; } + /** * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write... * @@ -358,6 +376,12 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, dev->ctrl.d_pol = out_lev; } +static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) +{ + dev->user1.cs_hold_time = hold_n - 1; + dev->user.cs_hold = (hold_n > 0? 1: 0); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/spi_flash_ll.h b/components/hal/esp32s3/include/hal/spi_flash_ll.h index 411058da81..1b5c23849c 100644 --- a/components/hal/esp32s3/include/hal/spi_flash_ll.h +++ b/components/hal/esp32s3/include/hal/spi_flash_ll.h @@ -66,13 +66,15 @@ typedef union { #define spi_flash_ll_set_clock(dev, clk) gpspi_flash_ll_set_clock((spi_dev_t*)dev, (gpspi_flash_ll_clock_reg_t*)clk) #define spi_flash_ll_set_miso_bitlen(dev, bitlen) gpspi_flash_ll_set_miso_bitlen((spi_dev_t*)dev, bitlen) #define spi_flash_ll_set_mosi_bitlen(dev, bitlen) gpspi_flash_ll_set_mosi_bitlen((spi_dev_t*)dev, bitlen) -#define spi_flash_ll_set_command8(dev, cmd) gpspi_flash_ll_set_command8((spi_dev_t*)dev, cmd) +#define spi_flash_ll_set_command(dev, cmd, bitlen) gpspi_flash_ll_set_command((spi_dev_t*)dev, cmd, bitlen) #define spi_flash_ll_set_addr_bitlen(dev, bitlen) gpspi_flash_ll_set_addr_bitlen((spi_dev_t*)dev, bitlen) #define spi_flash_ll_get_addr_bitlen(dev) gpspi_flash_ll_get_addr_bitlen((spi_dev_t*)dev) #define spi_flash_ll_set_address(dev, addr) gpspi_flash_ll_set_address((spi_dev_t*)dev, addr) #define spi_flash_ll_set_usr_address(dev, addr, bitlen) gpspi_flash_ll_set_usr_address((spi_dev_t*)dev, addr, bitlen) #define spi_flash_ll_set_dummy(dev, dummy) gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy) #define spi_flash_ll_set_dummy_out(dev, en, lev) gpspi_flash_ll_set_dummy_out((spi_dev_t*)dev, en, lev) +#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n) + #else #define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev) #define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev) @@ -91,13 +93,14 @@ typedef union { #define spi_flash_ll_set_clock(dev, clk) spimem_flash_ll_set_clock((spi_mem_dev_t*)dev, (spimem_flash_ll_clock_reg_t*)clk) #define spi_flash_ll_set_miso_bitlen(dev, bitlen) spimem_flash_ll_set_miso_bitlen((spi_mem_dev_t*)dev, bitlen) #define spi_flash_ll_set_mosi_bitlen(dev, bitlen) spimem_flash_ll_set_mosi_bitlen((spi_mem_dev_t*)dev, bitlen) -#define spi_flash_ll_set_command8(dev, cmd) spimem_flash_ll_set_command8((spi_mem_dev_t*)dev, cmd) +#define spi_flash_ll_set_command(dev, cmd, bitlen) spimem_flash_ll_set_command((spi_mem_dev_t*)dev, cmd, bitlen) #define spi_flash_ll_set_addr_bitlen(dev, bitlen) spimem_flash_ll_set_addr_bitlen((spi_mem_dev_t*)dev, bitlen) #define spi_flash_ll_get_addr_bitlen(dev) spimem_flash_ll_get_addr_bitlen((spi_mem_dev_t*) dev) #define spi_flash_ll_set_address(dev, addr) spimem_flash_ll_set_address((spi_mem_dev_t*)dev, addr) -#define spi_flash_ll_set_usr_address(dev, addr, bitlen) spimem_flash_ll_set_address((spi_mem_dev_t*)dev, addr) +#define spi_flash_ll_set_usr_address(dev, addr, bitlen) spimem_flash_ll_set_usr_address((spi_mem_dev_t*)dev, addr, bitlen) #define spi_flash_ll_set_dummy(dev, dummy) spimem_flash_ll_set_dummy((spi_mem_dev_t*)dev, dummy) #define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev) +#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) #endif #ifdef __cplusplus diff --git a/components/hal/esp32s3/include/hal/spimem_flash_ll.h b/components/hal/esp32s3/include/hal/spimem_flash_ll.h index e361eaa364..d85c9cc10d 100644 --- a/components/hal/esp32s3/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32s3/include/hal/spimem_flash_ll.h @@ -308,17 +308,18 @@ static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t } /** - * Set the command with fixed length (8 bits). + * Set the command. * * @param dev Beginning address of the peripheral registers. * @param command Command to send + * @param bitlen Length of the command */ -static inline void spimem_flash_ll_set_command8(spi_mem_dev_t *dev, uint8_t command) +static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen) { dev->user.usr_command = 1; typeof(dev->user2) user2 = { .usr_command_value = command, - .usr_command_bitlen = (8 - 1), + .usr_command_bitlen = (bitlen - 1), }; dev->user2 = user2; } @@ -357,6 +358,18 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr dev->addr = addr; } +/** + * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen) +{ + (void)bitlen; + spimem_flash_ll_set_address(dev, addr); +} + /** * Set the length of dummy cycles. * @@ -383,6 +396,12 @@ static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t ou dev->ctrl.d_pol = out_lev; } +static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) +{ + dev->ctrl2.cs_hold_time = hold_n - 1; + dev->user.cs_hold = (hold_n > 0? 1: 0); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/spi_flash_hal_common.inc b/components/hal/spi_flash_hal_common.inc index 3bc1b27d32..db785deebc 100644 --- a/components/hal/spi_flash_hal_common.inc +++ b/components/hal/spi_flash_hal_common.inc @@ -44,6 +44,7 @@ esp_err_t spi_flash_hal_device_config(spi_flash_host_inst_t *host) { spi_flash_hal_context_t* ctx = (spi_flash_hal_context_t*)host; spi_dev_t *dev = get_spi_dev(host); + spi_flash_ll_reset(dev); spi_flash_ll_set_cs_pin(dev, ctx->cs_num); spi_flash_ll_set_clock(dev, &ctx->clock_conf); diff --git a/components/soc/esp32s3/include/soc/spi_caps.h b/components/soc/esp32s3/include/soc/spi_caps.h index b18538e6e6..d95a6217ec 100644 --- a/components/soc/esp32s3/include/soc/spi_caps.h +++ b/components/soc/esp32s3/include/soc/spi_caps.h @@ -27,7 +27,8 @@ #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 // Peripheral supports DIO, DOUT, QIO, or QOUT -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3)) +// VSPI (SPI3) only support 1-bit mode +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2) // Peripheral supports output given level during its "dummy phase" #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1