alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Merge branch 'bugfix/esp32s2_wakeup_from_light_sleep_fix' into 'master'

Browse Source 
esp32s2 light sleep fix

Closes IDFCI-122

See merge request espressif/esp-idf!10269
This commit is contained in:
Angus Gratton 2021-02-11 07:34:57 +08:00
commit 807c8549e1
3 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -35,6 +35,7 @@
#include "driver/periph_ctrl.h" #include "driver/periph_ctrl.h"
#include "bootloader_clock.h" #include "bootloader_clock.h"
#include "soc/syscon_reg.h" #include "soc/syscon_reg.h"
#include "hal/clk_gate_ll.h"
static const char *TAG = "clk"; static const char *TAG = "clk";
@ -313,6 +314,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M); DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW); DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
periph_ll_reset(PERIPH_SYSTIMER_MODULE);
/* Enable RNG clock. */ /* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE); periph_module_enable(PERIPH_RNG_MODULE);
} }

2
components/esp_system/test/test_sleep.c
View File

@ -69,6 +69,7 @@ TEST_CASE("light sleep followed by deep sleep", "[deepsleep][reset=DEEPSLEEP_RES
esp_light_sleep_start(); esp_light_sleep_start();
esp_deep_sleep_start(); esp_deep_sleep_start();
} }
#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
TEST_CASE("wake up from light sleep using timer", "[deepsleep]") TEST_CASE("wake up from light sleep using timer", "[deepsleep]")
{ {
@ -81,7 +82,6 @@ TEST_CASE("wake up from light sleep using timer", "[deepsleep]")
(tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f; (tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f;
TEST_ASSERT_INT32_WITHIN(500, 2000, (int) dt); TEST_ASSERT_INT32_WITHIN(500, 2000, (int) dt);
} }
#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
static void test_light_sleep(void* arg) static void test_light_sleep(void* arg)
{ {

2
components/newlib/port/esp_time_impl.c
View File

@ -50,7 +50,7 @@
// Offset between FRC timer and the RTC. // Offset between FRC timer and the RTC.
// Initialized after reset or light sleep. // Initialized after reset or light sleep.
#if defined(CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER) && defined(CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER) #if defined(CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER) && defined(CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER)
uint64_t s_microseconds_offset; uint64_t s_microseconds_offset = 0;
#endif #endif
#ifndef CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER #ifndef CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER