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synced 2024-09-20 20:56:01 -04:00
bootloader: fix analog reset on C6 and H2
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aeabe8d742
commit
80315b77a0
@ -103,33 +103,10 @@ static inline void bootloader_hardware_init(void)
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static inline void bootloader_ana_reset_config(void)
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{
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// TODO: IDF-5990 copied from C3, need update
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// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
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/*
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For origin chip & ECO1: only support swt reset;
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For ECO2: fix brownout reset bug, support swt & brownout reset;
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For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
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*/
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uint8_t chip_version = efuse_hal_get_minor_chip_version();
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switch (chip_version) {
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case 0:
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case 1:
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//Disable BOR and GLITCH reset
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bootloader_ana_bod_reset_config(false);
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bootloader_ana_clock_glitch_reset_config(false);
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break;
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case 2:
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//Enable BOR reset. Disable GLITCH reset
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bootloader_ana_bod_reset_config(true);
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bootloader_ana_clock_glitch_reset_config(false);
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break;
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case 3:
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default:
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//Enable BOR, and GLITCH reset
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bootloader_ana_bod_reset_config(true);
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bootloader_ana_clock_glitch_reset_config(true);
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break;
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}
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//Enable super WDT reset.
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bootloader_ana_super_wdt_reset_config(true);
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//Enable BOD reset
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bootloader_ana_bod_reset_config(true);
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}
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esp_err_t bootloader_init(void)
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@ -1,15 +1,24 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <assert.h>
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#include "soc/soc.h"
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#include "soc/lp_analog_peri_reg.h"
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void bootloader_ana_super_wdt_reset_config(bool enable)
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{
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//C6 doesn't support bypass super WDT reset
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assert(enable);
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
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}
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void bootloader_ana_bod_reset_config(bool enable)
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{
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
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if (enable) {
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REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
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} else {
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@ -17,12 +26,8 @@ void bootloader_ana_bod_reset_config(bool enable)
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}
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}
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//Not supported but common bootloader calls the function. Do nothing
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void bootloader_ana_clock_glitch_reset_config(bool enable)
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{
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
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if (enable) {
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REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
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} else {
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
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}
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(void)enable;
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}
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@ -93,33 +93,10 @@ static inline void bootloader_hardware_init(void)
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static inline void bootloader_ana_reset_config(void)
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{
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// TODO: IDF-5990 copied from C6, need update
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// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
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/*
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For origin chip & ECO1: only support swt reset;
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For ECO2: fix brownout reset bug, support swt & brownout reset;
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For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
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*/
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uint8_t chip_version = efuse_hal_get_minor_chip_version();
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switch (chip_version) {
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case 0:
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case 1:
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//Disable BOR and GLITCH reset
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bootloader_ana_bod_reset_config(false);
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bootloader_ana_clock_glitch_reset_config(false);
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break;
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case 2:
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//Enable BOR reset. Disable GLITCH reset
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bootloader_ana_bod_reset_config(true);
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bootloader_ana_clock_glitch_reset_config(false);
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break;
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case 3:
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default:
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//Enable BOR, and GLITCH reset
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bootloader_ana_bod_reset_config(true);
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bootloader_ana_clock_glitch_reset_config(true);
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break;
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}
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//Enable super WDT reset.
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bootloader_ana_super_wdt_reset_config(true);
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//Enable BOD reset
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bootloader_ana_bod_reset_config(true);
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}
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esp_err_t bootloader_init(void)
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@ -1,20 +1,22 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include "soc/soc.h"
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#include "soc/lp_analog_peri_reg.h"
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void bootloader_ana_super_wdt_reset_config(bool enable)
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{
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// ESP32H2 has removed the super wdt
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//H2 doesn't support bypass super WDT reset
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assert(enable);
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
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}
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void bootloader_ana_bod_reset_config(bool enable)
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{
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
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if (enable) {
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REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
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} else {
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@ -22,12 +24,8 @@ void bootloader_ana_bod_reset_config(bool enable)
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}
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}
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//Not supported but common bootloader calls the function. Do nothing
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void bootloader_ana_clock_glitch_reset_config(bool enable)
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{
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
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if (enable) {
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REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
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} else {
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REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
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}
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(void)enable;
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}
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@ -85,7 +85,7 @@ static inline void bootloader_hardware_init(void)
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static inline void bootloader_ana_reset_config(void)
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{
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//Enable WDT, BOR, and GLITCH reset
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//Enable WDT, BOD, and GLITCH reset
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bootloader_ana_super_wdt_reset_config(true);
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bootloader_ana_bod_reset_config(true);
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bootloader_ana_clock_glitch_reset_config(true);
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@ -20,7 +20,7 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
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void bootloader_ana_bod_reset_config(bool enable)
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{
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REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
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REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
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if (enable) {
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REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
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@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -109,7 +109,7 @@ extern "C" {
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#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0
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#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
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#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1)
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#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
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#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
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/** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register
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@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -234,7 +234,7 @@ extern "C" {
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#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0
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#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
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#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1)
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#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
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#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
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/** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register
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@ -2727,7 +2727,7 @@ extern "C" {
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#define RTC_CNTL_FIB_SEL_S 0
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#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
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#define RTC_CNTL_FIB_BOR_RST BIT(1)
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#define RTC_CNTL_FIB_BOD_RST BIT(1)
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#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
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#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x013C)
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@ -3475,7 +3475,7 @@ extern "C" {
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#define RTC_CNTL_FIB_SEL_S 0
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#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
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#define RTC_CNTL_FIB_BOR_RST BIT(1)
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#define RTC_CNTL_FIB_BOD_RST BIT(1)
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#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
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/** RTC_CNTL_GPIO_WAKEUP_REG register
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