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bootloader: fix analog reset on C6 and H2

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This commit is contained in:
Michael (XIAO Xufeng) 2023-03-06 11:46:19 +08:00 committed by Xiao Xufeng
parent aeabe8d742
commit 80315b77a0
10 changed files with 37 additions and 80 deletions
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31
components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
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@ -103,33 +103,10 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void) static inline void bootloader_ana_reset_config(void)
{ {
// TODO: IDF-5990 copied from C3, need update //Enable super WDT reset.
// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back bootloader_ana_super_wdt_reset_config(true);
/* //Enable BOD reset
For origin chip & ECO1: only support swt reset; bootloader_ana_bod_reset_config(true);
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
*/
uint8_t chip_version = efuse_hal_get_minor_chip_version();
switch (chip_version) {
case 0:
case 1:
//Disable BOR and GLITCH reset
bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 2:
//Enable BOR reset. Disable GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 3:
default:
//Enable BOR, and GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);
break;
}
} }
esp_err_t bootloader_init(void) esp_err_t bootloader_init(void)

21
components/bootloader_support/src/esp32c6/bootloader_soc.c
View File

@ -1,15 +1,24 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include <stdbool.h> #include <stdbool.h>
#include <assert.h>
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h" #include "soc/lp_analog_peri_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
//C6 doesn't support bypass super WDT reset
assert(enable);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
}
void bootloader_ana_bod_reset_config(bool enable) void bootloader_ana_bod_reset_config(bool enable)
{ {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST); REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
if (enable) { if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA); REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
} else { } else {
@ -17,12 +26,8 @@ void bootloader_ana_bod_reset_config(bool enable)
} }
} }
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable) void bootloader_ana_clock_glitch_reset_config(bool enable)
{ {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST); (void)enable;
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
} else {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
}
} }

31
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
View File

@ -93,33 +93,10 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void) static inline void bootloader_ana_reset_config(void)
{ {
// TODO: IDF-5990 copied from C6, need update //Enable super WDT reset.
// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back bootloader_ana_super_wdt_reset_config(true);
/* //Enable BOD reset
For origin chip & ECO1: only support swt reset; bootloader_ana_bod_reset_config(true);
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
*/
uint8_t chip_version = efuse_hal_get_minor_chip_version();
switch (chip_version) {
case 0:
case 1:
//Disable BOR and GLITCH reset
bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 2:
//Enable BOR reset. Disable GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 3:
default:
//Enable BOR, and GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);
break;
}
} }
esp_err_t bootloader_init(void) esp_err_t bootloader_init(void)

18
components/bootloader_support/src/esp32h2/bootloader_soc.c
View File

@ -1,20 +1,22 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include <stdbool.h> #include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h" #include "soc/lp_analog_peri_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable) void bootloader_ana_super_wdt_reset_config(bool enable)
{ {
// ESP32H2 has removed the super wdt //H2 doesn't support bypass super WDT reset
assert(enable);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
} }
void bootloader_ana_bod_reset_config(bool enable) void bootloader_ana_bod_reset_config(bool enable)
{ {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST); REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
if (enable) { if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA); REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
} else { } else {
@ -22,12 +24,8 @@ void bootloader_ana_bod_reset_config(bool enable)
} }
} }
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable) void bootloader_ana_clock_glitch_reset_config(bool enable)
{ {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST); (void)enable;
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
} else {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
}
} }

2
components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
View File

@ -85,7 +85,7 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void) static inline void bootloader_ana_reset_config(void)
{ {
//Enable WDT, BOR, and GLITCH reset //Enable WDT, BOD, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true); bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true); bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true); bootloader_ana_clock_glitch_reset_config(true);

2
components/bootloader_support/src/esp32h4/bootloader_soc.c
View File

@ -20,7 +20,7 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
void bootloader_ana_bod_reset_config(bool enable) void bootloader_ana_bod_reset_config(bool enable)
{ {
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) { if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

4
components/soc/esp32c6/include/soc/lp_analog_peri_reg.h
View File

@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -109,7 +109,7 @@ extern "C" {
#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0 #define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0
#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0) #define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1) #define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2) #define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
/** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register /** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register

4
components/soc/esp32h2/include/soc/lp_analog_peri_reg.h
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@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -234,7 +234,7 @@ extern "C" {
#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0 #define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0
#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0) #define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1) #define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2) #define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
/** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register /** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register

2
components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h
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@ -2727,7 +2727,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0) #define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1) #define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x013C) #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x013C)

2
components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h
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@ -3475,7 +3475,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0) #define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1) #define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
/** RTC_CNTL_GPIO_WAKEUP_REG register /** RTC_CNTL_GPIO_WAKEUP_REG register