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Merge branch 'bugfix/return_error_when_fail_detect_oct_psram_v4.4' into 'release/v4.4'
esp_psram: return error when fail to detect oct psram (v4.4) See merge request espressif/esp-idf!22613
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@ -39,6 +39,7 @@
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#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
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#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
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#define OCT_PSRAM_CS1_IO SPI_CS1_GPIO_NUM
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#define OCT_PSRAM_VENDOR_ID 0xD
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#define OCT_PSRAM_CS_SETUP_TIME 3
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#define OCT_PSRAM_CS_HOLD_TIME 3
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@ -255,6 +256,10 @@ esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode)
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s_init_psram_mode_reg(1, &mode_reg);
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//Print PSRAM info
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s_get_psram_mode_reg(1, &mode_reg);
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if (mode_reg.mr1.vendor_id != OCT_PSRAM_VENDOR_ID) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", mode_reg.mr1.vendor_id);
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return ESP_ERR_NOT_SUPPORTED;
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}
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s_print_psram_info(&mode_reg);
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s_psram_size = mode_reg.mr2.density == 0x1 ? PSRAM_SIZE_32MBITS :
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mode_reg.mr2.density == 0X3 ? PSRAM_SIZE_64MBITS :
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@ -361,8 +361,8 @@ esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode)
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*/
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psram_read_id(SPI1_NUM, &s_psram_id);
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if (!PSRAM_IS_VALID(s_psram_id)) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
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return ESP_FAIL;
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)s_psram_id);
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return ESP_ERR_NOT_SUPPORTED;
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}
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}
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@ -55,7 +55,10 @@ psram_size_t psram_get_size(void);
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*
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* @param mode SPI mode to access psram in
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* @param vaddrmode Mode the psram cache works in.
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* @return ESP_OK on success, ESP_ERR_INVALID_STATE when VSPI peripheral is needed but cannot be claimed.
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* @return
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* - ESP_OK: on success
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* - ESP_ERR_NOT_SUPPORTED: PSRAM ID / vendor ID check fail
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* - ESP_ERR_INVALID_STATE when VSPI peripheral is needed but cannot be claimed.
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*/
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esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode);
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