From 65820c07ac30245aa30b3f96cc667e575e54d55b Mon Sep 17 00:00:00 2001 From: gaoxu Date: Sat, 13 Jul 2024 14:03:23 +0800 Subject: [PATCH 1/2] feat(adc): support ADC oneshot and continuous mode on ESP32C5 and enable test --- .../test_apps/legacy_adc_driver/README.md | 4 +- .../legacy_adc_driver/main/test_legacy_adc.c | 7 + .../legacy_adc_driver/pytest_legacy_adc.py | 2 +- components/esp_adc/adc_oneshot.c | 4 +- components/esp_adc/test_apps/adc/README.md | 4 +- .../test_apps/adc/main/test_common_adc.h | 9 + .../esp_adc/test_apps/adc/pytest_adc.py | 2 + .../port/esp32c5/sar_periph_ctrl.c | 2 - components/hal/esp32c5/include/hal/adc_ll.h | 784 ++++++++++++++++++ components/hal/include/hal/adc_types.h | 2 +- .../include/esp32c5/idf_performance_target.h | 8 + components/soc/esp32c5/adc_periph.c | 20 + .../esp32c5/include/soc/Kconfig.soc_caps.in | 78 +- .../soc/esp32c5/include/soc/adc_channel.h | 28 +- .../soc/esp32c5/include/soc/clk_tree_defs.h | 2 +- .../soc/esp32c5/include/soc/regi2c_saradc.h | 55 ++ components/soc/esp32c5/include/soc/soc_caps.h | 46 +- docs/docs_not_updated/esp32c5.txt | 2 - .../peripherals/adc_continuous.rst | 2 +- .../api-reference/peripherals/adc_oneshot.rst | 2 +- .../peripherals/adc_continuous.rst | 2 +- .../api-reference/peripherals/adc_oneshot.rst | 2 +- .../peripherals/adc/continuous_read/README.md | 4 +- .../continuous_read/pytest_adc_continuous.py | 2 +- .../peripherals/adc/oneshot_read/README.md | 4 +- .../adc/oneshot_read/pytest_adc_oneshot.py | 1 + 26 files changed, 1016 insertions(+), 62 deletions(-) create mode 100644 components/hal/esp32c5/include/hal/adc_ll.h create mode 100644 components/soc/esp32c5/adc_periph.c create mode 100644 components/soc/esp32c5/include/soc/regi2c_saradc.h diff --git a/components/driver/test_apps/legacy_adc_driver/README.md b/components/driver/test_apps/legacy_adc_driver/README.md index bf47d80ec6..3a502b1f86 100644 --- a/components/driver/test_apps/legacy_adc_driver/README.md +++ b/components/driver/test_apps/legacy_adc_driver/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c index e09a741b18..7a22fa26dc 100644 --- a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c +++ b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c @@ -74,6 +74,13 @@ #define ADC_TEST_HIGH_VAL 4095 #define ADC_TEST_HIGH_THRESH 200 +#elif CONFIG_IDF_TARGET_ESP32C5 +#define ADC_TEST_LOW_VAL 2195 +#define ADC_TEST_LOW_THRESH 200 + +#define ADC_TEST_HIGH_VAL 4095 +#define ADC_TEST_HIGH_THRESH 200 + #endif //ADC Channels diff --git a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py index 6bc3b838d6..b311f7b3a8 100644 --- a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py +++ b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 - import pytest from pytest_embedded import Dut @@ -11,6 +10,7 @@ from pytest_embedded import Dut @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 +@pytest.mark.esp32c5 @pytest.mark.adc @pytest.mark.parametrize( 'config', diff --git a/components/esp_adc/adc_oneshot.c b/components/esp_adc/adc_oneshot.c index 0691e22f1a..15166a4f99 100644 --- a/components/esp_adc/adc_oneshot.c +++ b/components/esp_adc/adc_oneshot.c @@ -126,7 +126,7 @@ esp_err_t adc_oneshot_new_unit(const adc_oneshot_unit_init_cfg_t *init_config, a if (init_config->ulp_mode == ADC_ULP_MODE_DISABLE) { sar_periph_ctrl_adc_oneshot_power_acquire(); } else { -#if !CONFIG_IDF_TARGET_ESP32P4 // # TODO: IDF-7528, IDF-7529 +#if !CONFIG_IDF_TARGET_ESP32C5// # TODO: IDF-8638, IDF-8640 esp_sleep_enable_adc_tsens_monitor(true); #endif } @@ -229,7 +229,7 @@ esp_err_t adc_oneshot_del_unit(adc_oneshot_unit_handle_t handle) if (ulp_mode == ADC_ULP_MODE_DISABLE) { sar_periph_ctrl_adc_oneshot_power_release(); } else { -#if !CONFIG_IDF_TARGET_ESP32P4 // # TODO: IDF-7528, IDF-7529 +#if !CONFIG_IDF_TARGET_ESP32C5// # TODO: IDF-8638, IDF-8640 esp_sleep_enable_adc_tsens_monitor(false); #endif } diff --git a/components/esp_adc/test_apps/adc/README.md b/components/esp_adc/test_apps/adc/README.md index bf47d80ec6..3a502b1f86 100644 --- a/components/esp_adc/test_apps/adc/README.md +++ b/components/esp_adc/test_apps/adc/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_adc/test_apps/adc/main/test_common_adc.h b/components/esp_adc/test_apps/adc/main/test_common_adc.h index 1d28c66e4e..c2bd4cd198 100644 --- a/components/esp_adc/test_apps/adc/main/test_common_adc.h +++ b/components/esp_adc/test_apps/adc/main/test_common_adc.h @@ -94,6 +94,15 @@ extern "C" { #define ADC_TEST_HIGH_VAL 4095 #define ADC_TEST_HIGH_VAL_DMA 4095 #define ADC_TEST_HIGH_THRESH 200 + +#elif CONFIG_IDF_TARGET_ESP32C5 +#define ADC_TEST_LOW_VAL 2169 +#define ADC_TEST_LOW_THRESH 200 + +#define ADC_TEST_HIGH_VAL 4095 +#define ADC_TEST_HIGH_VAL_DMA 4095 +#define ADC_TEST_HIGH_THRESH 200 + #endif /*--------------------------------------------------------------- diff --git a/components/esp_adc/test_apps/adc/pytest_adc.py b/components/esp_adc/test_apps/adc/pytest_adc.py index 5f61b66e59..780e910d30 100644 --- a/components/esp_adc/test_apps/adc/pytest_adc.py +++ b/components/esp_adc/test_apps/adc/pytest_adc.py @@ -10,6 +10,7 @@ from pytest_embedded import Dut @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 +@pytest.mark.esp32c5 @pytest.mark.adc @pytest.mark.parametrize('config', [ 'iram_safe', @@ -40,6 +41,7 @@ def test_adc_esp32c2_xtal_26mhz(dut: Dut) -> None: @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 +@pytest.mark.esp32c5 @pytest.mark.adc @pytest.mark.parametrize('config', [ 'gdma_iram_safe', diff --git a/components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c index 484b89be1b..c9ccaa662a 100644 --- a/components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c @@ -24,8 +24,6 @@ static const char *TAG = "sar_periph_ctrl"; extern portMUX_TYPE rtc_spinlock; -// TODO: [ESP32C5] IDF-8701, IDF-8703, IDF-8727 - void sar_periph_ctrl_init(void) { sar_ctrl_ll_force_power_ctrl_from_pwdet(true); diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h new file mode 100644 index 0000000000..616ea25e61 --- /dev/null +++ b/components/hal/esp32c5/include/hal/adc_ll.h @@ -0,0 +1,784 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "esp_attr.h" + +#include "soc/adc_periph.h" +#include "soc/apb_saradc_struct.h" +#include "soc/apb_saradc_reg.h" +#include "soc/pmu_reg.h" +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/misc.h" +#include "hal/assert.h" +#include "hal/adc_types.h" +#include "hal/adc_types_private.h" +#include "hal/regi2c_ctrl.h" +#include "hal/sar_ctrl_ll.h" + +#include "soc/regi2c_saradc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31) +#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30) + +#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M | \ + APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M | \ + APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M | \ + APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M) + +#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M) +#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M) + +/*--------------------------------------------------------------- + Oneshot +---------------------------------------------------------------*/ +#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) +#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0) + +/*--------------------------------------------------------------- + DMA +---------------------------------------------------------------*/ +#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) +#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8) +#define ADC_LL_FSM_START_WAIT_DEFAULT (5) +#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100) +#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2) +#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1) +#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15 +#define ADC_LL_CLKM_DIV_B_DEFAULT 1 +#define ADC_LL_CLKM_DIV_A_DEFAULT 0 +#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 + +#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32C5 supported to manage power mode +/*--------------------------------------------------------------- + PWDET (Power Detect) +---------------------------------------------------------------*/ +#define ADC_LL_PWDET_CCT_DEFAULT (4) + +typedef enum { + ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_LL_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_LL_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF, /*!< ADC XPD controlled by SW. power off. */ +} adc_ll_power_t; + +typedef enum { + ADC_LL_CTRL_DIG = 0, ///< ADC digital controller +} adc_ll_controller_t; + +/** + * @brief ADC digital controller (DMA mode) work mode. + * + * @note The conversion mode affects the sampling frequency: + * ESP32C5 only support ONLY_ADC1 mode + * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once. + */ +typedef enum { + ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion +} adc_ll_digi_convert_mode_t; + +typedef struct { + union { + struct { + uint8_t atten: 2; + uint8_t channel: 3; + uint8_t unit: 1; + uint8_t reserved: 2; + }; + uint8_t val; + }; +} __attribute__((packed)) adc_ll_digi_pattern_table_t; + +/*--------------------------------------------------------------- + Digital controller setting +---------------------------------------------------------------*/ + +/** + * Set adc fsm interval parameter for digital controller. These values are fixed for same platforms. + * + * @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor. + * @param start_wait Delay time after open xpd. + * @param standby_wait Delay time to close xpd. + */ +static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait) +{ + // Internal FSM reset wait time + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_rstb_wait, rst_wait); + // Internal FSM start wait time + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_xpd_wait, start_wait); + // Internal FSM standby wait time + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_standby_wait, standby_wait); +} + +/** + * Set adc sample cycle for digital controller. + * + * @note Normally, please use default value. + * @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor. + * Range: 2 ~ 0xFF. + */ +static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) +{ + /* Peripheral reg i2c has powered up in rtc_init, write directly */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); +} + +/** + * Set SAR ADC module clock division factor. + * SAR ADC clock divided from digital controller clock. + * + * @param div Division factor. + */ +static inline void adc_ll_digi_set_clk_div(uint32_t div) +{ + /* ADC clock divided from digital controller clock clk */ + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl, saradc_saradc_sar_clk_div, div); +} + +/** + * Set adc max conversion number for digital controller. + * If the number of ADC conversion is equal to the maximum, the conversion is stopped. + * + * @param meas_num Max conversion number. Range: 0 ~ 255. + */ +static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl2, saradc_saradc_max_meas_num, meas_num); +} + +/** + * Enable max conversion number detection for digital controller. + * If the number of ADC conversion is equal to the maximum, the conversion is stopped. + * + * @param enable true: enable; false: disable + */ +static inline void adc_ll_digi_convert_limit_enable(bool enable) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_meas_num_limit = enable; +} + +/** + * Set adc conversion mode for digital controller. + * + * @note ESP32C5 only support ADC1 single mode. + * + * @param mode Conversion mode select. + */ +static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode) +{ + //ESP32C5 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode +} + +/** + * Set pattern table length for digital controller. + * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection, + * and attenuation are stored. When the conversion is started, the controller reads conversion rules from the + * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. + * + * @param adc_n ADC unit. + * @param patt_len Items range: 1 ~ 8. + */ +static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1; +} + +/** + * Set pattern table for digital controller. + * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection, + * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the + * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. + * + * @param adc_n ADC unit. + * @param pattern_index Items index. Range: 0 ~ 7. + * @param pattern Stored conversion rules. + */ +static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) +{ + uint32_t tab; + uint8_t index = pattern_index / 4; + uint8_t offset = (pattern_index % 4) * 6; + adc_ll_digi_pattern_table_t pattern = {0}; + + pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5); + if (index == 0) { + tab = APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1; // Read old register value + tab &= (~(0xFC0000 >> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = tab; // Write back + } else { + tab = APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2; // Read old register value + tab &= (~(0xFC0000 >> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = tab; // Write back + } +} + +/** + * Reset the pattern table pointer, then take the measurement rule from table header in next measurement. + * + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_p_clear = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_p_clear = 0; +} + +/** + * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize. + * + * @note Only ADC2 have arbiter function. + * @param cycle range: 0 ~ 4. + */ +static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_wait_arb_cycle = cycle; +} + +/** + * ADC Digital controller output data invert or not. + * + * @param adc_n ADC unit. + * @param inv_en data invert or not. + */ +static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en) +{ + if (adc_n == ADC_UNIT_1) { + APB_SARADC.saradc_ctrl2.saradc_saradc_sar1_inv = inv_en; // Enable / Disable ADC data invert + } +} + +/** + * Set the interval clock cycle for the digital controller to trigger the measurement. + * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. + * + * @note The trigger interval should not be smaller than the sampling time of the SAR ADC. + * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095. + */ +static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle; +} + +/** + * Enable digital controller timer to trigger the measurement. + */ +static inline void adc_ll_digi_trigger_enable(void) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1; +} + +/** + * Disable digital controller timer to trigger the measurement. + */ +static inline void adc_ll_digi_trigger_disable(void) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0; +} + +/** + * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock. + * Expression: controller_clk = (APLL or APB) / (div_num + div_a / div_b + 1). + * + * @param div_num Division factor. Range: 0 ~ 255. + * @param div_b Division factor. Range: 1 ~ 63. + * @param div_a Division factor. Range: 0 ~ 63. + */ +static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num); + PCR.saradc_clkm_conf.saradc_clkm_div_b = div_b; + PCR.saradc_clkm_conf.saradc_clkm_div_a = div_a; +} + +/** + * Enable clock and select clock source for ADC digital controller. + * + * @param clk_src clock source for ADC digital controller. + */ +static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) +{ + switch (clk_src) { + case ADC_DIGI_CLK_SRC_XTAL: + PCR.saradc_clkm_conf.saradc_clkm_sel = 0; + break; + case ADC_DIGI_CLK_SRC_RC_FAST: + PCR.saradc_clkm_conf.saradc_clkm_sel = 1; + break; + case ADC_DIGI_CLK_SRC_PLL_F80M: + PCR.saradc_clkm_conf.saradc_clkm_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock"); + } + // Enable ADC_CTRL_CLK (i.e. digital domain clock) + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; +} + +/** + * Disable clock for ADC digital controller. + */ +static inline void adc_ll_digi_controller_clk_disable(void) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; +} + +/** + * Reset adc digital controller filter. + * + * @param idx Filter index + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_filter_reset(adc_digi_iir_filter_t idx, adc_unit_t adc_n) +{ + (void)adc_n; + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_reset = 1; + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_reset = 0; +} + +/** + * Set adc digital controller filter coeff. + * + * @param idx filter index + * @param adc_n adc unit + * @param channel adc channel + * @param coeff filter coeff + */ +static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_unit_t adc_n, adc_channel_t channel, adc_digi_iir_filter_coeff_t coeff) +{ + uint32_t factor_reg_val = 0; + switch (coeff) { + case ADC_DIGI_IIR_FILTER_COEFF_2: + factor_reg_val = 1; + break; + case ADC_DIGI_IIR_FILTER_COEFF_4: + factor_reg_val = 2; + break; + case ADC_DIGI_IIR_FILTER_COEFF_8: + factor_reg_val = 3; + break; + case ADC_DIGI_IIR_FILTER_COEFF_16: + factor_reg_val = 4; + break; + case ADC_DIGI_IIR_FILTER_COEFF_64: + factor_reg_val = 6; + break; + default: + HAL_ASSERT(false); + } + + if (idx == ADC_DIGI_IIR_FILTER_0) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel0 = ((adc_n + 1) << 3) | (channel & 0x7); + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor0 = factor_reg_val; + } else if (idx == ADC_DIGI_IIR_FILTER_1) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel1 = ((adc_n + 1) << 3) | (channel & 0x7); + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor1 = factor_reg_val; + } +} + +/** + * Enable adc digital controller filter. + * Filtering the ADC data to obtain smooth data at higher sampling rates. + * + * @param idx filter index + * @param adc_n ADC unit + * @param enable Enable / Disable + */ +static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit_t adc_n, bool enable) +{ + (void)adc_n; + if (!enable) { + if (idx == ADC_DIGI_IIR_FILTER_0) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel0 = 0xF; + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor0 = 0; + } else if (idx == ADC_DIGI_IIR_FILTER_1) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel1 = 0xF; + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor1 = 0; + } + } + //nothing to do to enable, after adc_ll_digi_filter_set_factor, it's enabled. +} + +/** + * Set monitor threshold of adc digital controller on specific channel. + * + * @param monitor_id ADC digi monitor unit index. + * @param adc_n Which adc unit the channel belong to. + * @param channel Which channel of adc want to be monitored. + * @param h_thresh High threshold of this monitor. + * @param l_thresh Low threshold of this monitor. + */ +static inline void adc_ll_digi_monitor_set_thres(adc_monitor_id_t monitor_id, adc_unit_t adc_n, uint8_t channel, int32_t h_thresh, int32_t l_thresh) +{ + if (monitor_id == ADC_MONITOR_0) { + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_channel = (adc_n << 3) | (channel & 0x7); + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_high = h_thresh; + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_low = l_thresh; + } else { // ADC_MONITOR_1 + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_channel = (adc_n << 3) | (channel & 0x7); + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_high = h_thresh; + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_low = l_thresh; + } +} + +/** + * Start/Stop monitor of adc digital controller. + * + * @param monitor_id ADC digi monitor unit index. + * @param start 1 for start, 0 for stop + */ +static inline void adc_ll_digi_monitor_user_start(adc_monitor_id_t monitor_id, bool start) +{ + if (monitor_id == ADC_MONITOR_0) { + APB_SARADC.saradc_thres_ctrl.saradc_apb_saradc_thres0_en = start; + } else { + APB_SARADC.saradc_thres_ctrl.saradc_apb_saradc_thres1_en = start; + } +} + +/** + * Enable/disable a intr of adc digital monitor. + * + * @param monitor_id ADC digi monitor unit index. + * @param mode monit mode to enable/disable intr. + * @param enable enable or disable. + */ +static inline void adc_ll_digi_monitor_enable_intr(adc_monitor_id_t monitor_id, adc_monitor_mode_t mode, bool enable) +{ + if (monitor_id == ADC_MONITOR_0) { + if (mode == ADC_MONITOR_MODE_HIGH) { + APB_SARADC.saradc_int_ena.saradc_apb_saradc_thres0_high_int_ena = enable; + } else { + APB_SARADC.saradc_int_ena.saradc_apb_saradc_thres0_low_int_ena = enable; + } + } + if (monitor_id == ADC_MONITOR_1) { + if (mode == ADC_MONITOR_MODE_HIGH) { + APB_SARADC.saradc_int_ena.saradc_apb_saradc_thres1_high_int_ena = enable; + } else { + APB_SARADC.saradc_int_ena.saradc_apb_saradc_thres1_low_int_ena = enable; + } + } +} + +/** + * Clear intr raw for adc digi monitors. + */ +__attribute__((always_inline)) +static inline void adc_ll_digi_monitor_clear_intr(void) +{ + APB_SARADC.saradc_int_clr.val |= ADC_LL_THRES_ALL_INTR_ST_M; +} + +/** + * Get the address of digi monitor intr statue register. + * + * @return address of register. + */ +__attribute__((always_inline)) +static inline volatile const void *adc_ll_digi_monitor_get_intr_status_addr(void) +{ + return &APB_SARADC.saradc_int_st.val; +} + +/** + * Set DMA eof num of adc digital controller. + * If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated. + * + * @param num eof num of DMA. + */ +static inline void adc_ll_digi_dma_set_eof_num(uint32_t num) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_dma_conf, saradc_apb_adc_eof_num, num); +} + +/** + * Enable output data to DMA from adc digital controller. + */ +static inline void adc_ll_digi_dma_enable(void) +{ + APB_SARADC.saradc_dma_conf.saradc_apb_adc_trans = 1; +} + +/** + * Disable output data to DMA from adc digital controller. + */ +static inline void adc_ll_digi_dma_disable(void) +{ + APB_SARADC.saradc_dma_conf.saradc_apb_adc_trans = 0; +} + +/** + * Reset adc digital controller. + */ +static inline void adc_ll_digi_reset(void) +{ + APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 1; + APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 0; +} + +/*--------------------------------------------------------------- + PWDET(Power detect) controller setting +---------------------------------------------------------------*/ +/** + * Set adc cct for PWDET controller. + * + * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. + * @param cct Range: 0 ~ 7. + */ +static inline void adc_ll_pwdet_set_cct(uint32_t cct) +{ + (void)cct; +} + +/** + * Get adc cct for PWDET controller. + * + * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. + * @return cct Range: 0 ~ 7. + */ +static inline uint32_t adc_ll_pwdet_get_cct(void) +{ + return 0; +} + +/*--------------------------------------------------------------- + Common setting +---------------------------------------------------------------*/ + +/** + * @brief Enable the ADC APB clock + * @param enable true to enable, false to disable + */ +static inline void adc_ll_enable_bus_clock(bool enable) +{ + PCR.saradc_conf.saradc_reg_clk_en = enable; +} + +/** + * @brief Reset ADC module + */ +static inline void adc_ll_reset_register(void) +{ + PCR.saradc_conf.saradc_reg_rst_en = 1; + PCR.saradc_conf.saradc_reg_rst_en = 0; +} + +/** + * Set ADC module power management. + * + * @param manage Set ADC power status. + */ +static inline void adc_ll_set_power_manage(adc_unit_t adc_n, adc_ll_power_t manage) +{ + (void) adc_n; + /* Bit1 0:Fsm 1: SW mode + Bit0 0:SW mode power down 1: SW mode power on */ + if (manage == ADC_LL_POWER_SW_ON) { + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3; + } else if (manage == ADC_LL_POWER_BY_FSM) { + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0; + } else if (manage == ADC_LL_POWER_SW_OFF) { + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2; + } +} + +__attribute__((always_inline)) +static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl) +{ + //Not used on ESP32C5 +} + +/*--------------------------------------------------------------- + Oneshot Read +---------------------------------------------------------------*/ +/** + * Set adc output data format for oneshot mode + * + * @note ESP32C5 Oneshot mode only supports 12bit. + * @param adc_n ADC unit. + * @param bits Output data bits width option. + */ +static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits) +{ + //ESP32C5 only supports 12bit, leave here for compatibility + HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT); +} + +/** + * Enable adc channel to start convert. + * + * @note Only one channel can be selected for measurement. + * + * @param adc_n ADC unit. + * @param channel ADC channel number for each ADCn. + */ +static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | channel); +} + +/** + * Disable adc channel to start convert. + * + * @note Only one channel can be selected in once measurement. + * + * @param adc_n ADC unit. + */ +static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0xF); +} + +/** + * Start oneshot conversion by software + * + * @param val Usage: set to 1 to start the ADC conversion. The step signal should at least keep 3 ADC digital controller clock cycle, + * otherwise the step signal may not be captured by the ADC digital controller when its frequency is slow. + * This hardware limitation will be removed in future versions. + */ +static inline void adc_oneshot_ll_start(bool val) +{ + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_start = val; +} + +/** + * Clear the event for each ADCn for Oneshot mode + * + * @param event ADC event + */ +static inline void adc_oneshot_ll_clear_event(uint32_t event_mask) +{ + APB_SARADC.saradc_int_clr.val |= event_mask; +} + +/** + * Check the event for each ADCn for Oneshot mode + * + * @param event ADC event + * + * @return + * -true : The conversion process is finish. + * -false : The conversion process is not finish. + */ +static inline bool adc_oneshot_ll_get_event(uint32_t event_mask) +{ + return (APB_SARADC.saradc_int_raw.val & event_mask); +} + +/** + * Get the converted value for each ADCn for controller. + * + * @param adc_n ADC unit. + * @return + * - Converted value. + */ +static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + uint32_t ret_val = 0; + ret_val = APB_SARADC.saradc_sar1data_status.saradc_apb_saradc1_data & 0xfff; + return ret_val; +} + + +/** + * Analyze whether the obtained raw data is correct. + * ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data. + * + * @param adc_n ADC unit. + * @param raw_data ADC raw data input (convert value). + * @return + * - 1: The data is correct to use. + * - 0: The data is invalid. + */ +static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + return true; +} + +/** + * ADC module RTC output data invert or not. + * + * @param adc_n ADC unit. + * @param inv_en data invert or not. + */ +static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + (void)inv_en; + //For compatibility +} + +/** + * Enable oneshot conversion trigger + * + * @param adc_n ADC unit + */ +static inline void adc_oneshot_ll_enable(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1; +} + +/** + * Disable oneshot conversion trigger for all the ADC units + */ +static inline void adc_oneshot_ll_disable_all_unit(void) +{ + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0; + APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0; +} + +/** + * Set attenuation + * + * @note Attenuation is for all channels + * + * @param adc_n ADC unit + * @param channel ADC channel + * @param atten ADC attenuation + */ +static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + (void)channel; + // Attenuation is for all channels, unit and channel are for compatibility + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten = atten; +} + +/** + * Get the attenuation of a particular channel on ADCn. + * + * @param adc_n ADC unit. + * @param channel ADCn channel number. + * @return atten The attenuation option. + */ +__attribute__((always_inline)) +static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + (void)channel; + return (adc_atten_t)APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h index b37689afe8..34445ee3d5 100644 --- a/components/hal/include/hal/adc_types.h +++ b/components/hal/include/hal/adc_types.h @@ -211,7 +211,7 @@ typedef struct { }; } adc_digi_output_data_t; -#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 /** * @brief ADC digital controller (DMA mode) output data format. * Used to analyze the acquired ADC (DMA) data. diff --git a/components/idf_test/include/esp32c5/idf_performance_target.h b/components/idf_test/include/esp32c5/idf_performance_target.h index dd3f635e54..7f0986535d 100644 --- a/components/idf_test/include/esp32c5/idf_performance_target.h +++ b/components/idf_test/include/esp32c5/idf_performance_target.h @@ -5,3 +5,11 @@ */ #pragma once + +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 5 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 5 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4 5 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_8 5 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_16 5 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64 5 +#define IDF_PERFORMANCE_MAX_ADC_ONESHOT_STD_ATTEN3 5 diff --git a/components/soc/esp32c5/adc_periph.c b/components/soc/esp32c5/adc_periph.c new file mode 100644 index 0000000000..9f9bd96cfb --- /dev/null +++ b/components/soc/esp32c5/adc_periph.c @@ -0,0 +1,20 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/adc_periph.h" + +/* Store IO number corresponding to the ADC channel number. */ +const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { + /* ADC1 */ + { + ADC1_CHANNEL_0_GPIO_NUM, + ADC1_CHANNEL_1_GPIO_NUM, + ADC1_CHANNEL_2_GPIO_NUM, + ADC1_CHANNEL_3_GPIO_NUM, + ADC1_CHANNEL_4_GPIO_NUM, + ADC1_CHANNEL_5_GPIO_NUM, + }, +}; diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index ad5ad1da43..14dd3a6e48 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### +config SOC_ADC_SUPPORTED + bool + default y + config SOC_UART_SUPPORTED bool default y @@ -191,13 +195,85 @@ config SOC_AES_SUPPORT_AES_256 bool default y +config SOC_ADC_DIG_CTRL_SUPPORTED + bool + default y + +config SOC_ADC_DIG_IIR_FILTER_SUPPORTED + bool + default y + +config SOC_ADC_MONITOR_SUPPORTED + bool + default y + +config SOC_ADC_DMA_SUPPORTED + bool + default y + config SOC_ADC_PERIPH_NUM int default 1 config SOC_ADC_MAX_CHANNEL_NUM int - default 7 + default 6 + +config SOC_ADC_ATTEN_NUM + int + default 4 + +config SOC_ADC_DIGI_CONTROLLER_NUM + int + default 1 + +config SOC_ADC_PATT_LEN_MAX + int + default 8 + +config SOC_ADC_DIGI_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_IIR_FILTER_NUM + int + default 2 + +config SOC_ADC_DIGI_MONITOR_NUM + int + default 2 + +config SOC_ADC_DIGI_RESULT_BYTES + int + default 4 + +config SOC_ADC_DIGI_DATA_BYTES_PER_CONV + int + default 4 + +config SOC_ADC_SAMPLE_FREQ_THRES_HIGH + int + default 83333 + +config SOC_ADC_SAMPLE_FREQ_THRES_LOW + int + default 611 + +config SOC_ADC_RTC_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_RTC_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_SHARED_POWER + bool + default y config SOC_SHARED_IDCACHE_SUPPORTED bool diff --git a/components/soc/esp32c5/include/soc/adc_channel.h b/components/soc/esp32c5/include/soc/adc_channel.h index 0f7c05d929..a540b82758 100644 --- a/components/soc/esp32c5/include/soc/adc_channel.h +++ b/components/soc/esp32c5/include/soc/adc_channel.h @@ -6,24 +6,20 @@ #pragma once -// TODO: [ESP32-C5] IDF-8701 Check the channel -#define ADC1_GPIO0_CHANNEL 0 -#define ADC1_CHANNEL_0_GPIO_NUM 0 +#define ADC1_GPIO1_CHANNEL 0 +#define ADC1_CHANNEL_0_GPIO_NUM 1 -#define ADC1_GPIO1_CHANNEL 1 -#define ADC1_CHANNEL_1_GPIO_NUM 1 +#define ADC1_GPIO2_CHANNEL 1 +#define ADC1_CHANNEL_1_GPIO_NUM 2 -#define ADC1_GPIO2_CHANNEL 2 -#define ADC1_CHANNEL_2_GPIO_NUM 2 +#define ADC1_GPIO3_CHANNEL 2 +#define ADC1_CHANNEL_2_GPIO_NUM 3 -#define ADC1_GPIO3_CHANNEL 3 -#define ADC1_CHANNEL_3_GPIO_NUM 3 +#define ADC1_GPIO4_CHANNEL 3 +#define ADC1_CHANNEL_3_GPIO_NUM 4 -#define ADC1_GPIO4_CHANNEL 4 -#define ADC1_CHANNEL_4_GPIO_NUM 4 +#define ADC1_GPIO5_CHANNEL 4 +#define ADC1_CHANNEL_4_GPIO_NUM 5 -#define ADC1_GPIO5_CHANNEL 5 -#define ADC1_CHANNEL_5_GPIO_NUM 5 - -#define ADC1_GPIO6_CHANNEL 6 -#define ADC1_CHANNEL_6_GPIO_NUM 6 +#define ADC1_GPIO6_CHANNEL 5 +#define ADC1_CHANNEL_5_GPIO_NUM 6 diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 1629252d8e..18d8dc5bfa 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -433,7 +433,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8691, IDF-8692 (inherit from C6) /** * @brief ADC digital controller clock source */ -typedef enum { // TODO: [ESP32C5] IDF-8701, IDF-8702, IDF-8703 (inherit from C6) +typedef enum { ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ diff --git a/components/soc/esp32c5/include/soc/regi2c_saradc.h b/components/soc/esp32c5/include/soc/regi2c_saradc.h new file mode 100644 index 0000000000..a5f8fbf611 --- /dev/null +++ b/components/soc/esp32c5/include/soc/regi2c_saradc.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_saradc.h + * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC. + * + * This file lists register fields of SAR, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * function in adc_ll.h. + */ + +#define I2C_SAR_ADC 0X69 +#define I2C_SAR_ADC_HOSTID 0 + +#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB 0x0 +#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_MSB 0x7 +#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_LSB 0x0 + +#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB 0x1 +#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_MSB 0x3 +#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_LSB 0x0 + +#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 + +#define ADC_SAR1_DREF_ADDR 0x2 +#define ADC_SAR1_DREF_ADDR_MSB 0x6 +#define ADC_SAR1_DREF_ADDR_LSB 0x4 + +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0 + +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 + +#define ADC_SAR2_SAMPLE_CYCLE_ADDR 0x5 +#define ADC_SAR2_SAMPLE_CYCLE_ADDR_MSB 0x2 +#define ADC_SAR2_SAMPLE_CYCLE_ADDR_LSB 0x0 + +#define ADC_SAR2_DREF_ADDR 0x5 +#define ADC_SAR2_DREF_ADDR_MSB 0x6 +#define ADC_SAR2_DREF_ADDR_LSB 0x4 + +#define I2C_SARADC_TSENS_DAC 0x6 +#define I2C_SARADC_TSENS_DAC_MSB 0x3 +#define I2C_SARADC_TSENS_DAC_LSB 0x0 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 25d312c41c..34d9b54025 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -17,7 +17,7 @@ #pragma once /*-------------------------- COMMON CAPS ---------------------------------------*/ -// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701 +#define SOC_ADC_SUPPORTED 1 // #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725 #define SOC_UART_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 @@ -94,32 +94,32 @@ /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ -// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 -// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 -// #define SOC_ADC_MONITOR_SUPPORTED 1 -// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit -// #define SOC_ADC_DMA_SUPPORTED 1 +#define SOC_ADC_DIG_CTRL_SUPPORTED 1 +#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +#define SOC_ADC_MONITOR_SUPPORTED 1 +#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +#define SOC_ADC_DMA_SUPPORTED 1 #define SOC_ADC_PERIPH_NUM (1U) -// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) -#define SOC_ADC_MAX_CHANNEL_NUM (7) -// #define SOC_ADC_ATTEN_NUM (4) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (6) +#define SOC_ADC_MAX_CHANNEL_NUM (6) +#define SOC_ADC_ATTEN_NUM (4) /*!< Digital */ -// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) -// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ -// #define SOC_ADC_DIGI_MAX_BITWIDTH (12) -// #define SOC_ADC_DIGI_MIN_BITWIDTH (12) -// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) -// #define SOC_ADC_DIGI_MONITOR_NUM (2) -// #define SOC_ADC_DIGI_RESULT_BYTES (4) -// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +#define SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_MIN_BITWIDTH (12) +#define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_DIGI_RESULT_BYTES (4) +#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ -// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 -// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 /*!< RTC */ -// #define SOC_ADC_RTC_MIN_BITWIDTH (12) -// #define SOC_ADC_RTC_MAX_BITWIDTH (12) +#define SOC_ADC_RTC_MIN_BITWIDTH (12) +#define SOC_ADC_RTC_MAX_BITWIDTH (12) /*!< Calibration */ // #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ @@ -127,10 +127,10 @@ // #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ /*!< Interrupt */ -// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) +// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) // TODO: [ESP32C5] IDF-8727 /*!< ADC power control is shared by PWDET */ -// #define SOC_ADC_SHARED_POWER 1 +#define SOC_ADC_SHARED_POWER 1 // ESP32C5-TODO: Copy from esp32C5, need check /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ diff --git a/docs/docs_not_updated/esp32c5.txt b/docs/docs_not_updated/esp32c5.txt index 10d49479d1..c01cdc9ce5 100644 --- a/docs/docs_not_updated/esp32c5.txt +++ b/docs/docs_not_updated/esp32c5.txt @@ -76,8 +76,6 @@ api-reference/storage/fatfsgen.rst api-reference/storage/index.rst api-reference/storage/nvs_partition_parse.rst api-reference/peripherals/sdspi_share.rst -api-reference/peripherals/adc_continuous.rst -api-reference/peripherals/adc_oneshot.rst api-reference/peripherals/usb_host.rst api-reference/peripherals/twai.rst api-reference/peripherals/usb_host/usb_host_notes_arch.rst diff --git a/docs/en/api-reference/peripherals/adc_continuous.rst b/docs/en/api-reference/peripherals/adc_continuous.rst index a22c733430..0b8ff39399 100644 --- a/docs/en/api-reference/peripherals/adc_continuous.rst +++ b/docs/en/api-reference/peripherals/adc_continuous.rst @@ -3,7 +3,7 @@ Analog to Digital Converter (ADC) Continuous Mode Driver :link_to_translation:`zh_CN:[中文]` -{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one"} +{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one", esp32c5="one"} Introduction ------------ diff --git a/docs/en/api-reference/peripherals/adc_oneshot.rst b/docs/en/api-reference/peripherals/adc_oneshot.rst index bec0bee186..0f07197216 100644 --- a/docs/en/api-reference/peripherals/adc_oneshot.rst +++ b/docs/en/api-reference/peripherals/adc_oneshot.rst @@ -3,7 +3,7 @@ Analog to Digital Converter (ADC) Oneshot Mode Driver :link_to_translation:`zh_CN:[中文]` -{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one"} +{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one", esp32c5="one"} Introduction ------------ diff --git a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst index 3e3ccdcc71..b9158a9cf3 100644 --- a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst +++ b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst @@ -3,7 +3,7 @@ :link_to_translation:`en:[English]` -{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一"} +{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一", esp32c5="一"} 简介 ------------ diff --git a/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst b/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst index 7c8687b480..093adfde30 100644 --- a/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst +++ b/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst @@ -3,7 +3,7 @@ :link_to_translation:`en:[English]` -{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一"} +{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一", esp32c5="一"} 简介 ---- diff --git a/examples/peripherals/adc/continuous_read/README.md b/examples/peripherals/adc/continuous_read/README.md index e02022f3c1..614dedffb6 100644 --- a/examples/peripherals/adc/continuous_read/README.md +++ b/examples/peripherals/adc/continuous_read/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # ADC DMA Example diff --git a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py index 7c820be545..c891db39e8 100644 --- a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py +++ b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 - import pytest from pytest_embedded.dut import Dut @@ -11,6 +10,7 @@ from pytest_embedded.dut import Dut @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 +@pytest.mark.esp32c5 @pytest.mark.adc def test_adc_continuous(dut: Dut) -> None: res = dut.expect(r'TASK: ret is 0, ret_num is (\d+) bytes') diff --git a/examples/peripherals/adc/oneshot_read/README.md b/examples/peripherals/adc/oneshot_read/README.md index 15404c47ee..431ae89904 100644 --- a/examples/peripherals/adc/oneshot_read/README.md +++ b/examples/peripherals/adc/oneshot_read/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # ADC Single Read Example diff --git a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py index 8bb86e3c00..4fb24a6d3c 100644 --- a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py +++ b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py @@ -10,6 +10,7 @@ from pytest_embedded.dut import Dut @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 +@pytest.mark.esp32c5 @pytest.mark.adc def test_adc_oneshot(dut: Dut) -> None: dut.expect(r'EXAMPLE: ADC1 Channel\[(\d+)\] Raw Data: (\d+)', timeout=5) From 2f49a2e9c842dcdd582ce186755afa1cf3af6c38 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Sat, 13 Jul 2024 14:06:57 +0800 Subject: [PATCH 2/2] feat(adc): add ADC func clock enable function on C5,C6,H2 --- components/esp_hw_support/adc_share_hw_ctrl.c | 6 ++++++ components/hal/esp32c5/include/hal/adc_ll.h | 11 +++++++++++ components/hal/esp32c6/include/hal/adc_ll.h | 11 +++++++++++ components/hal/esp32h2/include/hal/adc_ll.h | 11 +++++++++++ 4 files changed, 39 insertions(+) diff --git a/components/esp_hw_support/adc_share_hw_ctrl.c b/components/esp_hw_support/adc_share_hw_ctrl.c index 32f3c67b79..a9054d47a1 100644 --- a/components/esp_hw_support/adc_share_hw_ctrl.c +++ b/components/esp_hw_support/adc_share_hw_ctrl.c @@ -207,6 +207,9 @@ void adc_apb_periph_claim(void) if (s_adc_digi_ctrlr_cnt == 1) { ADC_BUS_CLK_ATOMIC() { adc_ll_enable_bus_clock(true); +#if SOC_RCC_IS_INDEPENDENT + adc_ll_enable_func_clock(true); +#endif adc_ll_reset_register(); } } @@ -221,6 +224,9 @@ void adc_apb_periph_free(void) if (s_adc_digi_ctrlr_cnt == 0) { ADC_BUS_CLK_ATOMIC() { adc_ll_enable_bus_clock(false); +#if SOC_RCC_IS_INDEPENDENT + adc_ll_enable_func_clock(false); +#endif } } else if (s_adc_digi_ctrlr_cnt < 0) { portEXIT_CRITICAL(&s_spinlock); diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h index 616ea25e61..7c491440b4 100644 --- a/components/hal/esp32c5/include/hal/adc_ll.h +++ b/components/hal/esp32c5/include/hal/adc_ll.h @@ -566,6 +566,17 @@ static inline void adc_ll_enable_bus_clock(bool enable) PCR.saradc_conf.saradc_reg_clk_en = enable; } +#if SOC_RCC_IS_INDEPENDENT +/** + * @brief Enable the ADC function clock + * @param enable true to enable, false to disable + */ +static inline void adc_ll_enable_func_clock(bool enable) +{ + PCR.saradc_clkm_conf.saradc_clkm_en = enable; +} +#endif + /** * @brief Reset ADC module */ diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h index db51a869da..439f4c0514 100644 --- a/components/hal/esp32c6/include/hal/adc_ll.h +++ b/components/hal/esp32c6/include/hal/adc_ll.h @@ -565,6 +565,17 @@ static inline void adc_ll_enable_bus_clock(bool enable) PCR.saradc_conf.saradc_reg_clk_en = enable; } +#if SOC_RCC_IS_INDEPENDENT +/** + * @brief Enable the ADC function clock + * @param enable true to enable, false to disable + */ +static inline void adc_ll_enable_func_clock(bool enable) +{ + PCR.saradc_clkm_conf.saradc_clkm_en = enable; +} +#endif + /** * @brief Reset ADC module */ diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h index 8c02ddd191..ab7f8fa58f 100644 --- a/components/hal/esp32h2/include/hal/adc_ll.h +++ b/components/hal/esp32h2/include/hal/adc_ll.h @@ -566,6 +566,17 @@ static inline void adc_ll_enable_bus_clock(bool enable) PCR.saradc_conf.saradc_reg_clk_en = enable; } +#if SOC_RCC_IS_INDEPENDENT +/** + * @brief Enable the ADC function clock + * @param enable true to enable, false to disable + */ +static inline void adc_ll_enable_func_clock(bool enable) +{ + PCR.saradc_clkm_conf.saradc_clkm_en = enable; +} +#endif + /** * @brief Reset ADC module */