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docs: JTAG debugging update for ESP32C6
This commit is contained in:
Erhan Kurubas
parent
2f1d30d155
commit
7cb79db71e
@ -6,17 +6,6 @@ api-guides/performance/speed
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api-guides/performance/size
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api-guides/performance/ram-usage
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api-guides/performance/index
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api-guides/jtag-debugging
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api-guides/jtag-debugging/debugging-examples
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api-guides/jtag-debugging/configure-ft2232h-jtag
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api-guides/jtag-debugging/tips-and-quirks
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api-guides/jtag-debugging/using-debugger
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api-guides/jtag-debugging/building-openocd-macos
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api-guides/jtag-debugging/building-openocd-linux
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api-guides/jtag-debugging/configure-other-jtag
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api-guides/jtag-debugging/building-openocd-windows
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api-guides/jtag-debugging/index
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api-guides/jtag-debugging/configure-builtin-jtag
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api-guides/partition-tables
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api-guides/app_trace
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api-guides/thread-local-storage
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@ -6,8 +6,8 @@
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Configure {IDF_TARGET_NAME} built-in JTAG Interface
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===================================================
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{IDF_TARGET_JTAG_PIN_Dneg:default="Not Updated!", esp32c3="GPIO18", esp32s3="GPIO19"}
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{IDF_TARGET_JTAG_PIN_Dpos:default="Not Updated!", esp32c3="GPIO19", esp32s3="GPIO20"}
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{IDF_TARGET_JTAG_PIN_Dneg:default="Not Updated!", esp32c3="GPIO18", esp32c6="GPIO12", esp32s3="GPIO19"}
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{IDF_TARGET_JTAG_PIN_Dpos:default="Not Updated!", esp32c3="GPIO19", esp32c6="GPIO13", esp32s3="GPIO20"}
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{IDF_TARGET_NAME} has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. The necessary connections are shown in the following section.
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@ -2,31 +2,25 @@ Configure Other JTAG Interfaces
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===============================
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:link_to_translation:`zh_CN:[中文]`
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{IDF_TARGET_JTAG_SEL_EFUSE:default="Not Updated!", esp32s3="STRAP_JTAG_SEL", esp32c6="JTAG_SEL_ENABLE"}
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For guidance about which JTAG interface to select when using OpenOCD with {IDF_TARGET_NAME}, refer to the section :ref:`jtag-debugging-selecting-jtag-adapter`. Then follow the configuration steps below to get it working.
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.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED and not esp32c3
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.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED
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Configure eFuses
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^^^^^^^^^^^^^^^^
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By default, {IDF_TARGET_NAME} JTAG interface is connected to the :doc:`built-in USB_SERIAL_JTAG peripheral <configure-builtin-jtag>`. To use an external JTAG adapter instead, you need to switch the JTAG interface to the GPIO pins. This can be done by burning eFuses using ``espefuse.py`` tool.
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- Burning ``DIS_USB_JTAG`` eFuse will permanently disable the connection between USB_SERIAL_JTAG and the JTAG port of the CPU. JTAG interface can then be connected to |jtag-gpio-list|. Note that USB CDC functionality of USB_SERIAL_JTAG will still be usable, i.e., flashing and monitoring over USB CDC will still work.
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- Burning ``STRAP_JTAG_SEL`` eFuse will enable selection of JTAG interface by a strapping pin, |jtag-sel-gpio|. If the strapping pin is low when {IDF_TARGET_NAME} is reset, JTAG interface will use |jtag-gpio-list|. If the strapping pin is high, USB_SERIAL_JTAG will be used as the JTAG interface.
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.. only:: esp32c3
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.. warning::
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Burning eFuses is an irreversible operation, so please consider the above options before starting the process.
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Burning ``DIS_USB_JTAG`` eFuse will permanently disable the connection between USB_SERIAL_JTAG and the JTAG port of the {IDF_TARGET_NAME}. JTAG interface can then be connected to |jtag-gpio-list|. Note that USB CDC functionality of USB_SERIAL_JTAG will still be usable, i.e., flashing and monitoring over USB CDC will still work.
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.. only:: esp32s3 or esp32c6
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.. only:: esp32c3
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Configure eFuses
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^^^^^^^^^^^^^^^^
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By default, {IDF_TARGET_NAME} JTAG interface is connected to the :doc:`built-in USB_SERIAL_JTAG peripheral <configure-builtin-jtag>`. To use an external JTAG adapter instead, you need to switch the JTAG interface to the GPIO pins. This can be done by burning eFuses using ``espefuse.py`` tool.
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Burning ``DIS_USB_JTAG`` eFuse will permanently disable the connection between USB_SERIAL_JTAG and the JTAG port of the CPU. JTAG interface can then be connected to |jtag-gpio-list|. Note that USB CDC functionality of USB_SERIAL_JTAG will still be usable, i.e., flashing and monitoring over USB CDC will still work.
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- Burning ``DIS_USB_JTAG`` eFuse will permanently disable the connection between USB_SERIAL_JTAG and the JTAG port of the {IDF_TARGET_NAME}. JTAG interface can then be connected to |jtag-gpio-list|. Note that USB CDC functionality of USB_SERIAL_JTAG will still be usable, i.e., flashing and monitoring over USB CDC will still work.
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- Burning ``{IDF_TARGET_JTAG_SEL_EFUSE}`` eFuse will enable selection of JTAG interface by a strapping pin, |jtag-sel-gpio|. If the strapping pin is low when {IDF_TARGET_NAME} is reset, JTAG interface will use |jtag-gpio-list|. If the strapping pin is high, USB_SERIAL_JTAG will be used as the JTAG interface.
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.. warning::
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Burning eFuses is an irreversible operation, so please consider the above option before starting the process.
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@ -6,7 +6,6 @@
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.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
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.. These code blocks can be moved back to the main .rst files, with target-specific
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.. file names being replaced by substitutions.
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.. TODO IDF-6033
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.. run-openocd
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@ -22,7 +21,28 @@
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::
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TO BE UPDATED
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user-name@computer-name:~/esp/esp-idf$ openocd -f board/esp32c6-builtin.cfg
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Open On-Chip Debugger v0.11.0-esp32-20221026-85-g0718fffd (2023-01-12-07:28)
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Licensed under GNU GPL v2
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For bug reports, read
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http://openocd.org/doc/doxygen/bugs.html
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Info : only one transport option; autoselect 'jtag'
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Info : esp_usb_jtag: VID set to 0x303a and PID to 0x1001
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Info : esp_usb_jtag: capabilities descriptor set to 0x2000
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Warn : Transport "jtag" was already selected
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WARNING: ESP flash support is disabled!
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force hard breakpoints
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Info : Listening on port 6666 for tcl connections
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Info : Listening on port 4444 for telnet connections
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Info : esp_usb_jtag: serial (60:55:F9:F6:03:3C)
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Info : esp_usb_jtag: Device found. Base speed 24000KHz, div range 1 to 255
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Info : clock speed 24000 kHz
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Info : JTAG tap: esp32c6.cpu tap/device found: 0x0000dc25 (mfg: 0x612 (Espressif Systems), part: 0x000d, ver: 0x0)
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Info : datacount=2 progbufsize=16
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Info : Examined RISC-V core; found 2 harts
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Info : hart 0: XLEN=32, misa=0x40903105
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Info : starting gdb server for esp32c6 on 3333
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Info : Listening on port 3333 for gdb connections
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.. |run-openocd-cfg-file-err| replace:: ``Can't find board/esp32c6-builtin.cfg``
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@ -68,14 +88,22 @@
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.. openocd-cfg-files
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.. list-table:: OpenOCD configuration files for ESP32-C3
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.. list-table:: OpenOCD configuration files for ESP32-C6
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:widths: 25 75
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:header-rows: 1
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* - Name
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- Description
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* - TO BE UPDATED
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- TO BE UPDATED
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* - ``board/esp32c6-builtin.cfg``
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- Board configuration file for ESP32-C6 through built-in USB, includes target and adapter configuration.
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* - ``board/esp32c6-ftdi.cfg``
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- Board configuration file for ESP32-C6 for via externally connected FTDI-based probe like ESP-Prog, includes target and adapter configuration.
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* - ``target/esp32c6.cfg``
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- ESP32-C6 target configuration file. Can be used together with one of the ``interface/`` configuration files.
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* - ``interface/esp_usb_jtag.cfg``
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- JTAG adapter configuration file for ESP32-C6.
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* - ``interface/ftdi/esp32_devkitj_v1.cfg``
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- JTAG adapter configuration file for ESP-Prog boards.
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---
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@ -93,17 +121,17 @@
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* - ESP32-C6 Pin
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- JTAG Signal
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* - MTDO
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* - MTDO / GPIO7
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- TDO
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* - MTDI
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* - MTDI / GPIO5
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- TDI
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* - MTCK
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* - MTCK / GPIO6
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- TCK
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* - MTMS
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* - MTMS / GPIO4
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- TMS
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.. |jtag-sel-gpio| replace:: TO BE UPDATED
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.. |jtag-gpio-list| replace:: TO BE UPDATED
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.. |jtag-sel-gpio| replace:: GPIO15
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.. |jtag-gpio-list| replace:: GPIO4-GPIO7
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---
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@ -206,13 +206,15 @@ Another option is to write application image to flash using OpenOCD via JTAG wit
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OpenOCD flashing command ``program_esp`` has the following format:
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``program_esp <image_file> <offset> [verify] [reset] [exit]``
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``program_esp <image_file> <offset> [verify] [reset] [exit] [compress] [encrypt]``
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- ``image_file`` - Path to program image file.
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- ``offset`` - Offset in flash bank to write image.
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- ``verify`` - Optional. Verify flash contents after writing.
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- ``reset`` - Optional. Reset target after programing.
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- ``exit`` - Optional. Finally exit OpenOCD.
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- ``compress`` - Optional. Compress image file before programming.
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- ``encrypt`` - Optional. Encrypt binary before writing to flash. Same functionality with ``idf.py encrypted-flash``
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You are now ready to start application debugging. Follow the steps described in the section below.
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@ -6,7 +6,6 @@
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.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
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.. These code blocks can be moved back to the main .rst files, with target-specific
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.. file names being replaced by substitutions.
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.. TODO IDF-6033
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.. run-openocd
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@ -22,7 +21,28 @@
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::
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TO BE UPDATED
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user-name@computer-name:~/esp/esp-idf$ openocd -f board/esp32c6-builtin.cfg
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Open On-Chip Debugger v0.11.0-esp32-20221026-85-g0718fffd (2023-01-12-07:28)
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Licensed under GNU GPL v2
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For bug reports, read
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http://openocd.org/doc/doxygen/bugs.html
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Info : only one transport option; autoselect 'jtag'
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Info : esp_usb_jtag: VID set to 0x303a and PID to 0x1001
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Info : esp_usb_jtag: capabilities descriptor set to 0x2000
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Warn : Transport "jtag" was already selected
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WARNING: ESP flash support is disabled!
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force hard breakpoints
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Info : Listening on port 6666 for tcl connections
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Info : Listening on port 4444 for telnet connections
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Info : esp_usb_jtag: serial (60:55:F9:F6:03:3C)
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Info : esp_usb_jtag: Device found. Base speed 24000KHz, div range 1 to 255
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Info : clock speed 24000 kHz
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Info : JTAG tap: esp32c6.cpu tap/device found: 0x0000dc25 (mfg: 0x612 (Espressif Systems), part: 0x000d, ver: 0x0)
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Info : datacount=2 progbufsize=16
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Info : Examined RISC-V core; found 2 harts
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Info : hart 0: XLEN=32, misa=0x40903105
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Info : starting gdb server for esp32c6 on 3333
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Info : Listening on port 3333 for gdb connections
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.. |run-openocd-cfg-file-err| replace:: ``Can't find board/esp32c6-builtin.cfg``
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@ -68,14 +88,22 @@
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.. openocd-cfg-files
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.. list-table:: OpenOCD configuration files for ESP32-C3
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.. list-table:: OpenOCD configuration files for ESP32-C6
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:widths: 25 75
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:header-rows: 1
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* - Name
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- Description
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* - TO BE UPDATED
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- TO BE UPDATED
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* - ``board/esp32c6-builtin.cfg``
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- Board configuration file for ESP32-C6 through built-in USB, includes target and adapter configuration.
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* - ``board/esp32c6-ftdi.cfg``
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- Board configuration file for ESP32-C6 for via externally connected FTDI-based probe like ESP-Prog, includes target and adapter configuration.
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* - ``target/esp32c6.cfg``
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- ESP32-C6 target configuration file. Can be used together with one of the ``interface/`` configuration files.
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* - ``interface/esp_usb_jtag.cfg``
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- JTAG adapter configuration file for ESP32-C6.
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* - ``interface/ftdi/esp32_devkitj_v1.cfg``
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- JTAG adapter configuration file for ESP-Prog boards.
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---
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@ -93,17 +121,17 @@
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* - ESP32-C6 Pin
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- JTAG Signal
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* - MTDO
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* - MTDO / GPIO7
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- TDO
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* - MTDI
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* - MTDI / GPIO5
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- TDI
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* - MTCK
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* - MTCK / GPIO6
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- TCK
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* - MTMS
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* - MTMS / GPIO4
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- TMS
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.. |jtag-sel-gpio| replace:: TO BE UPDATED
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.. |jtag-gpio-list| replace:: TO BE UPDATED
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.. |jtag-sel-gpio| replace:: GPIO15
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.. |jtag-gpio-list| replace:: GPIO4-GPIO7
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---
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@ -41,4 +41,5 @@ OPENOCD_TAGET_CONFIG: Dict[str, str] = {
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'esp32s2': '-f board/esp32s2-kaluga-1.cfg',
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'esp32c3': '-f board/esp32c3-builtin.cfg',
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'esp32s3': '-f board/esp32s3-builtin.cfg',
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'esp32c6': '-f board/esp32c6-builtin.cfg',
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}
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