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Merge branch 'contrib/github_pr_10997' into 'master'
i2s: intrerrupt fix (GitHub PR) Closes IDFGH-9650 and IDFGH-9654 See merge request espressif/esp-idf!22945
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commit
7c5d65b82b
@ -53,17 +53,6 @@
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* Set 4092 here to align with 4-byte, so that the position of the slot data in the buffer will be relatively fixed */
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#define I2S_DMA_BUFFER_MAX_SIZE (4092)
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// If ISR handler is allowed to run whilst cache is disabled,
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// Make sure all the code and related variables used by the handler are in the SRAM
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#if CONFIG_I2S_ISR_IRAM_SAFE
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#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED)
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#define I2S_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED)
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#define I2S_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
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#endif //CONFIG_I2S_ISR_IRAM_SAFE
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#define I2S_DMA_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA)
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/**
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* @brief Global i2s platform object
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* @note For saving all the I2S related information
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@ -180,7 +180,7 @@ esp_err_t i2s_channel_init_pdm_tx_mode(i2s_chan_handle_t handle, const i2s_pdm_t
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}
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#endif
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ESP_GOTO_ON_ERROR(i2s_pdm_tx_set_clock(handle, &pdm_tx_cfg->clk_cfg), err, TAG, "initialize channel failed while setting clock");
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ESP_GOTO_ON_ERROR(i2s_init_dma_intr(handle, ESP_INTR_FLAG_LEVEL1), err, TAG, "initialize dma interrupt failed");
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ESP_GOTO_ON_ERROR(i2s_init_dma_intr(handle, I2S_INTR_ALLOC_FLAGS), err, TAG, "initialize dma interrupt failed");
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i2s_ll_tx_enable_pdm(handle->controller->hal.dev);
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#if SOC_I2S_HW_VERSION_2
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -23,6 +23,17 @@
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extern "C" {
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#endif
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// If ISR handler is allowed to run whilst cache is disabled,
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// Make sure all the code and related variables used by the handler are in the SRAM
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#if CONFIG_I2S_ISR_IRAM_SAFE
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#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED)
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#define I2S_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED)
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#define I2S_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
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#endif //CONFIG_I2S_ISR_IRAM_SAFE
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#define I2S_DMA_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA)
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#define I2S_NULL_POINTER_CHECK(tag, p) ESP_RETURN_ON_FALSE((p), ESP_ERR_INVALID_ARG, tag, "input parameter '"#p"' is NULL")
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/**
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@ -217,7 +217,7 @@ esp_err_t i2s_channel_init_std_mode(i2s_chan_handle_t handle, const i2s_std_conf
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}
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#endif
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ESP_GOTO_ON_ERROR(i2s_std_set_clock(handle, &std_cfg->clk_cfg), err, TAG, "initialize channel failed while setting clock");
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ESP_GOTO_ON_ERROR(i2s_init_dma_intr(handle, ESP_INTR_FLAG_LEVEL1), err, TAG, "initialize dma interrupt failed");
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ESP_GOTO_ON_ERROR(i2s_init_dma_intr(handle, I2S_INTR_ALLOC_FLAGS), err, TAG, "initialize dma interrupt failed");
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#if SOC_I2S_HW_VERSION_2
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/* Enable clock to start outputting mclk signal. Some codecs will reset once mclk stop */
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if (handle->dir == I2S_DIR_TX) {
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@ -222,7 +222,7 @@ esp_err_t i2s_channel_init_tdm_mode(i2s_chan_handle_t handle, const i2s_tdm_conf
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}
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#endif
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ESP_GOTO_ON_ERROR(i2s_tdm_set_clock(handle, &tdm_cfg->clk_cfg), err, TAG, "initialize channel failed while setting clock");
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ESP_GOTO_ON_ERROR(i2s_init_dma_intr(handle, ESP_INTR_FLAG_LEVEL1), err, TAG, "initialize dma interrupt failed");
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ESP_GOTO_ON_ERROR(i2s_init_dma_intr(handle, I2S_INTR_ALLOC_FLAGS), err, TAG, "initialize dma interrupt failed");
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#if SOC_I2S_HW_VERSION_2
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/* Enable clock to start outputting mclk signal. Some codecs will reset once mclk stop */
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