mirror of
https://github.com/espressif/esp-idf.git
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Merge branch 'feature/optimize_chips_memory_allocation' into 'master'
system: Optimize chips bootloader and heap memory allocation Closes IDF-4585 and IDF-4299 See merge request espressif/esp-idf!18807
This commit is contained in:
Wu Zheng Hui
commit
7c17a04733
@ -5,15 +5,41 @@
|
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*/
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/** Simplified memory map for the bootloader.
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* Make sure the bootloader can load into main memory without overwriting itself.
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* We put 2nd bootloader in the high address space (before ROM stack/data/bss).
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* See memory usage for ROM bootloader at the end of this file.
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*
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* ESP32-C2 ROM static data usage is as follows:
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* - 0x3fccb264 - 0x3fcdcb70: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x3fcdcb70 - 0x3fcdeb70: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fcdeb70 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
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*
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* The 2nd stage bootloader can take space up to the end of ROM shared
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* buffers area (0x3fcdcb70).
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*/
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/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */
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iram_dram_offset = 0x6e0000;
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/* We consider 0x3fcdcb70 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
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* and work out iram_seg and iram_loader_seg addresses from there, backwards.
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*/
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/* These lengths can be adjusted, if necessary: */
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bootloader_usable_dram_end = 0x3fcdcb70;
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bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
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bootloader_dram_seg_len = 0x5000;
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bootloader_iram_loader_seg_len = 0x7000;
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bootloader_iram_seg_len = 0x2000;
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/* Start of the lower region is determined by region size and the end of the higher region */
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bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
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bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
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bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;
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bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
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MEMORY
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{
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iram_seg (RWX) : org = 0x403AE000, len = 0x2000
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iram_loader_seg (RWX) : org = 0x403B0000, len = 0x6000
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dram_seg (RW) : org = 0x3FCD6000, len = 0x4000
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iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
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iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
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dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
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}
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/* Default entry point: */
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@ -183,17 +209,34 @@ SECTIONS
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/**
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* Appendix: Memory Usage of ROM bootloader
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*
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* +--------+--------------+------+ 0x3FCC_B0B0
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* | ^ |
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* | | |
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* | | data/bss |
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* | | |
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* | v |
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* +------------------------------+ 0x3FCD_C9C0
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* | ^ |
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* | | |
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* | | stack |
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* | | |
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* | v |
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* +------------------------------+ 0x3FCD_E9C0
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* 0x3fccb264 ------------------> _dram0_0_start
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* | |
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* | |
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* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
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* | |
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* | |
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* 0x3fcdcb70 ------------------> __stack_sentry
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* | |
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* | | 2. Startup pro cpu stack (freed when IDF app is running)
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* | |
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* 0x3fcdeb70 ------------------> __stack (pro cpu)
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* | |
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* | |
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* | | 3. Shared memory only used in startup code or nonos/early boot*
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* | | (can be freed when IDF runs)
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* | |
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* | |
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* 0x3fcdf4bc ------------------> _dram0_rtos_reserved_start
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* | |
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* | |
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* | | 4. Shared memory used in startup code and when IDF runs
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* | |
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* | |
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* 0x3fcdfa70 ------------------> _dram0_rtos_reserved_end
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* | |
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* 0x3fcdfa74 ------------------> _data_start_interface
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* | |
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* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
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* | |
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* 0x3fce0000 ------------------> _data_end_interface
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*/
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@ -5,15 +5,41 @@
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*/
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/** Simplified memory map for the bootloader.
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* Make sure the bootloader can load into main memory without overwriting itself.
|
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* We put 2nd bootloader in the high address space (before ROM stack/data/bss).
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* See memory usage for ROM bootloader at the end of this file.
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*
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* ESP32-C3 ROM static data usage is as follows:
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* - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
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*
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* The 2nd stage bootloader can take space up to the end of ROM shared
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* buffers area (0x3fcdc710).
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*/
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/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */
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iram_dram_offset = 0x700000;
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/* We consider 0x3fcdc710 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
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* and work out iram_seg and iram_loader_seg addresses from there, backwards.
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*/
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/* These lengths can be adjusted, if necessary: */
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bootloader_usable_dram_end = 0x3fcdc710;
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bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
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bootloader_dram_seg_len = 0x5000;
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bootloader_iram_loader_seg_len = 0x7000;
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bootloader_iram_seg_len = 0x2000;
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/* Start of the lower region is determined by region size and the end of the higher region */
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bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
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bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
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bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;
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bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
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MEMORY
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{
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iram_seg (RWX) : org = 0x403CE000, len = 0x1600
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iram_loader_seg (RWX) : org = 0x403CF600, len = 0x6A00
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dram_seg (RW) : org = 0x3FCD6000, len = 0x4000
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iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
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iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
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dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
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}
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/* Default entry point: */
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@ -184,17 +210,34 @@ SECTIONS
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/**
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* Appendix: Memory Usage of ROM bootloader
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*
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* +--------+--------------+------+ 0x3FCC_AE00
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* | ^ |
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* | | |
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* | | data/bss |
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* | | |
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* | v |
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* +------------------------------+ 0x3FCD_C710
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* | ^ |
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* | | |
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* | | stack |
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* | | |
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* | v |
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* +------------------------------+ 0x3FCD_E710
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* 0x3fccae00 ------------------> _dram0_0_start
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* | |
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* | |
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* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
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* | |
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||||
* | |
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* 0x3fcdc710 ------------------> __stack_sentry
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* | |
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* | | 2. Startup pro cpu stack (freed when IDF app is running)
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* | |
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* 0x3fcde710 ------------------> __stack (pro cpu)
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* | |
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* | |
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* | | 3. Shared memory only used in startup code or nonos/early boot*
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* | | (can be freed when IDF runs)
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* | |
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* | |
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* 0x3fcdf060 ------------------> _dram0_rtos_reserved_start
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* | |
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* | |
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* | | 4. Shared memory used in startup code and when IDF runs
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* | |
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* | |
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* 0x3fcdf664 ------------------> _dram0_rtos_reserved_end
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* | |
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* 0x3fcdf830 ------------------> _data_start_interface
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* | |
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* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
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* | |
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* 0x3fce0000 ------------------> _data_end_interface
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*/
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@ -5,15 +5,41 @@
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||||
*/
|
||||
/** Simplified memory map for the bootloader.
|
||||
* Make sure the bootloader can load into main memory without overwriting itself.
|
||||
* We put 2nd bootloader in the high address space (before ROM stack/data/bss).
|
||||
* See memory usage for ROM bootloader at the end of this file.
|
||||
*
|
||||
* ESP32-H2 ROM static data usage is as follows:
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* - 0x3fccb900 - 0x3fcdd210: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x3fcdd210 - 0x3fcdf210: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fcdf210 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
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*
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* The 2nd stage bootloader can take space up to the end of ROM shared
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* buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700).
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*/
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/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */
|
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iram_dram_offset = 0x700000;
|
||||
|
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/* We consider 0x3fce9700 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
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* and work out iram_seg and iram_loader_seg addresses from there, backwards.
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*/
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/* These lengths can be adjusted, if necessary: */
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bootloader_usable_dram_end = 0x3fcdd120;
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bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
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bootloader_dram_seg_len = 0x5000;
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bootloader_iram_loader_seg_len = 0x7000;
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bootloader_iram_seg_len = 0x2000;
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/* Start of the lower region is determined by region size and the end of the higher region */
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bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
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bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
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bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;
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bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
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MEMORY
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{
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iram_seg (RWX) : org = 0x403CE000, len = 0x2000
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iram_loader_seg (RWX) : org = 0x403D0000, len = 0x6000
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dram_seg (RW) : org = 0x3FCD6000, len = 0x4000
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iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
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iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
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dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
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}
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|
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/* Default entry point: */
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@ -181,17 +207,34 @@ SECTIONS
|
||||
/**
|
||||
* Appendix: Memory Usage of ROM bootloader
|
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*
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* +--------+--------------+------+ 0x3FCC_B900
|
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* | ^ |
|
||||
* | | |
|
||||
* | | data/bss |
|
||||
* | | |
|
||||
* | v |
|
||||
* +------------------------------+ 0x3FCD_D210
|
||||
* | ^ |
|
||||
* | | |
|
||||
* | | stack |
|
||||
* | | |
|
||||
* | v |
|
||||
* +------------------------------+ 0x3FCD_F210
|
||||
* 0x3fccb81c ------------------> _dram0_0_start
|
||||
* | |
|
||||
* | |
|
||||
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
|
||||
* | |
|
||||
* | |
|
||||
* 0x3fcdd120 ------------------> __stack_sentry
|
||||
* | |
|
||||
* | | 2. Startup pro cpu stack (freed when IDF app is running)
|
||||
* | |
|
||||
* 0x3fcdf120 ------------------> __stack (pro cpu)
|
||||
* | |
|
||||
* | |
|
||||
* | | 3. Shared memory only used in startup code or nonos/early boot*
|
||||
* | | (can be freed when IDF runs)
|
||||
* | |
|
||||
* | |
|
||||
* 0x3fcdfa6c ------------------> _dram0_rtos_reserved_start
|
||||
* | |
|
||||
* | |
|
||||
* | | 4. Shared memory used in startup code and when IDF runs
|
||||
* | |
|
||||
* | |
|
||||
* 0x3fcdfe40 ------------------> _dram0_rtos_reserved_end
|
||||
* | |
|
||||
* 0x3fcdfe4c ------------------> _data_start_interface
|
||||
* | |
|
||||
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
|
||||
* | |
|
||||
* 0x3fce0000 ------------------> _data_end_interface
|
||||
*/
|
||||
|
||||
@ -233,3 +233,42 @@ SECTIONS
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Appendix: Memory Usage of ROM bootloader
|
||||
*
|
||||
* 0x3fcd7e00 ------------------> _dram0_0_start
|
||||
* | |
|
||||
* | |
|
||||
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
|
||||
* | |
|
||||
* | |
|
||||
* 0x3fce9710 ------------------> __stack_sentry
|
||||
* | |
|
||||
* | | 2. Startup pro cpu stack (freed when IDF app is running)
|
||||
* | |
|
||||
* 0x3fceb710 ------------------> __stack (pro cpu)
|
||||
* | |
|
||||
* | | Startup app cpu stack
|
||||
* | |
|
||||
* 0x3fced710 ------------------> __stack_app (app cpu)
|
||||
* | |
|
||||
* | |
|
||||
* | | 3. Shared memory only used in startup code or nonos/early boot*
|
||||
* | | (can be freed when IDF runs)
|
||||
* | |
|
||||
* | |
|
||||
* 0x3fceee34 ------------------> _dram0_rtos_reserved_start
|
||||
* | |
|
||||
* | |
|
||||
* | | 4. Shared memory used in startup code and when IDF runs
|
||||
* | |
|
||||
* | |
|
||||
* 0x3fcef770 ------------------> _dram0_rtos_reserved_end
|
||||
* | |
|
||||
* 0x3fcef81c ------------------> _data_start_interface
|
||||
* | |
|
||||
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
|
||||
* | |
|
||||
* 0x3fcf0000 ------------------> _data_end_interface
|
||||
*/
|
||||
|
||||
@ -27,14 +27,6 @@ extern "C" {
|
||||
#define DRAM_SRAM_START 0x3FC7C000
|
||||
#endif
|
||||
|
||||
#ifndef MAP_DRAM_TO_IRAM
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr - DRAM_SRAM_START + IRAM_SRAM_START)
|
||||
#endif
|
||||
|
||||
#ifndef MAP_IRAM_TO_DRAM
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr - IRAM_SRAM_START + DRAM_SRAM_START)
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
MEMPROT_NONE = 0x00000000,
|
||||
MEMPROT_IRAM0_SRAM = 0x00000001,
|
||||
|
||||
@ -50,9 +50,6 @@ typedef enum {
|
||||
} memprot_hal_area_t;
|
||||
|
||||
//auxiliary macros & defines
|
||||
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
|
||||
|
||||
#define MEMP_HAL_CHECK_IRAM_ADDR_IN_RANGE(x) if (x < SOC_DIRAM_IRAM_LOW || x >= SOC_DIRAM_IRAM_HIGH) { return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; }
|
||||
#define MEMP_HAL_CHECK_DRAM_ADDR_IN_RANGE(x) if (x < SOC_DIRAM_DRAM_LOW || x >= SOC_DIRAM_DRAM_HIGH) { return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; }
|
||||
|
||||
@ -25,19 +25,22 @@
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
// IDF-4299
|
||||
const soc_memory_type_desc_t soc_memory_types[] = {
|
||||
// Type 0: DRAM
|
||||
{ "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
{ "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
// Type 2: DRAM which has an alias on the I-port
|
||||
{ "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: IRAM
|
||||
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
|
||||
/* Index of memory in `soc_memory_types[]` */
|
||||
enum {
|
||||
SOC_MEMORY_TYPE_STACK_DRAM = 0,
|
||||
SOC_MEMORY_TYPE_DIRAM = 1,
|
||||
SOC_MEMORY_TYPE_NUM,
|
||||
};
|
||||
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 2
|
||||
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
|
||||
// Type 0: DRAM used for startup stacks
|
||||
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
// Type 1: DRAM which has an alias on the I-port
|
||||
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
};
|
||||
|
||||
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
|
||||
@ -49,26 +52,18 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
|
||||
*
|
||||
*/
|
||||
|
||||
#define RAM_BOTTOM_LEVEL_REUSE_SIZE 0x18000
|
||||
#define RAM_BOTTOM_LEVEL_RESERVE_SIZE 0x8000
|
||||
#define MIN_ADDR_OF_STARTUP_STACK_TOP 0x3FCD81D0 //TODO: IDF-4585
|
||||
|
||||
/*|------------------------------------ SRAM LEVEL 3 -------------------------------------|*/
|
||||
/*|0x3FCC0000 0x3FCDFFFF|*/
|
||||
/*|------------------------------------------------|--------------------------|-------------|*/
|
||||
/*| Shared Buffer | Startup Stack | Interface |*/
|
||||
/*|------------------------------------------------|--------------------------|-------------|*/
|
||||
/*| <---RAM_BOTTOM_LEVEL_REUSE_SIZE---> | <---------RAM_BOTTOM_LEVEL_RESERVE_SIZE---------> |*/
|
||||
/*|-----------------------------------------------------------------------------------------|*/
|
||||
/**
|
||||
* Register the shared buffer area of the last memory block into the heap during heap initialization
|
||||
*/
|
||||
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
|
||||
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 1, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //Block 2, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCC0000, RAM_BOTTOM_LEVEL_REUSE_SIZE, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 3, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCC0000 + RAM_BOTTOM_LEVEL_REUSE_SIZE, RAM_BOTTOM_LEVEL_RESERVE_SIZE, 1, 0x403A0000 + RAM_BOTTOM_LEVEL_REUSE_SIZE} //Block 4, can be used as trace memory
|
||||
{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1
|
||||
{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //D/IRAM level2
|
||||
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level3
|
||||
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)} //D/IRAM level3 (ROM reserved area)
|
||||
};
|
||||
|
||||
_Static_assert(0x3FCC0000 + RAM_BOTTOM_LEVEL_REUSE_SIZE <= MIN_ADDR_OF_STARTUP_STACK_TOP, "Heap reuse area overlaps startup stack");
|
||||
|
||||
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
|
||||
|
||||
|
||||
@ -24,23 +24,31 @@
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
const soc_memory_type_desc_t soc_memory_types[] = {
|
||||
|
||||
/* Index of memory in `soc_memory_types[]` */
|
||||
enum {
|
||||
SOC_MEMORY_TYPE_DRAM = 0,
|
||||
SOC_MEMORY_TYPE_STACK_DRAM = 1,
|
||||
SOC_MEMORY_TYPE_DIRAM = 2,
|
||||
SOC_MEMORY_TYPE_RTCRAM = 3,
|
||||
SOC_MEMORY_TYPE_NUM,
|
||||
};
|
||||
|
||||
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
|
||||
// Type 0: DRAM
|
||||
{ "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
{ "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
// Type 2: DRAM which has an alias on the I-port
|
||||
{ "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: IRAM
|
||||
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
// Type 4: RTCRAM
|
||||
{ "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
|
||||
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: RTCRAM
|
||||
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 0
|
||||
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
|
||||
#else
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 2
|
||||
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
|
||||
#endif
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
@ -52,12 +60,19 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
|
||||
* this list should always be sorted from low to high by start address.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* Register the shared buffer area of the last memory block into the heap during heap initialization
|
||||
*/
|
||||
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
|
||||
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 4, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory
|
||||
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory
|
||||
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory
|
||||
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory
|
||||
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x2000, 4, 0}, //Fast RTC memory
|
||||
{ 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@ -24,23 +24,30 @@
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
const soc_memory_type_desc_t soc_memory_types[] = {
|
||||
/* Index of memory in `soc_memory_types[]` */
|
||||
enum {
|
||||
SOC_MEMORY_TYPE_DRAM = 0,
|
||||
SOC_MEMORY_TYPE_STACK_DRAM = 1,
|
||||
SOC_MEMORY_TYPE_DIRAM = 2,
|
||||
SOC_MEMORY_TYPE_RTCRAM = 3,
|
||||
SOC_MEMORY_TYPE_NUM,
|
||||
};
|
||||
|
||||
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
|
||||
// Type 0: DRAM
|
||||
{ "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
{ "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
// Type 2: DRAM which has an alias on the I-port
|
||||
{ "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: IRAM
|
||||
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
// Type 4: RTCRAM
|
||||
{ "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false},
|
||||
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: RTCRAM
|
||||
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 0
|
||||
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
|
||||
#else
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 2
|
||||
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
|
||||
#endif
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
@ -52,12 +59,19 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
|
||||
* this list should always be sorted from low to high by start address.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* Register the shared buffer area of the last memory block into the heap during heap initialization
|
||||
*/
|
||||
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
|
||||
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 4, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory
|
||||
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory
|
||||
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory
|
||||
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory
|
||||
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x2000, 4, 0}, //Fast RTC memory
|
||||
{ 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@ -26,21 +26,34 @@
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
const soc_memory_type_desc_t soc_memory_types[] = {
|
||||
|
||||
/* Index of memory in `soc_memory_types[]` */
|
||||
enum {
|
||||
SOC_MEMORY_TYPE_DRAM = 0,
|
||||
SOC_MEMORY_TYPE_STACK_DRAM = 1,
|
||||
SOC_MEMORY_TYPE_DIRAM = 2,
|
||||
SOC_MEMORY_TYPE_IRAM = 3,
|
||||
SOC_MEMORY_TYPE_SPIRAM = 4,
|
||||
SOC_MEMORY_TYPE_NODMARAM = 5,
|
||||
SOC_MEMORY_TYPE_RTCRAM = 6,
|
||||
SOC_MEMORY_TYPE_NUM,
|
||||
};
|
||||
|
||||
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
|
||||
// Type 0: DRAM
|
||||
{ "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
{ "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true},
|
||||
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true},
|
||||
// Type 2: DRAM which has an alias on the I-port
|
||||
{ "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: IRAM
|
||||
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
[SOC_MEMORY_TYPE_IRAM] = { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
// Type 4: SPI SRAM data
|
||||
{ "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false},
|
||||
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false},
|
||||
// Type 5: DRAM which is not DMA accesible
|
||||
{ "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
[SOC_MEMORY_TYPE_NODMARAM] = { "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 6: RTC Fast RAM
|
||||
{ "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
|
||||
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
|
||||
};
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
@ -52,28 +65,35 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
|
||||
* this list should always be sorted from low to high by start address.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* Register the shared buffer area of the last memory block into the heap during heap initialization
|
||||
*/
|
||||
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
|
||||
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
#ifdef CONFIG_SPIRAM
|
||||
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available
|
||||
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0}, //SPI SRAM, if available
|
||||
#endif
|
||||
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB
|
||||
{ 0x40374000, 0x4000, 3, 0}, //Level 1, IRAM
|
||||
{ 0x40374000, 0x4000, SOC_MEMORY_TYPE_IRAM, 0}, //Level 1, IRAM
|
||||
#endif
|
||||
{ 0x3FC88000, 0x8000, 2, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy
|
||||
{ 0x3FC90000, 0x10000, 2, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCA0000, 0x10000, 2, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCB0000, 0x10000, 2, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCE0000, 0x10000, 1, 0}, //Level 8, IDRAM, can be used as trace memroy, contains stacks used by startup flow, recycled by heap allocator in app_main task
|
||||
{ 0x3FC88000, 0x8000, SOC_MEMORY_TYPE_DIRAM, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy
|
||||
{ 0x3FC90000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCC0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCD0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), SOC_MEMORY_TYPE_DIRAM, 0x403D0000}, //Level 8, IDRAM, can be used as trace memroy,
|
||||
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task
|
||||
#if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB
|
||||
{ 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM
|
||||
{ 0x3FCF0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0}, //Level 9, DRAM
|
||||
#endif
|
||||
#if CONFIG_ESP32S3_DATA_CACHE_16KB
|
||||
{ 0x3C000000, 0x4000, 5, 0},
|
||||
{ 0x3C000000, 0x4000, SOC_MEMORY_TYPE_NODMARAM, 0},
|
||||
#endif
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x600fe000, 0x2000, 6, 0}, //Fast RTC memory
|
||||
{ 0x600fe000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@ -53,14 +53,12 @@ TEST_CASE("realloc move data to a new heap type", "[heap]")
|
||||
// move data from 'a' to IRAM
|
||||
char *b = heap_caps_realloc(a, 64, MALLOC_CAP_EXEC);
|
||||
TEST_ASSERT_NOT_NULL(b);
|
||||
TEST_ASSERT_NOT_EQUAL(a, b);
|
||||
TEST_ASSERT(heap_caps_check_integrity(MALLOC_CAP_INVALID, true));
|
||||
TEST_ASSERT_EQUAL_HEX32_ARRAY(buf, b, 64 / sizeof(uint32_t));
|
||||
|
||||
// Move data back to DRAM
|
||||
char *c = heap_caps_realloc(b, 48, MALLOC_CAP_8BIT);
|
||||
TEST_ASSERT_NOT_NULL(c);
|
||||
TEST_ASSERT_NOT_EQUAL(b, c);
|
||||
TEST_ASSERT(heap_caps_check_integrity(MALLOC_CAP_INVALID, true));
|
||||
TEST_ASSERT_EQUAL_HEX8_ARRAY(buf, c, 48);
|
||||
|
||||
|
||||
@ -175,6 +175,10 @@
|
||||
#define SOC_DIRAM_DRAM_LOW 0x3FCA0000
|
||||
#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
|
||||
|
||||
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
|
||||
|
||||
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
|
||||
#define SOC_DMA_LOW 0x3FC88000
|
||||
#define SOC_DMA_HIGH 0x3FD00000
|
||||
@ -187,8 +191,6 @@
|
||||
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
|
||||
#define SOC_MEM_INTERNAL_LOW 0x3FCA0000
|
||||
#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000
|
||||
#define SOC_MEM_INTERNAL_LOW1 0x4037C000
|
||||
#define SOC_MEM_INTERNAL_HIGH1 0x403C0000
|
||||
|
||||
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
|
||||
|
||||
@ -201,7 +203,8 @@
|
||||
#define SOC_DEBUG_HIGH 0x28000000
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x3fcebf10
|
||||
#define SOC_ROM_STACK_START 0x3fcdeb70
|
||||
#define SOC_ROM_STACK_SIZE 0x2000
|
||||
|
||||
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
|
||||
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
|
||||
|
||||
@ -179,6 +179,10 @@
|
||||
#define SOC_DIRAM_DRAM_LOW 0x3FC80000
|
||||
#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
|
||||
|
||||
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
|
||||
|
||||
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
|
||||
#define SOC_DMA_LOW 0x3FC88000
|
||||
#define SOC_DMA_HIGH 0x3FD00000
|
||||
@ -191,10 +195,6 @@
|
||||
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
|
||||
#define SOC_MEM_INTERNAL_LOW 0x3FC80000
|
||||
#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000
|
||||
#define SOC_MEM_INTERNAL_LOW1 0x40370000
|
||||
#define SOC_MEM_INTERNAL_HIGH1 0x403E0000
|
||||
#define SOC_MEM_INTERNAL_LOW2 0x600FE000
|
||||
#define SOC_MEM_INTERNAL_HIGH2 0x60100000
|
||||
|
||||
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
|
||||
|
||||
@ -207,7 +207,8 @@
|
||||
#define SOC_DEBUG_HIGH 0x28000000
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x3fcebf10
|
||||
#define SOC_ROM_STACK_START 0x3fcde710
|
||||
#define SOC_ROM_STACK_SIZE 0x2000
|
||||
|
||||
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
|
||||
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
|
||||
|
||||
@ -179,6 +179,10 @@
|
||||
#define SOC_DIRAM_DRAM_LOW 0x3FC80000
|
||||
#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
|
||||
|
||||
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
|
||||
|
||||
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
|
||||
#define SOC_DMA_LOW 0x3FC88000
|
||||
#define SOC_DMA_HIGH 0x3FD00000
|
||||
@ -191,10 +195,6 @@
|
||||
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
|
||||
#define SOC_MEM_INTERNAL_LOW 0x3FC80000
|
||||
#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000
|
||||
#define SOC_MEM_INTERNAL_LOW1 0x40370000
|
||||
#define SOC_MEM_INTERNAL_HIGH1 0x403E0000
|
||||
#define SOC_MEM_INTERNAL_LOW2 0x600FE000
|
||||
#define SOC_MEM_INTERNAL_HIGH2 0x60100000
|
||||
|
||||
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
|
||||
|
||||
@ -208,6 +208,7 @@
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x3fcdf120
|
||||
#define SOC_ROM_STACK_SIZE 0x2000
|
||||
|
||||
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
|
||||
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
|
||||
|
||||
@ -181,6 +181,10 @@
|
||||
#define SOC_DIRAM_DRAM_LOW 0x3FFB0000
|
||||
#define SOC_DIRAM_DRAM_HIGH 0x40000000
|
||||
|
||||
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
|
||||
|
||||
// Region of memory accessible via DMA in internal memory. See esp_ptr_dma_capable().
|
||||
#define SOC_DMA_LOW 0x3FFB0000
|
||||
#define SOC_DMA_HIGH 0x40000000
|
||||
|
||||
@ -199,6 +199,10 @@
|
||||
#define SOC_DIRAM_DRAM_LOW 0x3FC88000
|
||||
#define SOC_DIRAM_DRAM_HIGH 0x3FCF0000
|
||||
|
||||
#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
|
||||
|
||||
// Region of memory accessible via DMA in internal memory. See esp_ptr_dma_capable().
|
||||
#define SOC_DMA_LOW 0x3FC88000
|
||||
#define SOC_DMA_HIGH 0x3FD00000
|
||||
@ -218,7 +222,8 @@
|
||||
#define SOC_MEM_INTERNAL_HIGH 0x403E2000
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x3fcebf10
|
||||
#define SOC_ROM_STACK_START 0x3fceb710
|
||||
#define SOC_ROM_STACK_SIZE 0x2000
|
||||
|
||||
//interrupt cpu using table, Please see the core-isa.h
|
||||
/*************************************************************************************************************
|
||||
|
||||
@ -95,9 +95,6 @@ static uint8_t fnc_call0_buff[] = {0xf0, 0x22, 0x11, 0x0d, 0xf0, 0x00, 0x00, 0x0
|
||||
|
||||
volatile bool g_override_illegal_instruction = false;
|
||||
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr - SOC_DIRAM_DRAM_LOW + SOC_DIRAM_IRAM_LOW)
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_DIRAM_IRAM_LOW + SOC_DIRAM_DRAM_LOW)
|
||||
|
||||
#define SRAM_TEST_BUFFER_SIZE 0x400
|
||||
#define SRAM_TEST_OFFSET 0x200
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user