diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index 187784fae6..db743763ae 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -249,6 +249,32 @@ bool pmu_sleep_finish(void); */ void pmu_init(void); +/** + * @brief Initialize PVT related parameters + */ +void pvt_auto_dbias_init(void); + +/** + * @brief Enable or disable PVT functions + */ +void pvt_func_enable(bool enable); + +/** + * @brief Initialize charge pump related parameters + */ +void charge_pump_init(void); + +/** + * @brief Enable or disable charge pump functions + */ +void charge_pump_enable(bool enable); + +/** + * @brief Get Hp_dbias from register + */ +uint32_t get_pvt_dbias(void); + + /** * @brief Enable or disable system clock in PMU HP sleep state * diff --git a/components/esp_hw_support/include/esp_private/esp_regdma.h b/components/esp_hw_support/include/esp_private/esp_regdma.h index ebf7ed423c..7ca796bc16 100644 --- a/components/esp_hw_support/include/esp_private/esp_regdma.h +++ b/components/esp_hw_support/include/esp_private/esp_regdma.h @@ -31,6 +31,7 @@ extern "C" { #define REGDMA_MODEMSYSCON_LINK(_pri) ((0x02 << 8) | _pri) #define REGDMA_MODEMLPCON_LINK(_pri) ((0x03 << 8) | _pri) +#define REGDMA_PVT_LINK(_pri) ((0x0c << 8) | _pri) #define REGDMA_INTMTX_LINK(_pri) ((0x0d << 8) | _pri) #define REGDMA_HPSYS_LINK(_pri) ((0x0e << 8) | _pri) #define REGDMA_TEEAPM_LINK(_pri) ((0x0f << 8) | _pri) diff --git a/components/esp_hw_support/include/esp_private/sleep_retention.h b/components/esp_hw_support/include/esp_private/sleep_retention.h index e64a95a9c0..08b69edb6d 100644 --- a/components/esp_hw_support/include/esp_private/sleep_retention.h +++ b/components/esp_hw_support/include/esp_private/sleep_retention.h @@ -45,6 +45,7 @@ typedef enum sleep_retention_module_bitmap { SLEEP_RETENTION_MODULE_IOMUX = BIT(21), SLEEP_RETENTION_MODULE_SPIMEM = BIT(22), SLEEP_RETENTION_MODULE_SYSTIMER = BIT(23), + SLEEP_RETENTION_MODULE_PVT = BIT(24), SLEEP_RETENTION_MODULE_ALL = (uint32_t)-1 } sleep_retention_module_bitmap_t; diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index 744de22edc..6347fc6b76 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -25,6 +25,10 @@ entries: pmu_sleep (noflash) if PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32 = n: sleep_modem:periph_inform_out_light_sleep_overhead (noflash) + if SOC_PMU_PVT_SUPPORTED = y: + pmu_pvt_pump: pvt_func_enable (noflash) + pmu_pvt_pump: charge_pump_enable (noflash) + pmu_pvt_pump: get_pvt_dbias (noflash) if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y: rtc_wdt (noflash_text) if PERIPH_CTRL_FUNC_IN_IRAM = y: diff --git a/components/esp_hw_support/port/esp32c6/CMakeLists.txt b/components/esp_hw_support/port/esp32c6/CMakeLists.txt index e82e407cb0..ee688dbc14 100644 --- a/components/esp_hw_support/port/esp32c6/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c6/CMakeLists.txt @@ -6,6 +6,7 @@ set(srcs "rtc_clk_init.c" "rtc_time.c" "chip_info.c" "ocode_init.c" + "pmu_pvt_pump.c" ) if(NOT BOOTLOADER_BUILD) diff --git a/components/esp_hw_support/port/esp32c6/pmu_init.c b/components/esp_hw_support/port/esp32c6/pmu_init.c index 8c04486f02..d5ebf98c02 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_init.c +++ b/components/esp_hw_support/port/esp32c6/pmu_init.c @@ -13,6 +13,7 @@ #include "soc/pmu_struct.h" #include "hal/pmu_hal.h" #include "pmu_param.h" +#include "esp_rom_sys.h" #include "esp_private/esp_pmu.h" #include "soc/regi2c_dig_reg.h" #include "regi2c_ctrl.h" @@ -195,8 +196,6 @@ void pmu_init(void) /* Peripheral reg i2c power up */ SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); @@ -204,4 +203,12 @@ void pmu_init(void) pmu_lp_system_init_default(PMU_instance()); pmu_power_domain_force_default(PMU_instance()); + + pvt_auto_dbias_init(); + charge_pump_init(); + + //HP dbias initialization + pvt_func_enable(1); + charge_pump_enable(1); + esp_rom_delay_us(1000); } diff --git a/components/esp_hw_support/port/esp32c6/pmu_param.c b/components/esp_hw_support/port/esp32c6/pmu_param.c index 6e0a8ea8cb..6c8a63af07 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_param.c +++ b/components/esp_hw_support/port/esp32c6/pmu_param.c @@ -211,7 +211,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp .xpd = 1, \ .slp_mem_dbias = 0, \ .slp_logic_dbias = 0, \ - .dbias = 0x19 \ + .dbias = HP_CALI_DBIAS \ }, \ .regulator1 = { \ .drv_b = 0x0 \ @@ -231,7 +231,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp .xpd = 1, \ .slp_mem_dbias = 0, \ .slp_logic_dbias = 0, \ - .dbias = 0x1a \ + .dbias = HP_CALI_DBIAS \ }, \ .regulator1 = { \ .drv_b = 0x0 \ @@ -294,7 +294,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ BIT(PMU_ICG_FUNC_ENA_SPI2) | \ BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ + BIT(PMU_ICG_FUNC_ENA_SYSTIMER) | \ + BIT(PMU_ICG_FUNC_ENA_PVT_MONITOR) \ ) \ } @@ -343,7 +344,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ BIT(PMU_ICG_FUNC_ENA_SPI2) | \ BIT(PMU_ICG_FUNC_ENA_UART0) | \ - BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ + BIT(PMU_ICG_FUNC_ENA_SYSTIMER) | \ + BIT(PMU_ICG_FUNC_ENA_PVT_MONITOR) \ ) \ } diff --git a/components/esp_hw_support/port/esp32c6/pmu_pvt_pump.c b/components/esp_hw_support/port/esp32c6/pmu_pvt_pump.c new file mode 100644 index 0000000000..344027b37b --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/pmu_pvt_pump.c @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "sdkconfig.h" +#include "soc/soc.h" +#include "soc/pvt_reg.h" +#include "soc/pmu_reg.h" +#include "soc/pcr_reg.h" +#include "pmu_param.h" +#include "esp_private/esp_pmu.h" +#include "soc/regi2c_dig_reg.h" +#include "regi2c_ctrl.h" +#include "soc/rtc.h" + +static __attribute__((unused)) const char *TAG = "pmu_pvt_pump"; + +void pvt_auto_dbias_init(void) +{ + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); + /*config for dbias func*/ + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL0_SEL, PVT_CHANNEL0_SEL, PVT_DBIAS_CHANNEL0_SEL_S); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL1_SEL, PVT_CHANNEL1_SEL, PVT_DBIAS_CHANNEL1_SEL_S); // Select monitor cell ,which used to monitor PVT situation + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL0_SEL_REG, PVT_DBIAS_CHANNEL0_CFG, PVT_CHANNEL0_CFG, PVT_DBIAS_CHANNEL0_CFG_S); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL1_SEL_REG, PVT_DBIAS_CHANNEL1_CFG, PVT_CHANNEL1_CFG, PVT_DBIAS_CHANNEL1_CFG_S); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL2_SEL_REG, PVT_DBIAS_CHANNEL2_CFG, PVT_CHANNEL2_CFG, PVT_DBIAS_CHANNEL2_CFG_S); // Configure filter threshold for avoiding auto-dbias overly sensitive regulation + SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0, PVT_CMD0, PVT_DBIAS_CMD0_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1, PVT_CMD1, PVT_DBIAS_CMD1_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2, PVT_CMD2, PVT_DBIAS_CMD2_S); // Configure auto-dbias adjust property, such as adjusting step + SET_PERI_REG_BITS(PVT_DBIAS_TIMER_REG, PVT_TIMER_TARGET, PVT_TARGET, PVT_TIMER_TARGET_S); // Configure auto-dbias voltage regulation cycle + + SET_PERI_REG_BITS(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM, PVT_CLK_DIV, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S); //pvt function clock divider number + + /*config for pvt cell: unit0; site2; vt2*/ + SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_SEL); //pvt function clock source select + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0, PVT_EDG_MODE, PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S); // Select edge_mode + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0, PVT_DELAY_NUM_HIGH, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S); // The threshold for determining whether the voltage is too high + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1, PVT_DELAY_NUM_LOW, PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S); // The threshold for determining whether the voltage is too low +} + +void pvt_func_enable(bool enable) +{ + if (enable) { + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); + CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt + SET_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN); + SET_PERI_REG_MASK(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0); // enable pvt clk + SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias + } else { + uint32_t pvt_cali_dbias = get_pvt_dbias(); // update pvt_cali_dbias + SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V, pvt_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S); + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu + CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); //disable auto dbias + CLEAR_PERI_REG_MASK(PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG, PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0); + CLEAR_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN); + } +} + +void charge_pump_init(void) +{ + /*config for charge pump*/ + SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code + WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, PVT_PUMP_BITMAP); // Select monitor cell for charge pump + SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity +} + +void charge_pump_enable(bool enable) +{ + if (enable) { + SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump + } else { + CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump + } +} + +inline uint32_t get_pvt_dbias() +{ + return REG_GET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL); +} diff --git a/components/esp_hw_support/port/esp32c6/pmu_sleep.c b/components/esp_hw_support/port/esp32c6/pmu_sleep.c index cdeeb43fa9..812cfccc95 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32c6/pmu_sleep.c @@ -208,6 +208,7 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd); pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); + pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(MODEM), get_pvt_dbias()); pmu_ll_lp_set_dbg_atten (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten); pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur); diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c index ed6eb4126f..bdccc8af60 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c @@ -13,6 +13,7 @@ #include "esp32c6/rom/rtc.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" +#include "esp_private/esp_pmu.h" #include "esp_hw_log.h" #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" @@ -184,6 +185,10 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) clk_ll_cpu_set_ls_divider(div); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); esp_rom_set_cpu_ticks_per_us(cpu_freq); +#ifndef BOOTLOADER_BUILD + charge_pump_enable(0); + pvt_func_enable(0); +#endif } static void rtc_clk_cpu_freq_to_8m(void) @@ -192,6 +197,10 @@ static void rtc_clk_cpu_freq_to_8m(void) clk_ll_cpu_set_ls_divider(1); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); esp_rom_set_cpu_ticks_per_us(20); +#ifndef BOOTLOADER_BUILD + charge_pump_enable(0); + pvt_func_enable(0); +#endif } /** @@ -201,6 +210,10 @@ static void rtc_clk_cpu_freq_to_8m(void) */ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) { +#ifndef BOOTLOADER_BUILD + pvt_func_enable(1); + charge_pump_enable(1); +#endif clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c index 0f911ace88..2884550feb 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c @@ -24,6 +24,8 @@ #include "hal/pmu_ll.h" #include "hal/modem_syscon_ll.h" #include "hal/modem_lpcon_ll.h" +#include "soc/pmu_reg.h" +#include "pmu_param.h" static const char *TAG = "rtc_clk_init"; @@ -72,6 +74,10 @@ void rtc_clk_init(rtc_clk_config_t cfg) REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap); REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); + REG_SET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, HP_CALI_DBIAS); + REG_SET_FIELD(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, LP_CALI_DBIAS); clk_ll_rc_fast_tick_conf(); diff --git a/components/esp_hw_support/port/esp32h2/CMakeLists.txt b/components/esp_hw_support/port/esp32h2/CMakeLists.txt index 9c1949a12c..ec54417242 100644 --- a/components/esp_hw_support/port/esp32h2/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32h2/CMakeLists.txt @@ -5,6 +5,7 @@ set(srcs "rtc_clk_init.c" "pmu_sleep.c" "rtc_time.c" "chip_info.c" + "pmu_pvt_pump.c" ) if(NOT BOOTLOADER_BUILD) diff --git a/components/esp_hw_support/port/esp32h2/pmu_init.c b/components/esp_hw_support/port/esp32h2/pmu_init.c index 0548461a2b..d8e247b8d9 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_init.c +++ b/components/esp_hw_support/port/esp32h2/pmu_init.c @@ -13,6 +13,7 @@ #include "soc/pmu_struct.h" #include "hal/pmu_hal.h" #include "pmu_param.h" +#include "esp_rom_sys.h" #include "esp_private/esp_pmu.h" #include "soc/regi2c_pmu.h" #include "soc/regi2c_bias.h" @@ -193,9 +194,6 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx) void pmu_init() { /* No peripheral reg i2c power up required on the target */ - - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0); REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG_SLP, 0); REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG_SLP, 0); REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_REG, 0); @@ -215,4 +213,12 @@ void pmu_init() pmu_lp_system_init_default(PMU_instance()); pmu_power_domain_force_default(PMU_instance()); + + pvt_auto_dbias_init(); + charge_pump_init(); + + //HP dbias initialization + pvt_func_enable(1); + charge_pump_enable(1); + esp_rom_delay_us(1000); } diff --git a/components/esp_hw_support/port/esp32h2/pmu_param.c b/components/esp_hw_support/port/esp32h2/pmu_param.c index 83bf887aa3..10fdceca55 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_param.c +++ b/components/esp_hw_support/port/esp32h2/pmu_param.c @@ -295,7 +295,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m | BIT(PMU_ICG_FUNC_ENA_SEC) \ | BIT(PMU_ICG_FUNC_ENA_PWM) \ | BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - | BIT(PMU_ICG_FUNC_ENA_UART0)), \ + | BIT(PMU_ICG_FUNC_ENA_UART0)) \ + | BIT(PMU_ICG_FUNC_ENA_PVT_MONITOR), \ } #define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \ @@ -342,7 +343,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m | BIT(PMU_ICG_FUNC_ENA_SEC) \ | BIT(PMU_ICG_FUNC_ENA_PWM) \ | BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ - | BIT(PMU_ICG_FUNC_ENA_UART0)), \ + | BIT(PMU_ICG_FUNC_ENA_UART0)) \ + | BIT(PMU_ICG_FUNC_ENA_PVT_MONITOR), \ } const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode) diff --git a/components/esp_hw_support/port/esp32h2/pmu_pvt_pump.c b/components/esp_hw_support/port/esp32h2/pmu_pvt_pump.c new file mode 100644 index 0000000000..7aa1bd03d0 --- /dev/null +++ b/components/esp_hw_support/port/esp32h2/pmu_pvt_pump.c @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "sdkconfig.h" +#include "soc/soc.h" +#include "soc/pvt_reg.h" +#include "soc/pmu_reg.h" +#include "soc/pcr_reg.h" +#include "pmu_param.h" +#include "esp_private/esp_pmu.h" +#include "soc/regi2c_pmu.h" +#include "soc/regi2c_bias.h" +#include "regi2c_ctrl.h" +#include "soc/rtc.h" + +static __attribute__((unused)) const char *TAG = "pmu_pvt_pump"; + +void pvt_auto_dbias_init(void) +{ + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0); + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0); + /*config for dbias func*/ + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL0_SEL, PVT_CHANNEL0_SEL, PVT_DBIAS_CHANNEL0_SEL_S); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL1_SEL, PVT_CHANNEL1_SEL, PVT_DBIAS_CHANNEL1_SEL_S); // Select monitor cell ,which used to monitor PVT situation + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL0_SEL_REG, PVT_DBIAS_CHANNEL0_CFG, PVT_CHANNEL0_CFG, PVT_DBIAS_CHANNEL0_CFG_S); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL1_SEL_REG, PVT_DBIAS_CHANNEL1_CFG, PVT_CHANNEL1_CFG, PVT_DBIAS_CHANNEL1_CFG_S); + SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL2_SEL_REG, PVT_DBIAS_CHANNEL2_CFG, PVT_CHANNEL2_CFG, PVT_DBIAS_CHANNEL2_CFG_S); // Configure filter threshold for avoiding auto-dbias overly sensitive regulation + SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0, PVT_CMD0, PVT_DBIAS_CMD0_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1, PVT_CMD1, PVT_DBIAS_CMD1_S); + SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2, PVT_CMD2, PVT_DBIAS_CMD2_S); // Configure auto-dbias adjust property, such as adjusting step + SET_PERI_REG_BITS(PVT_DBIAS_TIMER_REG, PVT_TIMER_TARGET, PVT_TARGET, PVT_TIMER_TARGET_S); // Configure auto-dbias voltage regulation cycle + + SET_PERI_REG_BITS(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM, PVT_CLK_DIV, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S); //pvt function clock divider number + + /*config for pvt cell: unit0; site2; vt0*/ + SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_SEL); //pvt function clock source select + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG, PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0, PVT_EDG_MODE, PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S); // Select edge_mode + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG, PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0, PVT_DELAY_NUM_HIGH, PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S); // The threshold for determining whether the voltage is too high + SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG, PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1, PVT_DELAY_NUM_LOW, PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S); // The threshold for determining whether the voltage is too low +} + +void pvt_func_enable(bool enable) +{ + if (enable) { + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); + CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt + SET_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN); + SET_PERI_REG_MASK(PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG, PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0); // enable pvt clk + SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias + } else { + uint32_t pvt_cali_dbias = get_pvt_dbias(); // update pvt_cali_dbias + SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V, pvt_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S); + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu + CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); //disable auto dbias + CLEAR_PERI_REG_MASK(PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG, PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0); + CLEAR_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN); + } +} + +void charge_pump_init(void) +{ + /*config for charge pump*/ + SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code + WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, PVT_PUMP_BITMAP); // Select monitor cell for charge pump + SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity +} + +void charge_pump_enable(bool enable) +{ + if (enable) { + SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump + } else { + CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump + } +} + +inline uint32_t get_pvt_dbias() +{ + return REG_GET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL); +} diff --git a/components/esp_hw_support/port/esp32h2/pmu_sleep.c b/components/esp_hw_support/port/esp32h2/pmu_sleep.c index 1f39dd0a7f..c6210b475b 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h2/pmu_sleep.c @@ -164,6 +164,8 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); pmu_ll_hp_set_trx_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd_trx); + pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(MODEM), get_pvt_dbias()); + pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur); pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep); pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_xpd); diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c index ce0a0e260b..7c6720492a 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c @@ -13,6 +13,7 @@ #include "esp32h2/rom/rtc.h" #include "soc/rtc.h" #include "esp_private/rtc_clk.h" +#include "esp_private/esp_pmu.h" #include "esp_hw_log.h" #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" @@ -203,6 +204,10 @@ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); clk_ll_bus_update(); esp_rom_set_cpu_ticks_per_us(cpu_freq); +#ifndef BOOTLOADER_BUILD + charge_pump_enable(0); + pvt_func_enable(0); +#endif } static void rtc_clk_cpu_freq_to_8m(void) @@ -213,6 +218,10 @@ static void rtc_clk_cpu_freq_to_8m(void) clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); clk_ll_bus_update(); esp_rom_set_cpu_ticks_per_us(8); +#ifndef BOOTLOADER_BUILD + charge_pump_enable(0); + pvt_func_enable(0); +#endif } /** @@ -222,6 +231,10 @@ static void rtc_clk_cpu_freq_to_8m(void) */ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) { +#ifndef BOOTLOADER_BUILD + pvt_func_enable(1); + charge_pump_enable(1); +#endif // f_hp_root = 96MHz uint32_t cpu_divider = CLK_LL_PLL_96M_FREQ_MHZ / cpu_freq_mhz; clk_ll_cpu_set_divider(cpu_divider); @@ -241,6 +254,10 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) */ static void rtc_clk_cpu_freq_to_flash_pll(uint32_t cpu_freq_mhz, uint32_t cpu_divider) { +#ifndef BOOTLOADER_BUILD + pvt_func_enable(1); + charge_pump_enable(1); +#endif // f_hp_root = 64MHz clk_ll_cpu_set_divider(cpu_divider); // Constraint: f_ahb <= 32MHz; f_cpu = N * f_ahb (N = 1, 2, 3...) diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c index aaa476e5b6..02d8b9bc4a 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c @@ -20,6 +20,8 @@ #include "sdkconfig.h" #include "esp_rom_uart.h" #include "hal/clk_tree_ll.h" +#include "soc/pmu_reg.h" +#include "pmu_param.h" static const char *TAG = "rtc_clk_init"; @@ -39,6 +41,10 @@ void rtc_clk_init(rtc_clk_config_t cfg) REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq); REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, cfg.slow_clk_dcap); REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq); + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0); + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0); + REG_SET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, HP_CALI_DBIAS); + REG_SET_FIELD(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, LP_CALI_DBIAS); clk_ll_rc_fast_tick_conf(); diff --git a/components/esp_hw_support/sleep_system_peripheral.c b/components/esp_hw_support/sleep_system_peripheral.c index fa48c6692e..74001fbd15 100644 --- a/components/esp_hw_support/sleep_system_peripheral.c +++ b/components/esp_hw_support/sleep_system_peripheral.c @@ -28,6 +28,11 @@ #include "soc/gpio_reg.h" #include "soc/io_mux_reg.h" #include "soc/interrupt_matrix_reg.h" +#if SOC_PMU_PVT_SUPPORTED +#include "soc/pvt_reg.h" +#endif + +#include "hal/mwdt_ll.h" static __attribute__((unused)) const char *TAG = "sleep_sys_periph"; @@ -219,6 +224,30 @@ esp_err_t sleep_sys_periph_systimer_retention_init(void) return ESP_OK; } +#if SOC_PMU_PVT_SUPPORTED +esp_err_t sleep_sys_periph_pvt_retention_init(void) +{ +#if CONFIG_IDF_TARGET_ESP32C6 + #define PVT_RETENTION_REGS_CNT 14 + #define PVT_RETENTION_MAP_BASE PVT_PMUP_BITMAP_LOW0_REG + const static uint32_t pvt_regs_map[4] = {0x139D61, 0x600000, 0x2000000, 0}; +#elif CONFIG_IDF_TARGET_ESP32H2 + #define PVT_RETENTION_REGS_CNT 14 + #define PVT_RETENTION_MAP_BASE PVT_PMUP_BITMAP_LOW0_REG + const static uint32_t pvt_regs_map[4] = {0x139D61, 0x6000, 0x20000, 0}; +#endif + + const static sleep_retention_entries_config_t pvt_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PVT_LINK(0x00), PVT_RETENTION_MAP_BASE, PVT_RETENTION_MAP_BASE, PVT_RETENTION_REGS_CNT, 0, 0, pvt_regs_map[0], pvt_regs_map[1], pvt_regs_map[2], pvt_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) }, + }; + + esp_err_t err = sleep_retention_entries_create(pvt_regs_retention, ARRAY_SIZE(pvt_regs_retention), SLEEP_RETENTION_PERIPHERALS_PRIORITY_DEFAULT, SLEEP_RETENTION_MODULE_PVT); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for digital peripherals (PVT) retention"); + ESP_LOGI(TAG, "PVT sleep retention initialization"); + return ESP_OK; +} +#endif + esp_err_t sleep_sys_periph_retention_init(void) { esp_err_t err; @@ -237,6 +266,11 @@ esp_err_t sleep_sys_periph_retention_init(void) err = sleep_sys_periph_spimem_retention_init(); if(err) goto error; err = sleep_sys_periph_systimer_retention_init(); + if(err) goto error; +#if SOC_PMU_PVT_SUPPORTED + err = sleep_sys_periph_pvt_retention_init(); + if(err) goto error; +#endif error: return err; @@ -246,14 +280,18 @@ bool IRAM_ATTR peripheral_domain_pd_allowed(void) { const uint32_t modules = sleep_retention_get_modules(); const uint32_t mask = (const uint32_t) ( - SLEEP_RETENTION_MODULE_INTR_MATRIX | \ - SLEEP_RETENTION_MODULE_HP_SYSTEM | \ - SLEEP_RETENTION_MODULE_TEE_APM | \ - SLEEP_RETENTION_MODULE_UART0 | \ - SLEEP_RETENTION_MODULE_TG0 | \ - SLEEP_RETENTION_MODULE_IOMUX | \ - SLEEP_RETENTION_MODULE_SPIMEM | \ - SLEEP_RETENTION_MODULE_SYSTIMER); + SLEEP_RETENTION_MODULE_INTR_MATRIX | + SLEEP_RETENTION_MODULE_HP_SYSTEM | + SLEEP_RETENTION_MODULE_TEE_APM | + SLEEP_RETENTION_MODULE_UART0 | + SLEEP_RETENTION_MODULE_TG0 | + SLEEP_RETENTION_MODULE_IOMUX | + SLEEP_RETENTION_MODULE_SPIMEM | + SLEEP_RETENTION_MODULE_SYSTIMER | +#if SOC_PMU_PVT_SUPPORTED + SLEEP_RETENTION_MODULE_PVT | +#endif + 0); return ((modules & mask) == mask); } diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 6226f91bee..1b670b8cff 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -171,6 +171,10 @@ config SOC_PMU_SUPPORTED bool default y +config SOC_PMU_PVT_SUPPORTED + bool + default y + config SOC_PAU_SUPPORTED bool default y diff --git a/components/soc/esp32c6/include/soc/pvt_reg.h b/components/soc/esp32c6/include/soc/pvt_reg.h new file mode 100644 index 0000000000..138d1230c1 --- /dev/null +++ b/components/soc/esp32c6/include/soc/pvt_reg.h @@ -0,0 +1,876 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define PVT_PMUP_BITMAP_HIGH0_REG (DR_REG_PVT_MONITOR_BASE + 0x0000) +#define PVT_PUMP_BITMAP_HIGH0 0xFFFFFFFF +#define PVT_PUMP_BITMAP_HIGH0_S 0 + +#define PVT_PMUP_BITMAP_HIGH1_REG (DR_REG_PVT_MONITOR_BASE + 0x0004) +#define PVT_PUMP_BITMAP_HIGH1 0xFFFFFFFF +#define PVT_PUMP_BITMAP_HIGH1_S 0 + +#define PVT_PMUP_BITMAP_HIGH2_REG (DR_REG_PVT_MONITOR_BASE + 0x0008) +#define PVT_PUMP_BITMAP_HIGH2 0xFFFFFFFF +#define PVT_PUMP_BITMAP_HIGH2_S 0 + +#define PVT_PMUP_BITMAP_HIGH3_REG (DR_REG_PVT_MONITOR_BASE + 0x000C) +#define PVT_PUMP_BITMAP_HIGH3 0xFFFFFFFF +#define PVT_PUMP_BITMAP_HIGH3_S 0 + +#define PVT_PMUP_BITMAP_HIGH4_REG (DR_REG_PVT_MONITOR_BASE + 0x0010) +#define PVT_PUMP_BITMAP_HIGH4 0xFFFFFFFF +#define PVT_PUMP_BITMAP_HIGH4_S 0 + +#define PVT_PMUP_BITMAP_LOW0_REG (DR_REG_PVT_MONITOR_BASE + 0x0014) +#define PVT_PUMP_BITMAP_LOW0 0xFFFFFFFF +#define PVT_PUMP_BITMAP_LOW0_S 0 + +#define PVT_PMUP_BITMAP_LOW1_REG (DR_REG_PVT_MONITOR_BASE + 0x0018) +#define PVT_PUMP_BITMAP_LOW1 0xFFFFFFFF +#define PVT_PUMP_BITMAP_LOW1_S 0 + +#define PVT_PMUP_BITMAP_LOW2_REG (DR_REG_PVT_MONITOR_BASE + 0x001C) +#define PVT_PUMP_BITMAP_LOW2 0xFFFFFFFF +#define PVT_PUMP_BITMAP_LOW2_S 0 + +#define PVT_PMUP_BITMAP_LOW3_REG (DR_REG_PVT_MONITOR_BASE + 0x0020) +#define PVT_PUMP_BITMAP_LOW3 0xFFFFFFFF +#define PVT_PUMP_BITMAP_LOW3_S 0 + +#define PVT_PMUP_BITMAP_LOW4_REG (DR_REG_PVT_MONITOR_BASE + 0x0024) +#define PVT_PUMP_BITMAP_LOW4 0xFFFFFFFF +#define PVT_PUMP_BITMAP_LOW4_S 0 + +#define PVT_PMUP_DRV_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x0028) +#define PVT_PUMP_DRV0 0x0000000F +#define PVT_PUMP_DRV0_S 27 +#define PVT_PUMP_DRV1 0x0000000F +#define PVT_PUMP_DRV1_S 23 +#define PVT_PUMP_DRV2 0x0000000F +#define PVT_PUMP_DRV2_S 19 +#define PVT_PUMP_DRV3 0x0000000F +#define PVT_PUMP_DRV3_S 15 +#define PVT_PUMP_DRV4 0x0000000F +#define PVT_PUMP_DRV4_S 11 +#define PVT_CLK_EN (BIT(10)) +#define PVT_CLK_EN_S 10 +#define PVT_PUMP_EN (BIT(9)) +#define PVT_PUMP_EN_S 9 + +#define PVT_PMUP_CHANNEL_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x002C) +#define PVT_PUMP_CHANNEL_CODE0 0x0000001F +#define PVT_PUMP_CHANNEL_CODE0_S 27 +#define PVT_PUMP_CHANNEL_CODE1 0x0000001F +#define PVT_PUMP_CHANNEL_CODE1_S 22 +#define PVT_PUMP_CHANNEL_CODE2 0x0000001F +#define PVT_PUMP_CHANNEL_CODE2_S 17 +#define PVT_PUMP_CHANNEL_CODE3 0x0000001F +#define PVT_PUMP_CHANNEL_CODE3_S 12 +#define PVT_PUMP_CHANNEL_CODE4 0x0000001F +#define PVT_PUMP_CHANNEL_CODE4_S 7 + +#define PVT_CLK_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x0030) +#define PVT_CLK_SEL (BIT(31)) +#define PVT_CLK_SEL_S 31 +#define PVT_MONITOR_CLK_PVT_EN (BIT(8)) +#define PVT_MONITOR_CLK_PVT_EN_S 8 +#define PVT_PUMP_CLK_DIV_NUM 0x000000FF +#define PVT_PUMP_CLK_DIV_NUM_S 0 + +#define PVT_DBIAS_CHANNEL_SEL0_REG (DR_REG_PVT_MONITOR_BASE + 0x0034) +#define PVT_DBIAS_CHANNEL0_SEL 0x0000007F +#define PVT_DBIAS_CHANNEL0_SEL_S 25 +#define PVT_DBIAS_CHANNEL1_SEL 0x0000007F +#define PVT_DBIAS_CHANNEL1_SEL_S 18 +#define PVT_DBIAS_CHANNEL2_SEL 0x0000007F +#define PVT_DBIAS_CHANNEL2_SEL_S 11 +#define PVT_DBIAS_CHANNEL3_SEL 0x0000007F +#define PVT_DBIAS_CHANNEL3_SEL_S 4 + +#define PVT_DBIAS_CHANNEL_SEL1_REG (DR_REG_PVT_MONITOR_BASE + 0x0038) +#define PVT_DBIAS_CHANNEL4_SEL 0x0000007F +#define PVT_DBIAS_CHANNEL4_SEL_S 25 + +#define PVT_DBIAS_CHANNEL0_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x003C) +#define PVT_DBIAS_CHANNEL0_CFG 0x0001FFFF +#define PVT_DBIAS_CHANNEL0_CFG_S 0 + +#define PVT_DBIAS_CHANNEL1_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x0040) +#define PVT_DBIAS_CHANNEL1_CFG 0x0001FFFF +#define PVT_DBIAS_CHANNEL1_CFG_S 0 + +#define PVT_DBIAS_CHANNEL2_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x0044) +#define PVT_DBIAS_CHANNEL2_CFG 0x0001FFFF +#define PVT_DBIAS_CHANNEL2_CFG_S 0 + +#define PVT_DBIAS_CHANNEL3_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x0048) +#define PVT_DBIAS_CHANNEL3_CFG 0x0001FFFF +#define PVT_DBIAS_CHANNEL3_CFG_S 0 + +#define PVT_DBIAS_CHANNEL4_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x004C) +#define PVT_DBIAS_CHANNEL4_CFG 0x0001FFFF +#define PVT_DBIAS_CHANNEL4_CFG_S 0 + +#define PVT_DBIAS_CMD0_REG (DR_REG_PVT_MONITOR_BASE + 0x0050) +#define PVT_DBIAS_CMD0 0x0001FFFF +#define PVT_DBIAS_CMD0_S 0 + +#define PVT_DBIAS_CMD1_REG (DR_REG_PVT_MONITOR_BASE + 0x0054) +#define PVT_DBIAS_CMD1 0x0001FFFF +#define PVT_DBIAS_CMD1_S 0 + +#define PVT_DBIAS_CMD2_REG (DR_REG_PVT_MONITOR_BASE + 0x0058) +#define PVT_DBIAS_CMD2 0x0001FFFF +#define PVT_DBIAS_CMD2_S 0 + +#define PVT_DBIAS_CMD3_REG (DR_REG_PVT_MONITOR_BASE + 0x005C) +#define PVT_DBIAS_CMD3 0x0001FFFF +#define PVT_DBIAS_CMD3_S 0 + +#define PVT_DBIAS_CMD4_REG (DR_REG_PVT_MONITOR_BASE + 0x0060) +#define PVT_DBIAS_CMD4 0x0001FFFF +#define PVT_DBIAS_CMD4_S 0 + +#define PVT_DBIAS_TIMER_REG (DR_REG_PVT_MONITOR_BASE + 0x0064) +#define PVT_TIMER_EN (BIT(31)) +#define PVT_TIMER_EN_S 31 +#define PVT_TIMER_TARGET 0x0000FFFF +#define PVT_TIMER_TARGET_S 15 + +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0068) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x006C) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0070) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0074) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0078) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x007C) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0080) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0084) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0088) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x008C) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0090) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0094) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0098) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x009C) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00A0) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00A4) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00A8) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00AC) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00B0) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00B4) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00B8) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00BC) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00C0) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00C4) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00C8) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00CC) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00D0) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00D4) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 0x000000FF +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 0x000000FF +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00D8) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00DC) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00E0) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00E4) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 0x000000FF +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 0x000000FF +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00E8) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00EC) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00F0) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00F4) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 0x000000FF +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 0x000000FF +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x00F8) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x00FC) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0100) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0104) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0108) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x010C) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0110) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0114) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0118) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x011C) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0120) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0124) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0128) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x012C) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0130) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0134) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0138) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x013C) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0140) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0144) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0148) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x014C) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0150) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0154) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0158) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x015C) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0160) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0164) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0168) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x016C) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0170) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0174) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0178) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x017C) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0180) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0184) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 0x0000FFFF +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S 0 + +#define PVT_DATE_REG (DR_REG_PVT_MONITOR_BASE + 0xFFC) +#define PVT_DATE 0xFFFFFFFF +#define PVT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/rtc.h b/components/soc/esp32c6/include/soc/rtc.h index f34531218a..828f9f192e 100644 --- a/components/soc/esp32c6/include/soc/rtc.h +++ b/components/soc/esp32c6/include/soc/rtc.h @@ -117,6 +117,26 @@ set sleep_init default param #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 +/* +set pvt default param +*/ +#define PVT_CHANNEL0_SEL 34 +#define PVT_CHANNEL1_SEL 38 +#define PVT_CHANNEL0_CFG 0x1033e +#define PVT_CHANNEL1_CFG 0x1033e +#define PVT_CHANNEL2_CFG 0x10000 +#define PVT_CMD0 0x24 +#define PVT_CMD1 0x5 +#define PVT_CMD2 0x427 +#define PVT_TARGET 0x1f40 +#define PVT_CLK_DIV 1 +#define PVT_EDG_MODE 1 +#define PVT_DELAY_NUM_HIGH 108 +#define PVT_DELAY_NUM_LOW 98 +#define PVT_PUMP_CHANNEL_CODE 1 +#define PVT_PUMP_BITMAP 512 +#define PVT_PUMP_DRV 0 + /* The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value storing in efuse (based on ATE 5k ECO3 chips) diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index acda16e32d..ff6484bbb2 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -67,6 +67,7 @@ #define SOC_BOD_SUPPORTED 1 #define SOC_APM_SUPPORTED 1 #define SOC_PMU_SUPPORTED 1 +#define SOC_PMU_PVT_SUPPORTED 1 #define SOC_PAU_SUPPORTED 1 #define SOC_LP_TIMER_SUPPORTED 1 #define SOC_LP_AON_SUPPORTED 1 diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index cc4654abc6..f2c8a08aba 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -167,6 +167,10 @@ config SOC_PMU_SUPPORTED bool default y +config SOC_PMU_PVT_SUPPORTED + bool + default y + config SOC_LP_TIMER_SUPPORTED bool default y diff --git a/components/soc/esp32h2/include/soc/pvt_reg.h b/components/soc/esp32h2/include/soc/pvt_reg.h new file mode 100644 index 0000000000..732eb501fe --- /dev/null +++ b/components/soc/esp32h2/include/soc/pvt_reg.h @@ -0,0 +1,881 @@ +/** + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef PVT_REG_H +#define PVT_REG_H + +#define PVT_PMUP_BITMAP_HIGH0_REG (DR_REG_PVT_MONITOR_BASE + 0x0000) +#define PVT_PUMP_BITMAP_HIGH0 0xffffffff +#define PVT_PUMP_BITMAP_HIGH0_S 0 + +#define PVT_PMUP_BITMAP_HIGH1_REG (DR_REG_PVT_MONITOR_BASE + 0x0004) +#define PVT_PUMP_BITMAP_HIGH1 0xffffffff +#define PVT_PUMP_BITMAP_HIGH1_S 0 + +#define PVT_PMUP_BITMAP_HIGH2_REG (DR_REG_PVT_MONITOR_BASE + 0x0008) +#define PVT_PUMP_BITMAP_HIGH2 0xffffffff +#define PVT_PUMP_BITMAP_HIGH2_S 0 + +#define PVT_PMUP_BITMAP_HIGH3_REG (DR_REG_PVT_MONITOR_BASE + 0x000C) +#define PVT_PUMP_BITMAP_HIGH3 0xffffffff +#define PVT_PUMP_BITMAP_HIGH3_S 0 + +#define PVT_PMUP_BITMAP_HIGH4_REG (DR_REG_PVT_MONITOR_BASE + 0x0010) +#define PVT_PUMP_BITMAP_HIGH4 0xffffffff +#define PVT_PUMP_BITMAP_HIGH4_S 0 + +#define PVT_PMUP_BITMAP_LOW0_REG (DR_REG_PVT_MONITOR_BASE + 0x0014) +#define PVT_PUMP_BITMAP_LOW0 0xffffffff +#define PVT_PUMP_BITMAP_LOW0_S 0 + +#define PVT_PMUP_BITMAP_LOW1_REG (DR_REG_PVT_MONITOR_BASE + 0x0018) +#define PVT_PUMP_BITMAP_LOW1 0xffffffff +#define PVT_PUMP_BITMAP_LOW1_S 0 + +#define PVT_PMUP_BITMAP_LOW2_REG (DR_REG_PVT_MONITOR_BASE + 0x001C) +#define PVT_PUMP_BITMAP_LOW2 0xffffffff +#define PVT_PUMP_BITMAP_LOW2_S 0 + +#define PVT_PMUP_BITMAP_LOW3_REG (DR_REG_PVT_MONITOR_BASE + 0x0020) +#define PVT_PUMP_BITMAP_LOW3 0xffffffff +#define PVT_PUMP_BITMAP_LOW3_S 0 + +#define PVT_PMUP_BITMAP_LOW4_REG (DR_REG_PVT_MONITOR_BASE + 0x0024) +#define PVT_PUMP_BITMAP_LOW4 0xffffffff +#define PVT_PUMP_BITMAP_LOW4_S 0 + +#define PVT_PMUP_DRV_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x0028) +#define PVT_PUMP_DRV0 0x0000000f +#define PVT_PUMP_DRV0_S 27 +#define PVT_PUMP_DRV1 0x0000000f +#define PVT_PUMP_DRV1_S 23 +#define PVT_PUMP_DRV2 0x0000000f +#define PVT_PUMP_DRV2_S 19 +#define PVT_PUMP_DRV3 0x0000000f +#define PVT_PUMP_DRV3_S 15 +#define PVT_PUMP_DRV4 0x0000000f +#define PVT_PUMP_DRV4_S 11 +#define PVT_CLK_EN 0x00000400 +#define PVT_CLK_EN_S 10 +#define PVT_PUMP_EN 0x00000200 +#define PVT_PUMP_EN_S 9 + +#define PVT_PMUP_CHANNEL_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x002C) +#define PVT_PUMP_CHANNEL_CODE0 0x0000001f +#define PVT_PUMP_CHANNEL_CODE0_S 27 +#define PVT_PUMP_CHANNEL_CODE1 0x0000001f +#define PVT_PUMP_CHANNEL_CODE1_S 22 +#define PVT_PUMP_CHANNEL_CODE2 0x0000001f +#define PVT_PUMP_CHANNEL_CODE2_S 17 +#define PVT_PUMP_CHANNEL_CODE3 0x0000001f +#define PVT_PUMP_CHANNEL_CODE3_S 12 +#define PVT_PUMP_CHANNEL_CODE4 0x0000001f +#define PVT_PUMP_CHANNEL_CODE4_S 7 + +#define PVT_CLK_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x0030) +#define PVT_CLK_SEL 0x80000000 +#define PVT_CLK_SEL_S 31 +#define PVT_MONITOR_CLK_PVT_EN 0x00000100 +#define PVT_MONITOR_CLK_PVT_EN_S 8 +#define PVT_PUMP_CLK_DIV_NUM 0x000000ff +#define PVT_PUMP_CLK_DIV_NUM_S 0 + +#define PVT_DBIAS_CHANNEL_SEL0_REG (DR_REG_PVT_MONITOR_BASE + 0x0034) +#define PVT_DBIAS_CHANNEL0_SEL 0x0000007f +#define PVT_DBIAS_CHANNEL0_SEL_S 25 +#define PVT_DBIAS_CHANNEL1_SEL 0x0000007f +#define PVT_DBIAS_CHANNEL1_SEL_S 18 +#define PVT_DBIAS_CHANNEL2_SEL 0x0000007f +#define PVT_DBIAS_CHANNEL2_SEL_S 11 +#define PVT_DBIAS_CHANNEL3_SEL 0x0000007f +#define PVT_DBIAS_CHANNEL3_SEL_S 4 + +#define PVT_DBIAS_CHANNEL_SEL1_REG (DR_REG_PVT_MONITOR_BASE + 0x0038) +#define PVT_DBIAS_CHANNEL4_SEL 0x0000007f +#define PVT_DBIAS_CHANNEL4_SEL_S 25 + +#define PVT_DBIAS_CHANNEL0_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x003C) +#define PVT_DBIAS_CHANNEL0_CFG 0x0001ffff +#define PVT_DBIAS_CHANNEL0_CFG_S 0 + +#define PVT_DBIAS_CHANNEL1_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x0040) +#define PVT_DBIAS_CHANNEL1_CFG 0x0001ffff +#define PVT_DBIAS_CHANNEL1_CFG_S 0 + +#define PVT_DBIAS_CHANNEL2_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x0044) +#define PVT_DBIAS_CHANNEL2_CFG 0x0001ffff +#define PVT_DBIAS_CHANNEL2_CFG_S 0 + +#define PVT_DBIAS_CHANNEL3_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x0048) +#define PVT_DBIAS_CHANNEL3_CFG 0x0001ffff +#define PVT_DBIAS_CHANNEL3_CFG_S 0 + +#define PVT_DBIAS_CHANNEL4_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x004C) +#define PVT_DBIAS_CHANNEL4_CFG 0x0001ffff +#define PVT_DBIAS_CHANNEL4_CFG_S 0 + +#define PVT_DBIAS_CMD0_REG (DR_REG_PVT_MONITOR_BASE + 0x0050) +#define PVT_DBIAS_CMD0 0x0001ffff +#define PVT_DBIAS_CMD0_S 0 + +#define PVT_DBIAS_CMD1_REG (DR_REG_PVT_MONITOR_BASE + 0x0054) +#define PVT_DBIAS_CMD1 0x0001ffff +#define PVT_DBIAS_CMD1_S 0 + +#define PVT_DBIAS_CMD2_REG (DR_REG_PVT_MONITOR_BASE + 0x0058) +#define PVT_DBIAS_CMD2 0x0001ffff +#define PVT_DBIAS_CMD2_S 0 + +#define PVT_DBIAS_CMD3_REG (DR_REG_PVT_MONITOR_BASE + 0x005C) +#define PVT_DBIAS_CMD3 0x0001ffff +#define PVT_DBIAS_CMD3_S 0 + +#define PVT_DBIAS_CMD4_REG (DR_REG_PVT_MONITOR_BASE + 0x0060) +#define PVT_DBIAS_CMD4 0x0001ffff +#define PVT_DBIAS_CMD4_S 0 + +#define PVT_DBIAS_TIMER_REG (DR_REG_PVT_MONITOR_BASE + 0x0064) +#define PVT_TIMER_EN 0x80000000 +#define PVT_TIMER_EN_S 31 +#define PVT_TIMER_TARGET 0x0000ffff +#define PVT_TIMER_TARGET_S 15 + +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0068) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x006C) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0070) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0074) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0078) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x007C) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0080) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0084) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0088) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x008C) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0090) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0094) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0098) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x009C) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00A0) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00A4) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00A8) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00AC) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00B0) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00B4) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00B8) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00BC) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00C0) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00C4) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00C8) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00CC) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00D0) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00D4) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 0x80000000 +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 0x000000ff +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 0x000000ff +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S 1 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 0x00000001 +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00D8) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00DC) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00E0) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00E4) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 0x80000000 +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 0x000000ff +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 0x000000ff +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S 1 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 0x00000001 +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00E8) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00EC) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00F0) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00F4) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 0x80000000 +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S 31 +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 0x000000ff +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S 23 +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 0x000000ff +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S 2 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 0x00000002 +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S 1 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 0x00000001 +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x00F8) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x00FC) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0100) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0104) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0108) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x010C) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0110) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0114) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0118) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S 0 + +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x011C) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S 0 + +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0120) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S 0 + +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0124) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0128) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x012C) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0130) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0134) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0138) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x013C) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0140) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0144) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0148) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S 0 + +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x014C) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S 0 + +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0150) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S 0 + +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0154) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0158) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x015C) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0160) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0164) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S 16 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 0x00008000 +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0168) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x016C) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0170) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0174) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S 16 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 0x00008000 +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S 0 + +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0178) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S 0 + +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x017C) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S 0 + +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0180) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S 0 + +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0184) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 0x0000ffff +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S 16 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 0x00008000 +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S 15 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 0x00000003 +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S 0 + +#define PVT_DATE_REG (DR_REG_PVT_MONITOR_BASE + 0xFFC) +#define PVT_DATE 0xffffffff +#define PVT_DATE_S 0 + +#endif//PVT_REG_H + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h index 1730c29980..10cc5a598d 100644 --- a/components/soc/esp32h2/include/soc/rtc.h +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -120,6 +120,26 @@ set sleep_init default param #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 +/* +set pvt default param +*/ +#define PVT_CHANNEL0_SEL 32 +#define PVT_CHANNEL1_SEL 36 +#define PVT_CHANNEL0_CFG 0x1033e +#define PVT_CHANNEL1_CFG 0x1033e +#define PVT_CHANNEL2_CFG 0x10000 +#define PVT_CMD0 0x24 +#define PVT_CMD1 0x5 +#define PVT_CMD2 0x427 +#define PVT_TARGET 0x1f40 +#define PVT_CLK_DIV 1 +#define PVT_EDG_MODE 1 +#define PVT_DELAY_NUM_HIGH 108 +#define PVT_DELAY_NUM_LOW 97 +#define PVT_PUMP_CHANNEL_CODE 1 +#define PVT_PUMP_BITMAP 512 +#define PVT_PUMP_DRV 0 + /* The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value storing in efuse (based on ATE 5k ECO3 chips) diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 6d7e5d9d53..df23f1f34d 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -137,7 +137,7 @@ #define APB_CLK_FREQ_ROM ( 32*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM #define EFUSE_CLK_FREQ_ROM ( 20*1000000) -#define CPU_CLK_FREQ_MHZ_BTLD (96) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration +#define CPU_CLK_FREQ_MHZ_BTLD (64) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 32*1000000 ) #define MODEM_APB_CLK_FREQ ( 32*1000000 ) diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 2b3b27ac2c..174bd84773 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -67,6 +67,7 @@ #define SOC_BOD_SUPPORTED 1 #define SOC_APM_SUPPORTED 1 #define SOC_PMU_SUPPORTED 1 +#define SOC_PMU_PVT_SUPPORTED 1 #define SOC_LP_TIMER_SUPPORTED 1 #define SOC_LP_AON_SUPPORTED 1 #define SOC_PAU_SUPPORTED 1