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refactor(lp_ana_periph): sync the reg names to TRM (part2)
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1bab9da223
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@ -755,10 +755,10 @@ static inline void touch_ll_filter_enable(bool enable)
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*/
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static inline void touch_ll_force_update_benchmark(uint32_t benchmark)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_ANA_PERI.touch_filter3, touch_baseline_sw, benchmark);
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LP_ANA_PERI.touch_filter3.touch_update_baseline_sw = 1;
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_ANA_PERI.touch_filter3, touch_benchmark_sw, benchmark);
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LP_ANA_PERI.touch_filter3.touch_update_benchmark_sw = 1;
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// waiting for update
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while (LP_ANA_PERI.touch_filter3.touch_update_baseline_sw);
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while (LP_ANA_PERI.touch_filter3.touch_update_benchmark_sw);
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}
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/************************ Waterproof register setting ************************/
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@ -619,13 +619,13 @@ extern "C" {
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* need_des
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*/
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#define LP_ANALOG_PERI_TOUCH_FILTER1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x110)
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/** LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN : R/W; bitpos: [0]; default: 0;
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/** LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN : R/W; bitpos: [0]; default: 0;
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* Reserved
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*/
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#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN (BIT(0))
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#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_M (LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_V << LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_S)
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#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_V 0x00000001U
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#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_S 0
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#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN (BIT(0))
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#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_M (LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_V << LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_S)
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#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_V 0x00000001U
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#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_S 0
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/** LP_ANALOG_PERI_TOUCH_HYSTERESIS : R/W; bitpos: [2:1]; default: 0;
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* need_des
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*/
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@ -727,20 +727,20 @@ extern "C" {
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* need_des
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*/
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#define LP_ANALOG_PERI_TOUCH_FILTER3_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x118)
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/** LP_ANALOG_PERI_TOUCH_BASELINE_SW : R/W; bitpos: [15:0]; default: 0;
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/** LP_ANALOG_PERI_TOUCH_BENCHMARK_SW : R/W; bitpos: [15:0]; default: 0;
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* need_des
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*/
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#define LP_ANALOG_PERI_TOUCH_BASELINE_SW 0x0000FFFFU
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#define LP_ANALOG_PERI_TOUCH_BASELINE_SW_M (LP_ANALOG_PERI_TOUCH_BASELINE_SW_V << LP_ANALOG_PERI_TOUCH_BASELINE_SW_S)
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#define LP_ANALOG_PERI_TOUCH_BASELINE_SW_V 0x0000FFFFU
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#define LP_ANALOG_PERI_TOUCH_BASELINE_SW_S 0
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/** LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW : WT; bitpos: [16]; default: 0;
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#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW 0x0000FFFFU
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#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_M (LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_V << LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_S)
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#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_V 0x0000FFFFU
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#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_S 0
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/** LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW : WT; bitpos: [16]; default: 0;
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* need_des
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*/
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#define LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW (BIT(16))
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#define LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_M (LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_V << LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_S)
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#define LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_V 0x00000001U
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#define LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_S 16
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#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW (BIT(16))
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#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_M (LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_V << LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_S)
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#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_V 0x00000001U
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#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_S 16
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/** LP_ANALOG_PERI_TOUCH_SLP0_REG register
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* need_des
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@ -510,10 +510,10 @@ typedef union {
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*/
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typedef union {
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struct {
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/** touch_nn_disupdate_baseline_en : R/W; bitpos: [0]; default: 0;
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/** touch_nn_disupdate_benchmark_en : R/W; bitpos: [0]; default: 0;
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* Reserved
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*/
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uint32_t touch_nn_disupdate_baseline_en:1;
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uint32_t touch_nn_disupdate_benchmark_en:1;
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/** touch_hysteresis : R/W; bitpos: [2:1]; default: 0;
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* need_des
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*/
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@ -585,14 +585,14 @@ typedef union {
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*/
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typedef union {
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struct {
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/** touch_baseline_sw : R/W; bitpos: [15:0]; default: 0;
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/** touch_benchmark_sw : R/W; bitpos: [15:0]; default: 0;
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* need_des
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*/
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uint32_t touch_baseline_sw:16;
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/** touch_update_baseline_sw : WT; bitpos: [16]; default: 0;
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uint32_t touch_benchmark_sw:16;
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/** touch_update_benchmark_sw : WT; bitpos: [16]; default: 0;
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* need_des
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*/
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uint32_t touch_update_baseline_sw:1;
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uint32_t touch_update_benchmark_sw:1;
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uint32_t reserved_17:15;
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};
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uint32_t val;
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@ -750,7 +750,7 @@ typedef union {
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/** touch_data_sel : R/W; bitpos: [9:8]; default: 0;
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* The type of the output data for debugging
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* 0/1: raw data
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* 2: baseline
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* 2: benchmark
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* 3: smooth data
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*/
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uint32_t touch_data_sel:2;
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@ -1,16 +1,8 @@
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// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_SENS_REG_H_
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#define _SOC_SENS_REG_H_
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@ -602,7 +594,7 @@ extern "C" {
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#define SENS_TOUCH_DENOISE_END_V 0x1
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#define SENS_TOUCH_DENOISE_END_S 18
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/* SENS_TOUCH_DATA_SEL : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
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/*description: 3: smooth data 2: baseline 1,0: raw_data.*/
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/*description: 3: smooth data 2: benchmark 1,0: raw_data.*/
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#define SENS_TOUCH_DATA_SEL 0x00000003
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#define SENS_TOUCH_DATA_SEL_M ((SENS_TOUCH_DATA_SEL_V)<<(SENS_TOUCH_DATA_SEL_S))
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#define SENS_TOUCH_DATA_SEL_V 0x3
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@ -1378,8 +1370,8 @@ extern "C" {
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#define SENS_SAR_HALL_CTRL_REG (DR_REG_SENS_BASE + 0xFC)
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/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[31] ;default: 1'b1 ; */
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/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-cop
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rocessor.*/
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/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in
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ULP-coprocessor.*/
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#define SENS_HALL_PHASE_FORCE (BIT(31))
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#define SENS_HALL_PHASE_FORCE_M (BIT(31))
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#define SENS_HALL_PHASE_FORCE_V 0x1
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@ -217,7 +217,7 @@ typedef volatile struct sens_dev_s {
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struct {
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uint32_t touch_outen : 15; /*touch controller output enable*/
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uint32_t touch_status_clr : 1; /*clear all touch active status*/
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uint32_t touch_data_sel : 2; /*3: smooth data 2: baseline 1,0: raw_data*/
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uint32_t touch_data_sel : 2; /*3: smooth data 2: benchmark 1,0: raw_data*/
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uint32_t touch_denoise_end : 1; /*touch_denoise_done*/
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uint32_t touch_unit_end : 1; /*touch_unit_done*/
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uint32_t touch_approach_pad2 : 4; /*indicate which pad is approach pad2*/
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@ -443,7 +443,7 @@ The Touch Element Wakeup example is available in `system/light_sleep` directory.
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// ESP_ERROR_CHECK(touch_element_enable_light_sleep(&sleep_config));
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ESP_ERROR_CHECK(touch_element_enable_deep_sleep(button_handle[0], &sleep_config));
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// ESP_ERROR_CHECK(touch_element_sleep_enable_wakeup_calibration(button_handle[0], false)); // (optional) Disable wakeup calibration to prevent updating the baseline to a wrong value
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// ESP_ERROR_CHECK(touch_element_sleep_enable_wakeup_calibration(button_handle[0], false)); // (optional) Disable wakeup calibration to prevent updating the benchmark to a wrong value
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touch_element_start();
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@ -687,7 +687,6 @@ components/soc/esp32s3/include/soc/rtc_io_reg.h
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components/soc/esp32s3/include/soc/rtc_io_struct.h
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components/soc/esp32s3/include/soc/sdmmc_pins.h
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components/soc/esp32s3/include/soc/sdmmc_reg.h
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components/soc/esp32s3/include/soc/sens_reg.h
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components/soc/esp32s3/include/soc/sensitive_reg.h
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components/soc/esp32s3/include/soc/sensitive_struct.h
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components/soc/esp32s3/include/soc/soc_ulp.h
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