mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
gpio:support gpio in/out/interrupt for esp32s3(728)
Add support of gpio for esp32s3(728). Adjust some pins and comments in test_gpio.c. Add support for gpio functions for gpio19 and gpio20. Update S3 programming guide Peripheral API: gpio and sigmadelta. Add unit test for input and output function of S3 USB pins(GPIO19 and GPIO20) and C3 USB pins(GPIO18 and GPIO19). Adjust input only test in test_spi_master.c.
This commit is contained in:
bizhuangyang
parent
afc2bc94b3
commit
78c67d2384
@ -30,6 +30,8 @@
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#define TEST_GPIO_OUTPUT_PIN 23
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#define TEST_GPIO_INPUT_ONLY_PIN 34
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#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_34
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#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 2
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#define TEST_GPIO_INPUT_LEVEL_LOW_PIN 4
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#elif CONFIG_IDF_TARGET_ESP32S2
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// ESP32_S2 DEVKIC uses IO19 and IO20 as USB functions, so it is necessary to avoid using IO19, otherwise GPIO io pull up/down function cannot pass
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// Also the first version of ESP32-S2-Saola has pullup issue on GPIO18, which is tied to 3V3 on the
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@ -39,20 +41,32 @@
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#define TEST_GPIO_OUTPUT_PIN 12
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#define TEST_GPIO_INPUT_ONLY_PIN 46
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#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_46
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#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 17
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#define TEST_GPIO_INPUT_LEVEL_LOW_PIN 1
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#elif CONFIG_IDF_TARGET_ESP32S3
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// IO19 and IO20 are connected as USB functions and should be avoided for testing
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// IO19 and IO20 are connected as USB functions.
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#define TEST_GPIO_EXT_OUT_IO 17 // default output GPIO
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#define TEST_GPIO_EXT_IN_IO 21 // default input GPIO
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#define TEST_GPIO_OUTPUT_PIN 12
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#define TEST_GPIO_INPUT_ONLY_PIN 46
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#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_MAX
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#define TEST_GPIO_USB_DM_IO 19 // USB D- GPIO
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#define TEST_GPIO_USB_DP_IO 20 // USB D+ GPIO
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#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 17
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#define TEST_GPIO_INPUT_LEVEL_LOW_PIN 1
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#elif CONFIG_IDF_TARGET_ESP32C3
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#define TEST_GPIO_EXT_OUT_IO 2 // default output GPIO
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#define TEST_GPIO_EXT_IN_IO 3 // default input GPIO
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#define TEST_GPIO_OUTPUT_PIN 1
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#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_21
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#define TEST_GPIO_USB_DM_IO 18 // USB D- GPIO
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#define TEST_GPIO_USB_DP_IO 19 // USB D+ GPIO
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#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 10
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#define TEST_GPIO_INPUT_LEVEL_LOW_PIN 1
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#endif
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// If there is any input-only pin, enable input-only pin part of some tests.
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#define SOC_HAS_INPUT_ONLY_PIN (CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2)
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// define public test io on all boards(esp32, esp32s2, esp32s3, esp32c3)
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#define TEST_IO_9 GPIO_NUM_9
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#define TEST_IO_10 GPIO_NUM_10
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@ -82,16 +96,16 @@ static gpio_config_t init_io(gpio_num_t num)
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return io_conf;
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}
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
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//No runners
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// edge interrupt event
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static void gpio_isr_edge_handler(void* arg)
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__attribute__((unused)) static void gpio_isr_edge_handler(void *arg)
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{
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uint32_t gpio_num = (uint32_t) arg;
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esp_rom_printf("GPIO[%d] intr, val: %d\n", gpio_num, gpio_get_level(gpio_num));
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edge_intr_times++;
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}
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
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//No runners
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// level interrupt event with "gpio_intr_disable"
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static void gpio_isr_level_handler(void *arg)
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{
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@ -172,7 +186,7 @@ static void drive_capability_set_get(gpio_num_t num, gpio_drive_cap_t capability
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TEST_CASE("GPIO config parameters test", "[gpio]")
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{
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//error param test
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//ESP32 test 41 bit, ESP32-S2 test 48 bit, ESP32-S3 test 49 bit
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//ESP32 test 41 bit, ESP32-S2 test 48 bit, ESP32-S3 test 50 bit
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gpio_config_t io_config = { 0 };
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io_config.intr_type = GPIO_INTR_DISABLE;
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io_config.pin_bit_mask = ((uint64_t)1 << (GPIO_NUM_MAX + 1));
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@ -182,22 +196,22 @@ TEST_CASE("GPIO config parameters test", "[gpio]")
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io_config.pin_bit_mask = 0;
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TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
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//ESP32 test 40 bit, ESP32-S2 test 47 bit, ESP32-S3 test 48 bit
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//ESP32 test 40 bit, ESP32-S2 test 47 bit, ESP32-S3 test 49 bit
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io_config.pin_bit_mask = ((uint64_t)1 << GPIO_NUM_MAX);
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TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
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io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_OUTPUT_PIN);
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TEST_ESP_OK(gpio_config(&io_config));
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//This IO is just used for input, C3 doesn't have input only pin.
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#if !CONFIG_IDF_TARGET_ESP32C3
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//This IO is just used for input, C3 and S3 doesn't have input only pin.
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#if SOC_HAS_INPUT_ONLY_PIN
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io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN);
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io_config.mode = GPIO_MODE_INPUT;
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TEST_ESP_OK(gpio_config(&io_config));
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io_config.mode = GPIO_MODE_OUTPUT;
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// The pin is input only, once set as output should log something
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TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
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#endif //!CONFIG_IDF_TARGET_ESP32C3
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#endif // SOC_HAS_INPUT_ONLY_PIN
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}
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
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@ -395,9 +409,9 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
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#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
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// ESP32 Connect GPIO18 with GPIO19, ESP32-S2 Connect GPIO17 with GPIO21,
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// ESP32-S3 Connect GPIO19 with GPIO20, ESP32C3 Connect GPIO2 with GPIO3
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// ESP32-S3 Connect GPIO17 with GPIO21, ESP32C3 Connect GPIO2 with GPIO3
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// use multimeter to test the voltage, so it is ignored in CI
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TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]")
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TEST_CASE("GPIO set gpio output level test", "[gpio][ignore][UT_T1_GPIO]")
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{
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gpio_config_t io_conf;
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io_conf.intr_type = GPIO_INTR_DISABLE;
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@ -419,30 +433,30 @@ TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]")
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// tested voltage is around 3.3v
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TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(TEST_GPIO_EXT_IN_IO), 1, "get level error! the level should be high!");
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//This IO is just used for input, C3 doesn't have input only pin.
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#if !CONFIG_IDF_TARGET_ESP32C3
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//This IO is just used for input, C3 and S3 doesn't have input only pin.
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#if SOC_HAS_INPUT_ONLY_PIN
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io_conf.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN);
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io_conf.mode = GPIO_MODE_OUTPUT;
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gpio_config(&io_conf);
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TEST_ASSERT(gpio_config(&io_conf) == ESP_ERR_INVALID_ARG);
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#endif //!CONFIG_IDF_TARGET_ESP32C3
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#endif // SOC_HAS_INPUT_ONLY_PIN
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}
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// gpio17 connects to 3.3v pin, gpio19 connects to the GND pin
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// TEST_GPIO_INPUT_LEVEL_HIGH_PIN connects to 3.3v pin, TEST_GPIO_INPUT_LEVEL_LOW_PIN connects to the GND pin
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// use multimeter to test the voltage, so it is ignored in CI
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TEST_CASE("GPIO get input level test", "[gpio][ignore]")
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{
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gpio_num_t num = 17;
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int level = gpio_get_level(num);
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printf("gpio17's level is: %d\n", level);
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TEST_ASSERT_EQUAL_INT_MESSAGE(level, 1, "get level error! the level should be high!");
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gpio_num_t num1 = TEST_GPIO_INPUT_LEVEL_HIGH_PIN;
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int level1 = gpio_get_level(num1);
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printf("TEST_GPIO_INPUT_LEVEL_HIGH_PIN's level is: %d\n", level1);
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TEST_ASSERT_EQUAL_INT_MESSAGE(level1, 1, "get level error! the level should be high!");
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gpio_num_t num2 = 19;
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gpio_num_t num2 = TEST_GPIO_INPUT_LEVEL_LOW_PIN;
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int level2 = gpio_get_level(num2);
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printf("gpio19's level is: %d\n", level2);
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printf("TEST_GPIO_INPUT_LEVEL_LOW_PIN's level is: %d\n", level2);
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TEST_ASSERT_EQUAL_INT_MESSAGE(level2, 0, "get level error! the level should be low!");
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printf("the memory get: %d\n", esp_get_free_heap_size());
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//when case finish, get the result from multimeter, the pin17 is 3.3v, the pin19 is 0.00v
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//when case finish, get the result from multimeter, the TEST_GPIO_INPUT_LEVEL_HIGH_PIN is 3.3v, the TEST_GPIO_INPUT_LEVEL_LOW_PIN is 0.00v
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}
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TEST_CASE("GPIO io pull up/down function", "[gpio]")
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@ -472,7 +486,7 @@ TEST_CASE("GPIO io pull up/down function", "[gpio]")
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//No runners
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TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]")
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{
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//ESP32 connect io18 and io19, ESP32-S2 connect io17 and io21, ESP32-S3 connect io19 and io20, ESP32C3 Connect GPIO2 with GPIO3
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//ESP32 connect io18 and io19, ESP32-S2 connect io17 and io21, ESP32-S3 connect io17 and io21, ESP32C3 Connect GPIO2 with GPIO3
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gpio_config_t output_io = init_io(TEST_GPIO_EXT_OUT_IO);
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gpio_config_t input_io = init_io(TEST_GPIO_EXT_IN_IO);
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gpio_config(&output_io);
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@ -668,7 +682,6 @@ TEST_CASE("GPIO drive capability test", "[gpio][ignore]")
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}
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#if !CONFIG_FREERTOS_UNICORE
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
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void gpio_enable_task(void *param)
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{
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int gpio_num = (int)param;
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@ -717,7 +730,6 @@ TEST_CASE("GPIO Enable/Disable interrupt on multiple cores", "[gpio][ignore]")
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gpio_uninstall_isr_service();
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TEST_ASSERT(edge_intr_times == 2);
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}
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#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
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#endif //!CONFIG_FREERTOS_UNICORE
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typedef struct {
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@ -790,3 +802,38 @@ TEST_CASE("GPIO ISR service test", "[gpio][ignore]")
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gpio_uninstall_isr_service();
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TEST_ASSERT((io9_param.isr_cnt == 1) && (io10_param.isr_cnt == 1));
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}
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#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
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TEST_CASE("GPIO input and output of USB pins test", "[gpio]")
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{
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const int test_pins[] = {TEST_GPIO_USB_DP_IO, TEST_GPIO_USB_DM_IO};
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gpio_config_t io_conf = {
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.intr_type = GPIO_INTR_DISABLE,
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.mode = GPIO_MODE_INPUT_OUTPUT,
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.pin_bit_mask = (BIT64(test_pins[0]) | BIT64(test_pins[1])),
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.pull_down_en = 0,
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.pull_up_en = 0,
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};
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gpio_config(&io_conf);
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for (int i = 0; i < sizeof(test_pins) / sizeof(int); i++) {
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int pin = test_pins[i];
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// test pin
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gpio_set_level(pin, 0);
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// tested voltage is around 0v
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TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 0, "get level error! the level should be low!");
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vTaskDelay(1000 / portTICK_RATE_MS);
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gpio_set_level(pin, 1);
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// tested voltage is around 3.3v
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TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 1, "get level error! the level should be high!");
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vTaskDelay(1000 / portTICK_RATE_MS);
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gpio_set_level(pin, 0);
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// tested voltage is around 0v
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TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 0, "get level error! the level should be low!");
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vTaskDelay(1000 / portTICK_RATE_MS);
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gpio_set_level(pin, 1);
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// tested voltage is around 3.3v
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TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 1, "get level error! the level should be high!");
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}
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}
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#endif //CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
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@ -41,7 +41,7 @@ TEST_CASE("SigmaDelta pin, duty, prescale set", "[sigma_delta][ignore]")
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int8_t duty = 0;
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int inc = 1;
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for (int i = 0; i < 1000; i++) {
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sigmadelta_set_duty(0, duty);
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sigmadelta_set_duty(sigmadelta_cfg.channel, duty);
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vTaskDelay(10 / portTICK_PERIOD_MS);
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duty += inc;
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@ -52,7 +52,7 @@ TEST_CASE("SigmaDelta pin, duty, prescale set", "[sigma_delta][ignore]")
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TEST_ESP_OK(sigmadelta_set_prescale(0, 200));
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for (int i = 0; i < 1000; i++) {
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sigmadelta_set_duty(0, duty);
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sigmadelta_set_duty(sigmadelta_cfg.channel, duty);
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vTaskDelay(10 / portTICK_PERIOD_MS);
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duty += inc;
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@ -61,6 +61,6 @@ TEST_CASE("SigmaDelta pin, duty, prescale set", "[sigma_delta][ignore]")
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}
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}
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TEST_ESP_OK(sigmadelta_set_pin(0, 5));
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TEST_ESP_OK(sigmadelta_set_pin(sigmadelta_cfg.channel, 5));
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vTaskDelay(3000 / portTICK_PERIOD_MS);
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}
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@ -32,6 +32,9 @@
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const static char TAG[] = "test_spi";
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// There is no input-only pin on esp32c3 and esp32s3
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#define TEST_SOC_HAS_INPUT_ONLY_PINS (!DISABLED_FOR_TARGETS(ESP32C3, ESP32S3))
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static void check_spi_pre_n_for(int clk, int pre, int n)
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{
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esp_err_t ret;
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@ -96,7 +99,8 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
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TEST_ASSERT(ret == ESP_OK);
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}
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static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) {
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static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma)
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{
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spi_bus_config_t buscfg = {
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.mosi_io_num = PIN_NUM_MOSI,
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.miso_io_num = PIN_NUM_MOSI,
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@ -125,7 +129,8 @@ static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) {
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return handle;
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}
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static int spi_test(spi_device_handle_t handle, int num_bytes) {
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static int spi_test(spi_device_handle_t handle, int num_bytes)
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{
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esp_err_t ret;
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int x;
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bool success = true;
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@ -155,24 +160,34 @@ static int spi_test(spi_device_handle_t handle, int num_bytes) {
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printf("Huh? Sendbuf corrupted at byte %d\n", x);
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TEST_ASSERT(0);
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}
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if (sendbuf[x]!=recvbuf[x]) break;
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if (sendbuf[x] != recvbuf[x]) {
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break;
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}
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}
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if (x != num_bytes) {
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int from = x - 16;
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if (from<0) from=0;
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if (from < 0) {
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from = 0;
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}
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success = false;
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printf("Error at %d! Sent vs recved: (starting from %d)\n", x, from);
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for (int i = 0; i < 32; i++) {
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if (i+from<num_bytes) printf("%02X ", sendbuf[from+i]);
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if (i + from < num_bytes) {
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printf("%02X ", sendbuf[from + i]);
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}
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}
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printf("\n");
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for (int i = 0; i < 32; i++) {
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if (i+from<num_bytes) printf("%02X ", recvbuf[from+i]);
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if (i + from < num_bytes) {
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printf("%02X ", recvbuf[from + i]);
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}
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}
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printf("\n");
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}
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if (success) printf("Success!\n");
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if (success) {
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printf("Success!\n");
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}
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free(sendbuf);
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free(recvbuf);
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return success;
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@ -223,7 +238,8 @@ TEST_CASE("SPI Master test", "[spi]")
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}
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TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") {
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TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]")
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{
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esp_err_t ret;
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bool success = true;
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spi_device_interface_config_t devcfg = {
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@ -266,7 +282,7 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") {
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TEST_ASSERT(success);
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}
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#if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored.
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#if TEST_SOC_HAS_INPUT_ONLY_PINS //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
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static esp_err_t test_master_pins(int mosi, int miso, int sclk, int cs)
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{
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esp_err_t ret;
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@ -328,8 +344,8 @@ TEST_CASE("spi placed on input-only pins", "[spi]")
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TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, INPUT_ONLY_PIN));
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}
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//There is no input-only pin on esp32c3, so this test could be ignored.
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#endif //#if !DISABLED_FOR_TARGETS(ESP32C3)
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//There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
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#endif //#if TEST_SOC_HAS_INPUT_ONLY_PINS
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TEST_CASE("spi bus setting with different pin configs", "[spi]")
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{
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@ -339,8 +355,10 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
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ESP_LOGI(TAG, "test 6 iomux output pins...");
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flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_QUAD;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
@ -348,8 +366,10 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
|
||||
|
||||
ESP_LOGI(TAG, "test 4 iomux output pins...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
@ -358,8 +378,10 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
|
||||
ESP_LOGI(TAG, "test 6 output pins...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD | SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
//swap MOSI and MISO
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
@ -368,113 +390,147 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
|
||||
ESP_LOGI(TAG, "test 4 output pins...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
//swap MOSI and MISO
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
|
||||
|
||||
#if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored.
|
||||
#if TEST_SOC_HAS_INPUT_ONLY_PINS //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
|
||||
ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
|
||||
|
||||
ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
|
||||
|
||||
ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
|
||||
|
||||
ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
|
||||
#endif
|
||||
//There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
|
||||
#endif //#if TEST_SOC_HAS_INPUT_ONLY_PINS
|
||||
|
||||
ESP_LOGI(TAG, "check native flag for 6 output pins...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
|
||||
//swap MOSI and MISO
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
|
||||
ESP_LOGI(TAG, "check native flag for 4 output pins...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
|
||||
//swap MOSI and MISO
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
|
||||
#if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored.
|
||||
#if TEST_SOC_HAS_INPUT_ONLY_PINS //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
|
||||
ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
|
||||
ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
#endif
|
||||
//There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
|
||||
#endif //#if TEST_SOC_HAS_INPUT_ONLY_PINS
|
||||
|
||||
ESP_LOGI(TAG, "check sclk flag...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_SCLK;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
|
||||
ESP_LOGI(TAG, "check mosi flag...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_MOSI;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = -1, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
|
||||
ESP_LOGI(TAG, "check miso flag...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_MISO;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
|
||||
ESP_LOGI(TAG, "check quad flag...");
|
||||
flags_expected = SPICOMMON_BUSFLAG_QUAD;
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected};
|
||||
cfg = (spi_bus_config_t) {
|
||||
.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1,
|
||||
.max_transfer_sz = 8, .flags = flags_expected
|
||||
};
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
|
||||
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
|
||||
}
|
||||
@ -730,7 +786,9 @@ static uint8_t bitswap(uint8_t in)
|
||||
uint8_t out = 0;
|
||||
for (int i = 0; i < 8; i++) {
|
||||
out = out >> 1;
|
||||
if (in&0x80) out |= 0x80;
|
||||
if (in & 0x80) {
|
||||
out |= 0x80;
|
||||
}
|
||||
in = in << 1;
|
||||
}
|
||||
return out;
|
||||
@ -748,7 +806,9 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
|
||||
TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
|
||||
spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
|
||||
devcfg.clock_speed_hz = 1 * 1000 * 1000;
|
||||
if (lsb_first) devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST;
|
||||
if (lsb_first) {
|
||||
devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST;
|
||||
}
|
||||
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi));
|
||||
|
||||
//connecting pins to two peripherals breaks the output, fix it.
|
||||
@ -830,7 +890,9 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
|
||||
cmd_got = cmd_got >> (16 - cmd_bits);
|
||||
|
||||
swap_ptr = (uint8_t *)&addr_got;
|
||||
for (int j = 0; j < 8; j++) swap_ptr[j] = bitswap(swap_ptr[j]);
|
||||
for (int j = 0; j < 8; j++) {
|
||||
swap_ptr[j] = bitswap(swap_ptr[j]);
|
||||
}
|
||||
addr_got = addr_got >> (64 - addr_bits);
|
||||
}
|
||||
|
||||
@ -1085,7 +1147,9 @@ static void sorted_array_insert(uint32_t* array, int* size, uint32_t item)
|
||||
{
|
||||
int pos;
|
||||
for (pos = *size; pos > 0; pos--) {
|
||||
if (array[pos-1] < item) break;
|
||||
if (array[pos - 1] < item) {
|
||||
break;
|
||||
}
|
||||
array[pos] = array[pos - 1];
|
||||
}
|
||||
array[pos] = item;
|
||||
|
||||
@ -26,6 +26,7 @@
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "soc/usb_serial_jtag_reg.h"
|
||||
#include "hal/gpio_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@ -399,6 +400,9 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
|
||||
*/
|
||||
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
|
||||
{
|
||||
if (pin_name == IO_MUX_GPIO19_REG || pin_name == IO_MUX_GPIO20_REG) {
|
||||
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
|
||||
}
|
||||
PIN_FUNC_SELECT(pin_name, func);
|
||||
}
|
||||
|
||||
|
||||
@ -78,6 +78,7 @@ typedef enum {
|
||||
#define GPIO_SEL_46 ((uint64_t)(((uint64_t)1)<<46)) /*!< Pin 46 selected */
|
||||
#if CONFIG_IDF_TARGET_ESP32S3
|
||||
#define GPIO_SEL_47 ((uint64_t)(((uint64_t)1)<<47)) /*!< Pin 47 selected */
|
||||
#define GPIO_SEL_48 ((uint64_t)(((uint64_t)1)<<48)) /*!< Pin 48 selected */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@ -129,6 +130,7 @@ typedef enum {
|
||||
#define GPIO_PIN_REG_45 IO_MUX_GPIO45_REG
|
||||
#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG
|
||||
#define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG
|
||||
#define GPIO_PIN_REG_48 IO_MUX_GPIO48_REG
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
typedef enum {
|
||||
@ -269,8 +271,9 @@ typedef enum {
|
||||
GPIO_NUM_43 = 43, /*!< GPIO43, input and output */
|
||||
GPIO_NUM_44 = 44, /*!< GPIO44, input and output */
|
||||
GPIO_NUM_45 = 45, /*!< GPIO45, input and output */
|
||||
GPIO_NUM_46 = 46, /*!< GPIO46, input mode only */
|
||||
GPIO_NUM_46 = 46, /*!< GPIO46, input and output */
|
||||
GPIO_NUM_47 = 47, /*!< GPIO47, input and output */
|
||||
GPIO_NUM_48 = 48, /*!< GPIO48, input and output */
|
||||
GPIO_NUM_MAX,
|
||||
/** @endcond */
|
||||
} gpio_num_t;
|
||||
|
||||
@ -63,6 +63,7 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
|
||||
IO_MUX_GPIO45_REG,
|
||||
IO_MUX_GPIO46_REG,
|
||||
IO_MUX_GPIO47_REG,
|
||||
IO_MUX_GPIO48_REG,
|
||||
};
|
||||
|
||||
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
|
||||
|
||||
@ -20,17 +20,17 @@ extern "C" {
|
||||
|
||||
// ESP32-S3 has 1 GPIO peripheral
|
||||
#define SOC_GPIO_PORT (1)
|
||||
#define SOC_GPIO_PIN_COUNT (48)
|
||||
#define SOC_GPIO_PIN_COUNT (49)
|
||||
|
||||
// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
|
||||
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
|
||||
// Force hold is a new function of ESP32-S3
|
||||
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
|
||||
|
||||
// 0~47 except from 22~25 are valid
|
||||
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
|
||||
// GPIO 46 is input only
|
||||
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46))
|
||||
// 0~48 except from 22~25 are valid
|
||||
#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
|
||||
// No GPIO is input only
|
||||
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -63,6 +63,7 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
|
||||
-1,//GPIO45
|
||||
-1,//GPIO46
|
||||
-1,//GPIO47
|
||||
-1,//GPIO48
|
||||
};
|
||||
|
||||
//Reg,Mux,Fun,IE,Up,Down,Rtc_number
|
||||
|
||||
@ -6,7 +6,7 @@ Overview
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
The {IDF_TARGET_NAME} chip features 40 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal.
|
||||
The {IDF_TARGET_NAME} chip features 34 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal.
|
||||
|
||||
- Note that GPIO6-11 are usually used for SPI flash.
|
||||
- GPIO34-39 can only be set as input mode and do not have software pullup or pulldown functions.
|
||||
@ -26,6 +26,14 @@ Overview
|
||||
- Note that GPIO 18 and 19 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers.
|
||||
- {IDF_TARGET_NAME} doesn't have separate "RTC GPIO" support. However, GPIO0-5 keep the rtc feature, which can be used for power-management and analog subsystem.
|
||||
|
||||
.. only:: esp32s3
|
||||
|
||||
The {IDF_TARGET_NAME} chip features 45 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal.
|
||||
|
||||
- Note that GPIO26-32 are usually used for SPI flash.
|
||||
- Note that GPIO 19 and 20 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers.
|
||||
- Note that when using SPI eight-line mode, GPIO33~37 are connected to IO4~IO7 and DQS. On ESP32-S3R8 / ESP32-S3R8V board GPIO33~37 are not recommended for other uses.
|
||||
|
||||
.. only:: SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
||||
|
||||
There is also separate "RTC GPIO" support, which functions when GPIOs are routed to the "RTC" low-power and analog subsystem. These pin functions can be used when:
|
||||
|
||||
@ -1,6 +1,8 @@
|
||||
Sigma-delta Modulation
|
||||
======================
|
||||
|
||||
{IDF_TARGET_SIGMA_DELTA_MODULATION_CHANNEL_NUM:default="8", esp32c3="4"}
|
||||
|
||||
Introduction
|
||||
------------
|
||||
|
||||
@ -9,13 +11,7 @@ Introduction
|
||||
Functionality Overview
|
||||
----------------------
|
||||
|
||||
.. only:: esp32 or esp32s2
|
||||
|
||||
There are eight independent sigma-delta modulation channels identified with :cpp:type:`sigmadelta_channel_t`. Each channel is capable to output the binary, hardware generated signal with the sigma-delta modulation.
|
||||
|
||||
.. only:: esp32c3
|
||||
|
||||
There are four independent sigma-delta modulation channels identified with :cpp:type:`sigmadelta_channel_t`. Each channel is capable to output the binary, hardware generated signal with the sigma-delta modulation.
|
||||
There are {IDF_TARGET_SIGMA_DELTA_MODULATION_CHANNEL_NUM} independent sigma-delta modulation channels identified with :cpp:type:`sigmadelta_channel_t`. Each channel is capable to output the binary, hardware generated signal with the sigma-delta modulation.
|
||||
|
||||
Selected channel should be set up by providing configuration parameters in :cpp:type:`sigmadelta_config_t` and then applying this configuration with :cpp:func:`sigmadelta_config`.
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user