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Merge branch 'bugfix/i2c_hardware_filter_default_enable' into 'master'
driver: Enable I2C master hardware filter by default. See merge request idf/esp-idf!3715
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commit
783ff9c455
@ -79,6 +79,7 @@ static DRAM_ATTR i2c_dev_t* const I2C[I2C_NUM_MAX] = { &I2C0, &I2C1 };
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#define I2C_SLAVE_SDA_HOLD_DEFAULT (10) /* I2C slave hold time after scl negative edge default value */
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#define I2C_SLAVE_SDA_HOLD_DEFAULT (10) /* I2C slave hold time after scl negative edge default value */
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#define I2C_MASTER_TOUT_CNUM_DEFAULT (8) /* I2C master timeout cycle number of I2C clock, after which the timeout interrupt will be triggered */
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#define I2C_MASTER_TOUT_CNUM_DEFAULT (8) /* I2C master timeout cycle number of I2C clock, after which the timeout interrupt will be triggered */
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#define I2C_ACKERR_CNT_MAX (10)
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#define I2C_ACKERR_CNT_MAX (10)
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#define I2C_FILTER_CYC_NUM_DEF (7) /* The number of apb cycles filtered by default*/
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typedef struct {
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typedef struct {
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uint8_t byte_num; /*!< cmd byte number */
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uint8_t byte_num; /*!< cmd byte number */
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@ -660,6 +661,8 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t* i2c_conf)
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//set timing for stop signal
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//set timing for stop signal
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I2C[i2c_num]->scl_stop_hold.time = half_cycle;
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I2C[i2c_num]->scl_stop_hold.time = half_cycle;
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I2C[i2c_num]->scl_stop_setup.time = half_cycle;
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I2C[i2c_num]->scl_stop_setup.time = half_cycle;
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//Default, we enable hardware filter
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i2c_filter_enable(i2c_num, I2C_FILTER_CYC_NUM_DEF);
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}
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}
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I2C_EXIT_CRITICAL(&i2c_spinlock[i2c_num]);
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I2C_EXIT_CRITICAL(&i2c_spinlock[i2c_num]);
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@ -693,6 +696,28 @@ esp_err_t i2c_get_period(i2c_port_t i2c_num, int* high_period, int* low_period)
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return ESP_OK;
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return ESP_OK;
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}
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}
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esp_err_t i2c_filter_enable(i2c_port_t i2c_num, uint8_t cyc_num)
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{
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I2C_CHECK(i2c_num < I2C_NUM_MAX, I2C_NUM_ERROR_STR, ESP_ERR_INVALID_ARG);
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I2C_ENTER_CRITICAL(&i2c_spinlock[i2c_num]);
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I2C[i2c_num]->scl_filter_cfg.thres = cyc_num;
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I2C[i2c_num]->sda_filter_cfg.thres = cyc_num;
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I2C[i2c_num]->scl_filter_cfg.en = 1;
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I2C[i2c_num]->sda_filter_cfg.en = 1;
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I2C_EXIT_CRITICAL(&i2c_spinlock[i2c_num]);
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return ESP_OK;
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}
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esp_err_t i2c_filter_disable(i2c_port_t i2c_num)
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{
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I2C_CHECK(i2c_num < I2C_NUM_MAX, I2C_NUM_ERROR_STR, ESP_ERR_INVALID_ARG);
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I2C_ENTER_CRITICAL(&i2c_spinlock[i2c_num]);
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I2C[i2c_num]->scl_filter_cfg.en = 0;
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I2C[i2c_num]->sda_filter_cfg.en = 0;
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I2C_EXIT_CRITICAL(&i2c_spinlock[i2c_num]);
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return ESP_OK;
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}
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esp_err_t i2c_set_start_timing(i2c_port_t i2c_num, int setup_time, int hold_time)
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esp_err_t i2c_set_start_timing(i2c_port_t i2c_num, int setup_time, int hold_time)
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{
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{
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I2C_CHECK(i2c_num < I2C_NUM_MAX, I2C_NUM_ERROR_STR, ESP_ERR_INVALID_ARG);
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I2C_CHECK(i2c_num < I2C_NUM_MAX, I2C_NUM_ERROR_STR, ESP_ERR_INVALID_ARG);
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@ -420,6 +420,35 @@ esp_err_t i2c_set_period(i2c_port_t i2c_num, int high_period, int low_period);
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*/
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*/
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esp_err_t i2c_get_period(i2c_port_t i2c_num, int* high_period, int* low_period);
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esp_err_t i2c_get_period(i2c_port_t i2c_num, int* high_period, int* low_period);
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/**
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* @brief enable hardware filter on I2C bus
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* Sometimes the I2C bus is disturbed by high frequency noise(about 20ns), or the rising edge of
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* the SCL clock is very slow, these may cause the master state machine broken. enable hardware
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* filter can filter out high frequency interference and make the master more stable.
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* @note
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* Enable filter will slow the SCL clock.
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*
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* @param i2c_num I2C port number
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* @param cyc_num the APB cycles need to be filtered(0<= cyc_num <=7).
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* When the period of a pulse is less than cyc_num * APB_cycle, the I2C controller will ignore this pulse.
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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*/
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esp_err_t i2c_filter_enable(i2c_port_t i2c_num, uint8_t cyc_num);
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/**
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* @brief disable filter on I2C bus
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*
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* @param i2c_num I2C port number
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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*/
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esp_err_t i2c_filter_disable(i2c_port_t i2c_num);
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/**
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/**
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* @brief set I2C master start signal timing
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* @brief set I2C master start signal timing
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*
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*
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