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soc: fix wrong APB_CLK_FREQ value on esp32c6

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This commit is contained in:
morris 2023-01-19 11:43:05 +08:00
parent 236fa5e669
commit 774a05399b
12 changed files with 102 additions and 103 deletions
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9
components/driver/Kconfig
View File

@ -111,15 +111,6 @@ menu "Driver Configurations"
Also you can forbid the ISR being disabled during flash writing
access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
config SPI_SUPPRESS_FREQ_MACRO_DEPRECATE_WARN
bool "Suppress SPI_MASTER_FREQ_nM deprecation warning"
default n
help
Select this option to suppress the deprecation warning when using
`SPI_MASTER_FREQ_nM` macros.
SPI clock source can be set into different clock sources. These
macros are no longer guaranteed to be accurate.
endmenu # SPI Configuration
menu "TWAI Configuration"

45
components/driver/include/driver/spi_master.h
View File

@ -9,35 +9,24 @@
#include "esp_err.h"
#include "freertos/FreeRTOS.h"
#include "hal/spi_types.h"
//for spi_bus_initialization funcions. to be back-compatible
//for spi_bus_initialization functions. to be back-compatible
#include "driver/spi_common.h"
/** SPI master clock is divided by clock source. Below defines are example frequencies. Be free to specify a random frequency, it will be rounded to closest frequency (to macros below if above 8MHz).
/**
* @brief SPI common used frequency (in Hz)
* @note SPI peripheral only has an integer divider, and the default clock source can be different on other targets,
* so the actual frequency may be slightly different from the desired frequency.
*/
#if !CONFIG_SPI_SUPPRESS_FREQ_MACRO_DEPRECATE_WARN
#define SPI_MASTER_FREQ_8M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/10)
#define SPI_MASTER_FREQ_9M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/9) ///< 8.89MHz
#define SPI_MASTER_FREQ_10M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/8) ///< 10MHz
#define SPI_MASTER_FREQ_11M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/7) ///< 11.43MHz
#define SPI_MASTER_FREQ_13M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/6) ///< 13.33MHz
#define SPI_MASTER_FREQ_16M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/5) ///< 16MHz
#define SPI_MASTER_FREQ_20M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/4) ///< 20MHz
#define SPI_MASTER_FREQ_26M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/3) ///< 26.67MHz
#define SPI_MASTER_FREQ_40M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/2) ///< 40MHz
#define SPI_MASTER_FREQ_80M _Pragma("GCC warning \"'SPI_MASTER_FREQ_xxM' macro is deprecated\"") (APB_CLK_FREQ/1) ///< 80MHz
#else
#define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/10)
#define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) ///< 8.89MHz
#define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) ///< 10MHz
#define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) ///< 11.43MHz
#define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) ///< 13.33MHz
#define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) ///< 16MHz
#define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) ///< 20MHz
#define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) ///< 26.67MHz
#define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) ///< 40MHz
#define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) ///< 80MHz
#endif //!CONFIG_SPI_SUPPRESS_FREQ_MACRO_DEPRECATE_WARN
#define SPI_MASTER_FREQ_8M (80 * 1000 * 1000 / 10) ///< 8MHz
#define SPI_MASTER_FREQ_9M (80 * 1000 * 1000 / 9) ///< 8.89MHz
#define SPI_MASTER_FREQ_10M (80 * 1000 * 1000 / 8) ///< 10MHz
#define SPI_MASTER_FREQ_11M (80 * 1000 * 1000 / 7) ///< 11.43MHz
#define SPI_MASTER_FREQ_13M (80 * 1000 * 1000 / 6) ///< 13.33MHz
#define SPI_MASTER_FREQ_16M (80 * 1000 * 1000 / 5) ///< 16MHz
#define SPI_MASTER_FREQ_20M (80 * 1000 * 1000 / 4) ///< 20MHz
#define SPI_MASTER_FREQ_26M (80 * 1000 * 1000 / 3) ///< 26.67MHz
#define SPI_MASTER_FREQ_40M (80 * 1000 * 1000 / 2) ///< 40MHz
#define SPI_MASTER_FREQ_80M (80 * 1000 * 1000 / 1) ///< 80MHz
#ifdef __cplusplus
extern "C"
@ -82,7 +71,7 @@ typedef struct {
uint16_t duty_cycle_pos; ///< Duty cycle of positive clock, in 1/256th increments (128 = 50%/50% duty). Setting this to 0 (=not setting it) is equivalent to setting this to 128.
uint16_t cs_ena_pretrans; ///< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions.
uint8_t cs_ena_posttrans; ///< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16)
int clock_speed_hz; ///< Clock speed, divisors of 80MHz, in Hz. See ``SPI_MASTER_FREQ_*``.
int clock_speed_hz; ///< Clock speed, divisors of the SPI `clock_source`, in Hz
int input_delay_ns; /**< Maximum data valid time of slave. The time required between SCLK and MISO
valid, including the possible clock delay from slave to master. The driver uses this value to give an extra
delay before the MISO is ready on the line. Leave at 0 unless you know you need a delay. For better timing
@ -361,7 +350,7 @@ void spi_device_release_bus(spi_device_handle_t dev);
* - ESP_ERR_INVALID_ARG : ``handle`` or ``freq_khz`` parameter is NULL
* - ESP_OK : Success
*/
esp_err_t spi_device_get_actual_freq(spi_device_handle_t handle, int* freq_khz);
esp_err_t spi_device_get_actual_freq(spi_device_handle_t handle, int *freq_khz);
/**
* @brief Calculate the working frequency that is most close to desired frequency.

18
components/driver/spi_master.c
View File

@ -330,8 +330,12 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
spi_host_t *host = bus_driver_ctx[host_id];
const spi_bus_attr_t* bus_attr = host->bus_attr;
SPI_CHECK(dev_config->spics_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(dev_config->spics_io_num), "spics pin invalid", ESP_ERR_INVALID_ARG);
uint32_t clock_source_hz;
clk_tree_src_get_freq_hz((dev_config->clock_source == 0)?SPI_CLK_SRC_DEFAULT:dev_config->clock_source, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
spi_clock_source_t clk_src = SPI_CLK_SRC_DEFAULT;
uint32_t clock_source_hz = 0;
if (dev_config->clock_source) {
clk_src = dev_config->clock_source;
}
clk_tree_src_get_freq_hz(clk_src, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
SPI_CHECK((dev_config->clock_speed_hz > 0) && (dev_config->clock_speed_hz <= clock_source_hz), "invalid sclk speed", ESP_ERR_INVALID_ARG);
#ifdef CONFIG_IDF_TARGET_ESP32
//The hardware looks like it would support this, but actually setting cs_ena_pretrans when transferring in full
@ -345,7 +349,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
SPI_CHECK(dev_config->post_cb != NULL, "use feature flag 'SPI_DEVICE_NO_RETURN_RESULT' but no post callback function sets", ESP_ERR_INVALID_ARG);
}
uint32_t lock_flag = ((dev_config->spics_io_num != -1)? SPI_BUS_LOCK_DEV_FLAG_CS_REQUIRED: 0);
uint32_t lock_flag = ((dev_config->spics_io_num != -1) ? SPI_BUS_LOCK_DEV_FLAG_CS_REQUIRED : 0);
spi_bus_lock_dev_config_t lock_config = {
.flags = lock_flag,
@ -362,7 +366,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
//input parameters to calculate timing configuration
int half_duplex = dev_config->flags & SPI_DEVICE_HALFDUPLEX ? 1 : 0;
int no_compensate = dev_config->flags & SPI_DEVICE_NO_DUMMY ? 1 : 0;
int duty_cycle = (dev_config->duty_cycle_pos==0) ? 128 : dev_config->duty_cycle_pos;
int duty_cycle = (dev_config->duty_cycle_pos == 0) ? 128 : dev_config->duty_cycle_pos;
int use_gpio = !(bus_attr->flags & SPICOMMON_BUSFLAG_IOMUX_PINS);
spi_hal_timing_param_t timing_param = {
.half_duplex = half_duplex,
@ -378,8 +382,8 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
spi_hal_timing_conf_t temp_timing_conf;
int freq;
esp_err_t ret = spi_hal_cal_clock_conf(&timing_param, &freq, &temp_timing_conf);
temp_timing_conf.clock_source = dev_config->clock_source;
SPI_CHECK(ret==ESP_OK, "assigned clock speed not supported", ret);
temp_timing_conf.clock_source = clk_src;
SPI_CHECK(ret == ESP_OK, "assigned clock speed not supported", ret);
//Allocate memory for device
dev = malloc(sizeof(spi_device_t));
@ -436,7 +440,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
hal_dev->rx_lsbfirst = dev_config->flags & SPI_DEVICE_RXBIT_LSBFIRST ? 1 : 0;
hal_dev->no_compensate = dev_config->flags & SPI_DEVICE_NO_DUMMY ? 1 : 0;
#if SOC_SPI_AS_CS_SUPPORTED
hal_dev->as_cs = dev_config->flags& SPI_DEVICE_CLK_AS_CS ? 1 : 0;
hal_dev->as_cs = dev_config->flags & SPI_DEVICE_CLK_AS_CS ? 1 : 0;
#endif
hal_dev->positive_cs = dev_config->flags & SPI_DEVICE_POSITIVE_CS ? 1 : 0;

100
components/driver/test_apps/legacy_timer_driver/main/test_legacy_timer.c
View File

@ -11,6 +11,7 @@
#include "unity.h"
#include "driver/timer.h"
#include "esp_private/esp_clk.h"
#include "clk_tree.h"
#include "soc/soc_caps.h"
#include "esp_rom_sys.h"
#include "soc/soc.h"
@ -286,6 +287,8 @@ static void timer_intr_enable_disable_test(timer_group_t group_num, timer_idx_t
TEST_CASE("Timer_init", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
// Test init 1:config parameter
// empty parameter
timer_config_t config0 = { };
@ -300,7 +303,7 @@ TEST_CASE("Timer_init", "[hw_timer]")
// lack one parameter
timer_config_t config2 = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.auto_reload = TIMER_AUTORELOAD_EN,
.counter_dir = TIMER_COUNT_UP,
.counter_en = TIMER_START,
@ -315,7 +318,7 @@ TEST_CASE("Timer_init", "[hw_timer]")
uint64_t set_timer_val = 0x0;
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_DIS,
.auto_reload = TIMER_AUTORELOAD_EN,
.counter_dir = TIMER_COUNT_UP,
@ -355,9 +358,11 @@ TEST_CASE("Timer_init", "[hw_timer]")
* 3. delay some time */
TEST_CASE("Timer_read_counter_value", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_EN,
.counter_dir = TIMER_COUNT_UP,
@ -395,9 +400,11 @@ TEST_CASE("Timer_read_counter_value", "[hw_timer]")
* */
TEST_CASE("Timer_start", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_EN,
.counter_dir = TIMER_COUNT_UP,
@ -427,9 +434,11 @@ TEST_CASE("Timer_start", "[hw_timer]")
*/
TEST_CASE("Timer_pause", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_EN,
.counter_dir = TIMER_COUNT_UP,
@ -455,9 +464,11 @@ TEST_CASE("Timer_pause", "[hw_timer]")
// positive mode and negative mode
TEST_CASE("Timer_counter_direction", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_EN,
.counter_dir = TIMER_COUNT_UP,
@ -492,9 +503,11 @@ TEST_CASE("Timer_counter_direction", "[hw_timer]")
TEST_CASE("Timer_divider", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_EN,
.counter_dir = TIMER_COUNT_UP,
@ -532,7 +545,7 @@ TEST_CASE("Timer_divider", "[hw_timer]")
vTaskDelay(1000 / portTICK_PERIOD_MS); //delay the same time
all_timer_get_counter_value(set_timer_val, false, comp_time_val);
for (int i = 0; i < TIMER_GROUP_MAX * TIMER_MAX; i++) {
TEST_ASSERT_INT_WITHIN(100, APB_CLK_FREQ / 256, comp_time_val[i]);
TEST_ASSERT_INT_WITHIN(100, clk_src_hz / 256, comp_time_val[i]);
}
all_timer_pause();
@ -542,7 +555,7 @@ TEST_CASE("Timer_divider", "[hw_timer]")
vTaskDelay(1000 / portTICK_PERIOD_MS);
all_timer_get_counter_value(set_timer_val, false, comp_time_val);
for (int i = 0; i < TIMER_GROUP_MAX * TIMER_MAX; i++) {
TEST_ASSERT_INT_WITHIN(5000, APB_CLK_FREQ / 2, comp_time_val[i]);
TEST_ASSERT_INT_WITHIN(5000, clk_src_hz / 2, comp_time_val[i]);
}
all_timer_pause();
@ -552,7 +565,7 @@ TEST_CASE("Timer_divider", "[hw_timer]")
vTaskDelay(1000 / portTICK_PERIOD_MS); //delay the same time
all_timer_get_counter_value(set_timer_val, false, comp_time_val);
for (int i = 0; i < TIMER_GROUP_MAX * TIMER_MAX; i++) {
TEST_ASSERT_INT_WITHIN(10, APB_CLK_FREQ / 65536, comp_time_val[i]);
TEST_ASSERT_INT_WITHIN(10, clk_src_hz / 65536, comp_time_val[i]);
}
all_timer_pause();
@ -568,9 +581,11 @@ TEST_CASE("Timer_divider", "[hw_timer]")
*/
TEST_CASE("Timer_enable_alarm", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config_test = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_DIS,
.auto_reload = TIMER_AUTORELOAD_DIS,
.counter_dir = TIMER_COUNT_UP,
@ -620,10 +635,12 @@ TEST_CASE("Timer_enable_alarm", "[hw_timer]")
*/
TEST_CASE("Timer_set_alarm_value", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
uint64_t alarm_val[SOC_TIMER_GROUP_TOTAL_TIMERS];
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_DIS,
.counter_dir = TIMER_COUNT_UP,
@ -658,9 +675,11 @@ TEST_CASE("Timer_set_alarm_value", "[hw_timer]")
*/
TEST_CASE("Timer_auto_reload", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_DIS,
.counter_dir = TIMER_COUNT_UP,
@ -698,9 +717,11 @@ TEST_CASE("Timer_auto_reload", "[hw_timer]")
*/
TEST_CASE("Timer_enable_timer_interrupt", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_DIS,
.counter_dir = TIMER_COUNT_UP,
.auto_reload = TIMER_AUTORELOAD_DIS,
@ -738,11 +759,13 @@ TEST_CASE("Timer_enable_timer_interrupt", "[hw_timer]")
*/
TEST_CASE("Timer_enable_timer_group_interrupt", "[hw_timer][ignore]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
intr_handle_t isr_handle = NULL;
alarm_flag = false;
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_DIS,
.counter_dir = TIMER_COUNT_UP,
@ -779,9 +802,11 @@ TEST_CASE("Timer_enable_timer_group_interrupt", "[hw_timer][ignore]")
*/
TEST_CASE("Timer_interrupt_register", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_DIS,
.auto_reload = TIMER_AUTORELOAD_DIS,
.counter_dir = TIMER_COUNT_UP,
@ -827,17 +852,14 @@ TEST_CASE("Timer_interrupt_register", "[hw_timer]")
}
#if SOC_TIMER_GROUP_SUPPORT_XTAL
/**
* Timer clock source:
* 1. configure clock source as APB clock, and enable timer interrupt
* 2. configure clock source as XTAL clock, adn enable timer interrupt
*/
TEST_CASE("Timer_clock_source", "[hw_timer]")
TEST_CASE("Timer_xtal_clock_source", "[hw_timer]")
{
// configure clock source as APB clock
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_XTAL, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
// configure clock source: XTAL
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.clk_src = TIMER_SRC_CLK_XTAL,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_DIS,
.auto_reload = TIMER_AUTORELOAD_DIS,
.counter_dir = TIMER_COUNT_UP,
@ -850,18 +872,6 @@ TEST_CASE("Timer_clock_source", "[hw_timer]")
all_timer_set_counter_value(0);
all_timer_isr_reg();
timer_intr_enable_disable_test(TIMER_GROUP_0, TIMER_0, 1.2 * TEST_TIMER_RESOLUTION_HZ);
#if SOC_TIMER_GROUPS > 1
timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_0, 1.2 * TEST_TIMER_RESOLUTION_HZ);
#endif
// configure clock source as XTAL clock
all_timer_pause();
config.clk_src = TIMER_SRC_CLK_XTAL;
config.divider = esp_clk_xtal_freq() / TEST_TIMER_RESOLUTION_HZ;
all_timer_init(&config, true);
all_timer_set_alarm_value(1.2 * TEST_TIMER_RESOLUTION_HZ);
timer_intr_enable_disable_test(TIMER_GROUP_0, TIMER_0, 1.2 * TEST_TIMER_RESOLUTION_HZ);
#if SOC_TIMER_GROUPS > 1
timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_0, 1.2 * TEST_TIMER_RESOLUTION_HZ);
@ -877,10 +887,12 @@ TEST_CASE("Timer_clock_source", "[hw_timer]")
*/
TEST_CASE("Timer_ISR_callback", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
alarm_flag = false;
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_DIS,
.counter_dir = TIMER_COUNT_UP,
@ -938,9 +950,11 @@ TEST_CASE("Timer_ISR_callback", "[hw_timer]")
*/
TEST_CASE("Timer_init_deinit_stress_test", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = TIMER_AUTORELOAD_EN,
.counter_dir = TIMER_COUNT_UP,
@ -959,11 +973,13 @@ TEST_CASE("Timer_init_deinit_stress_test", "[hw_timer]")
// This case will check under this fix, whether the interrupt status is cleared after timer_group initialization.
static void timer_group_test_init(void)
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
static const uint32_t time_ms = 100; // Alarm value 100ms.
static const uint32_t ste_val = time_ms * TEST_TIMER_RESOLUTION_HZ / 1000;
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.counter_dir = TIMER_COUNT_UP,
.counter_en = TIMER_PAUSE,
.alarm_en = TIMER_ALARM_EN,
@ -982,6 +998,8 @@ static void timer_group_test_init(void)
//
TEST_CASE("Timer_check_reinitialization_sequence", "[hw_timer]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
// 1. step - install driver
timer_group_test_init();
// 2 - register interrupt and start timer
@ -993,7 +1011,7 @@ TEST_CASE("Timer_check_reinitialization_sequence", "[hw_timer]")
TEST_ESP_OK(timer_deinit(TIMER_GROUP_0, TIMER_0));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TEST_TIMER_RESOLUTION_HZ,
.counter_dir = TIMER_COUNT_UP,
.counter_en = TIMER_START,
.alarm_en = TIMER_ALARM_EN,

2
components/hal/adc_hal.c
View File

@ -83,7 +83,7 @@
#define adc_ll_digi_dma_disable() adc_ll_digi_set_data_source(0)
//ESP32 ADC uses the DMA through I2S. The I2S needs to be configured.
#define I2S_BASE_CLK (2*APB_CLK_FREQ)
#define I2S_BASE_CLK (160 * 1000 * 1000)
#define SAMPLE_BITS 16
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 2
#define ADC_LL_CLKM_DIV_B_DEFAULT 0

4
components/hal/spi_hal.c
View File

@ -39,7 +39,7 @@ static void s_spi_hal_dma_init_config(const spi_hal_context_t *hal)
spi_dma_ll_rx_enable_burst_data(hal->dma_in, hal->rx_dma_chan, 1);
spi_dma_ll_tx_enable_burst_data(hal->dma_out, hal->tx_dma_chan, 1);
spi_dma_ll_rx_enable_burst_desc(hal->dma_in, hal->rx_dma_chan, 1);
spi_dma_ll_tx_enable_burst_desc(hal->dma_out, hal->tx_dma_chan ,1);
spi_dma_ll_tx_enable_burst_desc(hal->dma_out, hal->tx_dma_chan, 1);
}
void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_config_t *config)
@ -79,7 +79,7 @@ void spi_hal_deinit(spi_hal_context_t *hal)
esp_err_t spi_hal_cal_clock_conf(const spi_hal_timing_param_t *timing_param, int *out_freq, spi_hal_timing_conf_t *timing_conf)
{
spi_hal_timing_conf_t temp_conf;
spi_hal_timing_conf_t temp_conf = {};
int eff_clk_n = spi_ll_master_cal_clock(timing_param->clk_src_hz, timing_param->expected_freq, timing_param->duty_cycle, &temp_conf.clock_reg);

4
components/soc/esp32c3/include/soc/soc.h
View File

@ -137,11 +137,7 @@
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#if CONFIG_IDF_ENV_FPGA
#define APB_CLK_FREQ ( 40*1000000 )
#else
#define APB_CLK_FREQ ( 80*1000000 )
#endif
#define REF_CLK_FREQ ( 1000000 )
#define RTC_CLK_FREQ (20*1000000)
#define XTAL_CLK_FREQ (40*1000000)

2
components/soc/esp32c6/include/soc/soc.h
View File

@ -140,7 +140,7 @@
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 80*1000000 ) // TODO: IDF-6343 APB clock freq is 40MHz indeed
#define APB_CLK_FREQ ( 40*1000000 )
#define REF_CLK_FREQ ( 1000000 )
#define RTC_CLK_FREQ (20*1000000)
#define XTAL_CLK_FREQ (40*1000000)

4
components/soc/esp32h2/include/soc/soc.h
View File

@ -138,11 +138,7 @@
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#if CONFIG_IDF_ENV_FPGA
#define APB_CLK_FREQ ( 32*1000000 )
#else
#define APB_CLK_FREQ ( 80*1000000 )
#endif
#define REF_CLK_FREQ ( 1000000 )
#define RTC_CLK_FREQ (20*1000000)
#define XTAL_CLK_FREQ (32*1000000)

9
components/vfs/test/test_vfs_uart.c
View File

@ -19,6 +19,7 @@
#include "hal/uart_ll.h"
#include "esp_vfs_dev.h"
#include "esp_vfs.h"
#include "clk_tree.h"
#include "test_utils.h"
#include "sdkconfig.h"
@ -210,6 +211,8 @@ TEST_CASE("fcntl supported in UART VFS", "[vfs]")
#ifdef CONFIG_VFS_SUPPORT_TERMIOS
TEST_CASE("Can use termios for UART", "[vfs]")
{
uint32_t clk_src_hz = 0;
TEST_ESP_OK(clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
uart_config_t uart_config = {
.baud_rate = 115200,
.data_bits = UART_DATA_8_BITS,
@ -303,7 +306,7 @@ TEST_CASE("Can use termios for UART", "[vfs]")
TEST_ASSERT_EQUAL(CBAUD, tios_result.c_cflag & CBAUD);
TEST_ASSERT_EQUAL(ESP_OK, uart_get_baudrate(UART_NUM_1, &baudrate));
TEST_ASSERT_INT32_WITHIN(2, 38400, baudrate);
if (APB_CLK_FREQ == 40000000) {
if (clk_src_hz == 40000000) {
// Setting the speed to 38400 will set it actually to 38401
// Note: can't use TEST_ASSERT_INT32_WITHIN here because B38400 == 15
TEST_ASSERT_EQUAL(38401, tios_result.c_ispeed);
@ -320,7 +323,7 @@ TEST_CASE("Can use termios for UART", "[vfs]")
TEST_ASSERT_EQUAL(BOTHER, tios_result.c_cflag & BOTHER);
TEST_ASSERT_EQUAL(ESP_OK, uart_get_baudrate(UART_NUM_1, &baudrate));
// Setting the speed to 230400 will set it actually to something else,
// depending on the APB clock
// depending on the default clock source
TEST_ASSERT_INT32_WITHIN(100, 230400, tios_result.c_ispeed);
TEST_ASSERT_INT32_WITHIN(100, 230400, tios_result.c_ospeed);
TEST_ASSERT_INT32_WITHIN(100, 230400, baudrate);
@ -332,7 +335,7 @@ TEST_CASE("Can use termios for UART", "[vfs]")
TEST_ASSERT_EQUAL(BOTHER, tios_result.c_cflag & BOTHER);
TEST_ASSERT_EQUAL(ESP_OK, uart_get_baudrate(UART_NUM_1, &baudrate));
// Setting the speed to 230400 will set it actually to something else,
// depending on the APB clock
// depending on the default clock source
TEST_ASSERT_INT32_WITHIN(10, 42321, tios_result.c_ispeed);
TEST_ASSERT_INT32_WITHIN(10, 42321, tios_result.c_ospeed);
TEST_ASSERT_INT32_WITHIN(10, 42321, baudrate);

1
docs/en/migration-guides/release-5.x/5.1/peripherals.rst
View File

@ -57,4 +57,3 @@ Peripherals
Following items are deprecated. Since IDF v5.1, GPSPI clock source is configurable.
- ``spi_get_actual_clock`` is deprecated, you should use :cpp:func:`spi_device_get_actual_freq` instead.
- ``SPI_MASTER_FREQ_nM`` macros are deprecated, these macros are no longer guaranteed to be accurate, as clock source may not be APB. By default, using these macros will generate deprecation warnings. You can suppress the warnings by enabling the Kconfig option :ref:`CONFIG_SPI_SUPPRESS_FREQ_MACRO_DEPRECATE_WARN`.

5
examples/peripherals/timer_group/legacy_driver/main/timer_group_example_main.c
View File

@ -10,6 +10,7 @@
#include "freertos/task.h"
#include "freertos/queue.h"
#include "driver/timer.h"
#include "clk_tree.h"
#include "esp_log.h"
#define TIMER_RESOLUTION_HZ 1000000 // 1MHz resolution
@ -62,9 +63,11 @@ static void example_tg_timer_init(example_timer_user_data_t *user_data)
int group = user_data->timer_group;
int timer = user_data->timer_idx;
uint32_t clk_src_hz = 0;
ESP_ERROR_CHECK(clk_tree_src_get_freq_hz((soc_module_clk_t)TIMER_SRC_CLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz));
timer_config_t config = {
.clk_src = TIMER_SRC_CLK_DEFAULT,
.divider = APB_CLK_FREQ / TIMER_RESOLUTION_HZ,
.divider = clk_src_hz / TIMER_RESOLUTION_HZ,
.counter_dir = TIMER_COUNT_UP,
.counter_en = TIMER_PAUSE,
.alarm_en = TIMER_ALARM_EN,