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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
System/Memprot: fixed voltage glitching detection logic
When the application is being debugged it should check the call result (esp_cpu_in_ocd_debug_mode()) is not given volt.glitch attack - so the result is triple-checked by ESP_FAULT_ASSERT macro. In case the check fails, the system is reset immediately IDF-4014
This commit is contained in:
Martin Vychodil
parent
3a925002a7
commit
7689a801d4
@ -26,6 +26,8 @@
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#include "esp32c3/memprot.h"
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#include "riscv/interrupt.h"
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#include "esp32c3/rom/ets_sys.h"
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#include "esp_fault.h"
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#include "soc/cpu.h"
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extern int _iram_text_end;
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@ -99,18 +101,18 @@ void *esp_memprot_get_default_main_split_addr()
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uint32_t *esp_memprot_get_split_addr(split_line_t line_type)
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{
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switch ( line_type ) {
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case MEMPROT_IRAM0_DRAM0_SPLITLINE:
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return memprot_ll_get_iram0_split_line_main_I_D();
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case MEMPROT_IRAM0_LINE_0_SPLITLINE:
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return memprot_ll_get_iram0_split_line_I_0();
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case MEMPROT_IRAM0_LINE_1_SPLITLINE:
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return memprot_ll_get_iram0_split_line_I_1();
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case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE:
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return memprot_ll_get_dram0_split_line_D_0();
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case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE:
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return memprot_ll_get_dram0_split_line_D_1();
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default:
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abort();
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case MEMPROT_IRAM0_DRAM0_SPLITLINE:
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return memprot_ll_get_iram0_split_line_main_I_D();
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case MEMPROT_IRAM0_LINE_0_SPLITLINE:
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return memprot_ll_get_iram0_split_line_I_0();
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case MEMPROT_IRAM0_LINE_1_SPLITLINE:
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return memprot_ll_get_iram0_split_line_I_1();
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case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE:
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return memprot_ll_get_dram0_split_line_D_0();
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case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE:
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return memprot_ll_get_dram0_split_line_D_1();
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default:
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abort();
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}
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}
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@ -397,9 +399,9 @@ pms_world_t esp_memprot_get_violate_world(mem_type_prot_t mem_type)
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}
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switch ( world ) {
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case 0x01: return MEMPROT_PMS_WORLD_0;
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case 0x10: return MEMPROT_PMS_WORLD_1;
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default: return MEMPROT_PMS_WORLD_INVALID;
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case 0x01: return MEMPROT_PMS_WORLD_0;
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case 0x10: return MEMPROT_PMS_WORLD_1;
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default: return MEMPROT_PMS_WORLD_INVALID;
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}
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}
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@ -469,74 +471,81 @@ void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t
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void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask)
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{
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uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t)MEMPROT_ALL : *mem_type_mask;
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bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM;
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bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM;
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//if being debugged check we are not glitched and dont enable Memprot
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if (esp_cpu_in_ocd_debug_mode()) {
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ESP_FAULT_ASSERT(esp_cpu_in_ocd_debug_mode());
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} else {
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uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t) MEMPROT_ALL : *mem_type_mask;
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bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM;
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bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM;
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if (required_mem_prot == MEMPROT_NONE) {
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return;
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}
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if (required_mem_prot == MEMPROT_NONE) {
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return;
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}
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//disable protection
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if (use_iram0) {
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esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, false);
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}
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if (use_dram0) {
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esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, false);
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}
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//panic handling
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if (invoke_panic_handler) {
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//disable protection
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if (use_iram0) {
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esp_memprot_set_intr_matrix(MEMPROT_IRAM0_SRAM);
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esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, false);
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}
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if (use_dram0) {
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esp_memprot_set_intr_matrix(MEMPROT_DRAM0_SRAM);
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esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, false);
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}
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}
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//set split lines (must-have for all mem_types)
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const void *line_addr = split_addr == NULL ? esp_memprot_get_default_main_split_addr() : split_addr;
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esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_1_SPLITLINE, line_addr);
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esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_0_SPLITLINE, line_addr);
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esp_memprot_set_split_line(MEMPROT_IRAM0_DRAM0_SPLITLINE, line_addr);
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esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE, (void *)(MAP_IRAM_TO_DRAM((uint32_t)line_addr)));
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esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE, (void *)(MAP_IRAM_TO_DRAM((uint32_t)line_addr)));
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//panic handling
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if (invoke_panic_handler) {
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if (use_iram0) {
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esp_memprot_set_intr_matrix(MEMPROT_IRAM0_SRAM);
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}
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if (use_dram0) {
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esp_memprot_set_intr_matrix(MEMPROT_DRAM0_SRAM);
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}
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}
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//set permissions
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if (required_mem_prot & MEMPROT_IRAM0_SRAM) {
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_0, true, false, true);
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_1, true, false, true);
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_2, true, false, true);
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_3, true, true, false);
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}
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if (required_mem_prot & MEMPROT_DRAM0_SRAM) {
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esp_memprot_dram_set_pms_area( MEMPROT_DRAM0_PMS_AREA_0, true, false );
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_1, true, true);
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_2, true, true);
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_3, true, true);
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}
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//set split lines (must-have for all mem_types)
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const void *line_addr = split_addr == NULL ? esp_memprot_get_default_main_split_addr() : split_addr;
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esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_1_SPLITLINE, line_addr);
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esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_0_SPLITLINE, line_addr);
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esp_memprot_set_split_line(MEMPROT_IRAM0_DRAM0_SPLITLINE, line_addr);
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esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE,
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(void *) (MAP_IRAM_TO_DRAM((uint32_t) line_addr)));
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esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE,
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(void *) (MAP_IRAM_TO_DRAM((uint32_t) line_addr)));
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//reenable protection
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if (use_iram0) {
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esp_memprot_monitor_clear_intr(MEMPROT_IRAM0_SRAM);
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esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, true);
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}
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if (use_dram0) {
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esp_memprot_monitor_clear_intr(MEMPROT_DRAM0_SRAM);
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esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, true);
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}
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//set permissions
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if (required_mem_prot & MEMPROT_IRAM0_SRAM) {
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_0, true, false, true);
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_1, true, false, true);
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_2, true, false, true);
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_3, true, true, false);
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}
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if (required_mem_prot & MEMPROT_DRAM0_SRAM) {
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_0, true, false);
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_1, true, true);
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_2, true, true);
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_3, true, true);
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}
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//lock if required
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if (lock_feature) {
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esp_memprot_set_split_line_lock();
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//reenable protection
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if (use_iram0) {
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esp_memprot_set_pms_lock(MEMPROT_IRAM0_SRAM);
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esp_memprot_set_monitor_lock(MEMPROT_IRAM0_SRAM);
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esp_memprot_monitor_clear_intr(MEMPROT_IRAM0_SRAM);
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esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, true);
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}
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if (use_dram0) {
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esp_memprot_set_pms_lock(MEMPROT_DRAM0_SRAM);
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esp_memprot_set_monitor_lock(MEMPROT_DRAM0_SRAM);
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esp_memprot_monitor_clear_intr(MEMPROT_DRAM0_SRAM);
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esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, true);
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}
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//lock if required
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if (lock_feature) {
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esp_memprot_set_split_line_lock();
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if (use_iram0) {
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esp_memprot_set_pms_lock(MEMPROT_IRAM0_SRAM);
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esp_memprot_set_monitor_lock(MEMPROT_IRAM0_SRAM);
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}
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if (use_dram0) {
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esp_memprot_set_pms_lock(MEMPROT_DRAM0_SRAM);
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esp_memprot_set_monitor_lock(MEMPROT_DRAM0_SRAM);
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}
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}
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}
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}
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@ -30,7 +30,6 @@ static const char *TAG = "memprot";
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#include "hal/memprot_ll.h"
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#include "hal/memprot_peri_ll.h"
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#include "esp_fault.h"
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#include "soc/cpu.h"
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extern int _iram_text_end;
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@ -650,33 +649,32 @@ void esp_memprot_set_prot_peri2(mem_type_prot_t mem_type, uint32_t *split_addr,
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void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask)
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{
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//any IRAM0/DRAM0 enable/disable call applies to all memory modules connected
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uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t)MEMPROT_ALL : *mem_type_mask;
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bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM || required_mem_prot & MEMPROT_IRAM0_RTCFAST;
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bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM || required_mem_prot & MEMPROT_DRAM0_RTCFAST;
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bool use_peri1 = required_mem_prot & MEMPROT_PERI1_RTCSLOW;
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bool use_peri2 = required_mem_prot & MEMPROT_PERI2_RTCSLOW_0 || required_mem_prot & MEMPROT_PERI2_RTCSLOW_1;
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//if being debugged check we are not glitched and dont enable Memprot
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if (esp_cpu_in_ocd_debug_mode()) {
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ESP_FAULT_ASSERT(esp_cpu_in_ocd_debug_mode());
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} else {
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//disable protection
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if (use_iram0) {
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esp_memprot_intr_ena(MEMPROT_IRAM0_SRAM, false);
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}
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if (use_dram0) {
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esp_memprot_intr_ena(MEMPROT_DRAM0_SRAM, false);
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}
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if (use_peri1) {
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esp_memprot_intr_ena(MEMPROT_PERI1_RTCSLOW, false);
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}
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if (use_peri2) {
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esp_memprot_intr_ena(MEMPROT_PERI2_RTCSLOW_0, false);
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}
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//any IRAM0/DRAM0 enable/disable call applies to all memory modules connected
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uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t)MEMPROT_ALL : *mem_type_mask;
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bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM || required_mem_prot & MEMPROT_IRAM0_RTCFAST;
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bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM || required_mem_prot & MEMPROT_DRAM0_RTCFAST;
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bool use_peri1 = required_mem_prot & MEMPROT_PERI1_RTCSLOW;
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bool use_peri2 = required_mem_prot & MEMPROT_PERI2_RTCSLOW_0 || required_mem_prot & MEMPROT_PERI2_RTCSLOW_1;
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//connect to intr. matrix if not being debugged
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if (!esp_cpu_in_ocd_debug_mode()) {
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//disable protection
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if (use_iram0) {
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esp_memprot_intr_ena(MEMPROT_IRAM0_SRAM, false);
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}
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if (use_dram0) {
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esp_memprot_intr_ena(MEMPROT_DRAM0_SRAM, false);
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}
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if (use_peri1) {
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esp_memprot_intr_ena(MEMPROT_PERI1_RTCSLOW, false);
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}
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if (use_peri2) {
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esp_memprot_intr_ena(MEMPROT_PERI2_RTCSLOW_0, false);
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}
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ESP_FAULT_ASSERT(!esp_cpu_in_ocd_debug_mode());
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//initialize for specific buses (any memory type does the job)
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if (invoke_panic_handler) {
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if (use_iram0) {
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esp_memprot_intr_init(MEMPROT_IRAM0_SRAM);
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