From 7667d9ebbedd5f71c7d6f326bec8398df3bf4785 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Tue, 10 Sep 2024 21:01:15 +0530 Subject: [PATCH] fix(cpu_region_protect): Reset PMA entries before using them - ROM uses some PMA entries so we clear such PMA entries before using them in ESP-IDF --- .../port/esp32c5/cpu_region_protect.c | 36 +++++++++---------- .../port/esp32c61/cpu_region_protect.c | 31 +++++++++------- .../port/esp32p4/cpu_region_protect.c | 34 +++++++++--------- components/riscv/include/riscv/csr.h | 12 +++++++ 4 files changed, 67 insertions(+), 46 deletions(-) diff --git a/components/esp_hw_support/port/esp32c5/cpu_region_protect.c b/components/esp_hw_support/port/esp32c5/cpu_region_protect.c index 8e124295d5..339ae20f34 100644 --- a/components/esp_hw_support/port/esp32c5/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32c5/cpu_region_protect.c @@ -34,44 +34,44 @@ static void esp_cpu_configure_invalid_regions(void) __attribute__((unused)) const unsigned PMA_RX = PMA_L | PMA_EN | PMA_R | PMA_X; __attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X; + // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF + // 0. Gap at bottom of address space - PMA_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE); // 1. Gap between debug region & IROM - PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); // 2. ROM has configured the ROM region to be cacheable, so we just need to lock the configuration - PMA_ENTRY_SET_TOR(3, SOC_IROM_MASK_LOW, PMA_NONE); - PMA_ENTRY_SET_TOR(4, SOC_DROM_MASK_HIGH, PMA_TOR | PMA_RX); + PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_IROM_MASK_LOW, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(4, SOC_DROM_MASK_HIGH, PMA_TOR | PMA_RX); // 3. Gap between ROM & RAM - PMA_ENTRY_SET_TOR(5, SOC_DROM_MASK_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(6, SOC_IRAM_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(5, SOC_DROM_MASK_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IRAM_LOW, PMA_TOR | PMA_NONE); // 4. Gap between DRAM and I_Cache - PMA_ENTRY_SET_TOR(7, SOC_IRAM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(8, SOC_IROM_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(7, SOC_IRAM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_IROM_LOW, PMA_TOR | PMA_NONE); // 5. ROM has configured the MSPI region with RX permission, we should add W attribute for psram and lock the configuration // This function sets invalid regions but this is a valid memory region configuration that could have // been configured using PMP as well, but due to insufficient PMP entries we are configuring this using PMA. // This entry is also required to be set using PMA because the region needs to be configured as cacheable. - PMA_ENTRY_SET_NAPOT(9, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX); + PMA_RESET_AND_ENTRY_SET_NAPOT(9, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX); // 6. Gap between D_Cache & LP_RAM - PMA_ENTRY_SET_TOR(10, SOC_DROM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(11, SOC_RTC_IRAM_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_DROM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(11, SOC_RTC_IRAM_LOW, PMA_TOR | PMA_NONE); // 7. Gap between LP memory & peripheral addresses - PMA_ENTRY_SET_TOR(12, SOC_RTC_IRAM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(13, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(12, SOC_RTC_IRAM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(13, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE); // 8. End of address space - PMA_ENTRY_SET_TOR(14, SOC_PERIPHERAL_HIGH, PMA_NONE); - - PMA_ENTRY_CFG_RESET(15); - PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(14, SOC_PERIPHERAL_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE); } void esp_cpu_configure_region_protection(void) diff --git a/components/esp_hw_support/port/esp32c61/cpu_region_protect.c b/components/esp_hw_support/port/esp32c61/cpu_region_protect.c index 9a97b96597..b0866ac5f0 100644 --- a/components/esp_hw_support/port/esp32c61/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32c61/cpu_region_protect.c @@ -35,34 +35,41 @@ static void esp_cpu_configure_invalid_regions(void) __attribute__((unused)) const unsigned PMA_RX = PMA_L | PMA_EN | PMA_R | PMA_X; __attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X; + // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF + // 0. Gap at bottom of address space - PMA_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE); // 1. Gap between debug region & IROM - PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); // 3. Gap between ROM & RAM - PMA_ENTRY_SET_TOR(3, SOC_DROM_MASK_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(4, SOC_IRAM_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_DROM_MASK_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(4, SOC_IRAM_LOW, PMA_TOR | PMA_NONE); // 4. Gap between DRAM and I_Cache - PMA_ENTRY_SET_TOR(5, SOC_IRAM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(5, SOC_IRAM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE); // 5. ROM has configured the MSPI region with RX permission, we should add W attribute for psram and lock the configuration // This function sets invalid regions but this is a valid memory region configuration that could have // been configured using PMP as well, but due to insufficient PMP entries we are configuring this using PMA. // This entry is also required to be set using PMA because the region needs to be configured as cacheable. - PMA_ENTRY_SET_NAPOT(7, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX); + PMA_RESET_AND_ENTRY_SET_NAPOT(7, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX); // 6. Gap between D_Cache & peripheral addresses - PMA_ENTRY_SET_TOR(8, SOC_DROM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(9, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_DROM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(9, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE); // 7. End of address space - PMA_ENTRY_SET_TOR(10, SOC_PERIPHERAL_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(11, UINT32_MAX, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_PERIPHERAL_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(11, UINT32_MAX, PMA_TOR | PMA_NONE); + + PMA_ENTRY_CFG_RESET(12); + PMA_ENTRY_CFG_RESET(13); + PMA_ENTRY_CFG_RESET(14); + PMA_ENTRY_CFG_RESET(15); } void esp_cpu_configure_region_protection(void) diff --git a/components/esp_hw_support/port/esp32p4/cpu_region_protect.c b/components/esp_hw_support/port/esp32p4/cpu_region_protect.c index 0be25f6a1c..6f56e265b3 100644 --- a/components/esp_hw_support/port/esp32p4/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32p4/cpu_region_protect.c @@ -38,42 +38,44 @@ static void esp_cpu_configure_invalid_regions(void) __attribute__((unused)) const unsigned PMA_RX = PMA_L | PMA_EN | PMA_R | PMA_X; __attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X; + // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF + // 0. Gap at bottom of address space - PMA_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE); // 1. Gap between CPU subsystem region & HP TCM - PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(2, SOC_TCM_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_TCM_LOW, PMA_TOR | PMA_NONE); // 2. Gap between HP TCM and CPU Peripherals - PMA_ENTRY_SET_TOR(3, SOC_TCM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(4, CPU_PERIPH_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_TCM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(4, CPU_PERIPH_LOW, PMA_TOR | PMA_NONE); // 3. Gap between CPU Peripherals and I_Cache - PMA_ENTRY_SET_TOR(5, CPU_PERIPH_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(5, CPU_PERIPH_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE); // 4. Gap between I_Cache and external memory range - PMA_ENTRY_SET_NAPOT(7, SOC_DROM_HIGH, SOC_EXTRAM_LOW - SOC_DROM_HIGH, PMA_NAPOT | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_NAPOT(7, SOC_DROM_HIGH, SOC_EXTRAM_LOW - SOC_DROM_HIGH, PMA_NAPOT | PMA_NONE); // 5. Gap between external memory and ROM - PMA_ENTRY_SET_TOR(8, SOC_EXTRAM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(9, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_EXTRAM_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(9, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); // 6. Gap between ROM and internal memory - PMA_ENTRY_SET_TOR(10, SOC_IROM_MASK_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(11, SOC_IRAM_LOW, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_IROM_MASK_HIGH, PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(11, SOC_IRAM_LOW, PMA_TOR | PMA_NONE); // 7. Gap between internal memory and HP peripherals - PMA_ENTRY_SET_NAPOT(12, SOC_DRAM_HIGH, SOC_PERIPHERAL_LOW - SOC_DRAM_HIGH, PMA_NAPOT | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_NAPOT(12, SOC_DRAM_HIGH, SOC_PERIPHERAL_LOW - SOC_DRAM_HIGH, PMA_NAPOT | PMA_NONE); // 8. Special case - This whitelists the External flash/RAM, HP ROM and HP L2MEM regions and make them cacheable. // At the startup, this is done using PMA entry 15 by the ROM code. - PMA_ENTRY_SET_NAPOT(13, SOC_IROM_LOW, SOC_PERIPHERAL_LOW - SOC_IROM_LOW, PMA_NAPOT | PMA_RWX); + PMA_RESET_AND_ENTRY_SET_NAPOT(13, SOC_IROM_LOW, SOC_PERIPHERAL_LOW - SOC_IROM_LOW, PMA_NAPOT | PMA_RWX); // 9. Gap between Uncacheable L2 Mem and end of address space - PMA_ENTRY_SET_TOR(14, CACHE_LL_L2MEM_NON_CACHE_ADDR(SOC_DRAM_HIGH), PMA_NONE); - PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(14, CACHE_LL_L2MEM_NON_CACHE_ADDR(SOC_DRAM_HIGH), PMA_NONE); + PMA_RESET_AND_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE); } void esp_cpu_configure_region_protection(void) diff --git a/components/riscv/include/riscv/csr.h b/components/riscv/include/riscv/csr.h index 5640151c75..b55932f0b7 100644 --- a/components/riscv/include/riscv/csr.h +++ b/components/riscv/include/riscv/csr.h @@ -142,6 +142,18 @@ extern "C" { RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY) , 0); \ } while(0) +/* Reset and set the configuration of a particular TOR PMACFG entry */ +#define PMA_RESET_AND_ENTRY_SET_TOR(ENTRY, ADDR, CFG) do {\ + PMA_ENTRY_CFG_RESET(ENTRY); \ + PMA_ENTRY_SET_TOR(ENTRY, ADDR, CFG); \ + } while(0) + +/* Reset and set the configuration of a particular NAPOT PMACFG entry */ +#define PMA_RESET_AND_ENTRY_SET_NAPOT(ENTRY, ADDR, SIZE, CFG) do {\ + PMA_ENTRY_CFG_RESET(ENTRY); \ + PMA_ENTRY_SET_NAPOT(ENTRY, ADDR, SIZE, CFG); \ + } while(0) + /******************************************************** Trigger Module register fields (Debug specification) ********************************************************/