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esp_hw_support: Add esp32c3 regi2c headers
This commit is contained in:
Angus Gratton
parent
8e0d423a5e
commit
75dede2344
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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/**
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* @file regi2c_bbpll.h
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* @brief Register definitions for digital PLL (BBPLL)
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*
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* This file lists register fields of BBPLL, located on an internal configuration
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* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
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* rtc_clk_cpu_freq_set function in rtc_clk.c.
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*/
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#define I2C_BBPLL 0x66
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#define I2C_BBPLL_HOSTID 0
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#define I2C_BBPLL_IR_CAL_DELAY 0
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#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
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#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
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#define I2C_BBPLL_IR_CAL_CK_DIV 0
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#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
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#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
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#define I2C_BBPLL_IR_CAL_EXT_CAP 1
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#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
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#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
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#define I2C_BBPLL_IR_CAL_ENX_CAP 1
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#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
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#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
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#define I2C_BBPLL_IR_CAL_RSTB 1
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#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
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#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
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#define I2C_BBPLL_IR_CAL_START 1
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#define I2C_BBPLL_IR_CAL_START_MSB 6
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#define I2C_BBPLL_IR_CAL_START_LSB 6
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#define I2C_BBPLL_IR_CAL_UNSTOP 1
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#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
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#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
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#define I2C_BBPLL_OC_REF_DIV 2
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#define I2C_BBPLL_OC_REF_DIV_MSB 3
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#define I2C_BBPLL_OC_REF_DIV_LSB 0
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#define I2C_BBPLL_OC_DCHGP 2
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#define I2C_BBPLL_OC_DCHGP_MSB 6
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#define I2C_BBPLL_OC_DCHGP_LSB 4
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#define I2C_BBPLL_OC_ENB_FCAL 2
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#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
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#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
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#define I2C_BBPLL_OC_DIV_7_0 3
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#define I2C_BBPLL_OC_DIV_7_0_MSB 7
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#define I2C_BBPLL_OC_DIV_7_0_LSB 0
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#define I2C_BBPLL_RSTB_DIV_ADC 4
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#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
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#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
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#define I2C_BBPLL_MODE_HF 4
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#define I2C_BBPLL_MODE_HF_MSB 1
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#define I2C_BBPLL_MODE_HF_LSB 1
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#define I2C_BBPLL_DIV_ADC 4
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#define I2C_BBPLL_DIV_ADC_MSB 3
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#define I2C_BBPLL_DIV_ADC_LSB 2
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#define I2C_BBPLL_DIV_DAC 4
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#define I2C_BBPLL_DIV_DAC_MSB 4
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#define I2C_BBPLL_DIV_DAC_LSB 4
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#define I2C_BBPLL_DIV_CPU 4
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#define I2C_BBPLL_DIV_CPU_MSB 5
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#define I2C_BBPLL_DIV_CPU_LSB 5
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#define I2C_BBPLL_OC_ENB_VCON 4
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#define I2C_BBPLL_OC_ENB_VCON_MSB 6
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#define I2C_BBPLL_OC_ENB_VCON_LSB 6
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#define I2C_BBPLL_OC_TSCHGP 4
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#define I2C_BBPLL_OC_TSCHGP_MSB 7
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#define I2C_BBPLL_OC_TSCHGP_LSB 7
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#define I2C_BBPLL_OC_DR1 5
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#define I2C_BBPLL_OC_DR1_MSB 2
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#define I2C_BBPLL_OC_DR1_LSB 0
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#define I2C_BBPLL_OC_DR3 5
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#define I2C_BBPLL_OC_DR3_MSB 6
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#define I2C_BBPLL_OC_DR3_LSB 4
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#define I2C_BBPLL_EN_USB 5
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#define I2C_BBPLL_EN_USB_MSB 7
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#define I2C_BBPLL_EN_USB_LSB 7
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#define I2C_BBPLL_OC_DCUR 6
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#define I2C_BBPLL_OC_DCUR_MSB 2
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#define I2C_BBPLL_OC_DCUR_LSB 0
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#define I2C_BBPLL_INC_CUR 6
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#define I2C_BBPLL_INC_CUR_MSB 3
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#define I2C_BBPLL_INC_CUR_LSB 3
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#define I2C_BBPLL_OC_DHREF_SEL 6
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#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
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#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
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#define I2C_BBPLL_OC_DLREF_SEL 6
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#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
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#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
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#define I2C_BBPLL_OR_CAL_CAP 8
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#define I2C_BBPLL_OR_CAL_CAP_MSB 3
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#define I2C_BBPLL_OR_CAL_CAP_LSB 0
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#define I2C_BBPLL_OR_CAL_UDF 8
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#define I2C_BBPLL_OR_CAL_UDF_MSB 4
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#define I2C_BBPLL_OR_CAL_UDF_LSB 4
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#define I2C_BBPLL_OR_CAL_OVF 8
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#define I2C_BBPLL_OR_CAL_OVF_MSB 5
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#define I2C_BBPLL_OR_CAL_OVF_LSB 5
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#define I2C_BBPLL_OR_CAL_END 8
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#define I2C_BBPLL_OR_CAL_END_MSB 6
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#define I2C_BBPLL_OR_CAL_END_LSB 6
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#define I2C_BBPLL_OR_LOCK 8
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#define I2C_BBPLL_OR_LOCK_MSB 7
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#define I2C_BBPLL_OR_LOCK_LSB 7
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#define I2C_BBPLL_OC_VCO_DBIAS 9
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#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1
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#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0
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#define I2C_BBPLL_BBADC_DELAY2 9
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#define I2C_BBPLL_BBADC_DELAY2_MSB 3
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#define I2C_BBPLL_BBADC_DELAY2_LSB 2
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#define I2C_BBPLL_BBADC_DVDD 9
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#define I2C_BBPLL_BBADC_DVDD_MSB 5
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#define I2C_BBPLL_BBADC_DVDD_LSB 4
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#define I2C_BBPLL_BBADC_DREF 9
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#define I2C_BBPLL_BBADC_DREF_MSB 7
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#define I2C_BBPLL_BBADC_DREF_LSB 6
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#define I2C_BBPLL_BBADC_DCUR 10
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#define I2C_BBPLL_BBADC_DCUR_MSB 1
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#define I2C_BBPLL_BBADC_DCUR_LSB 0
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#define I2C_BBPLL_BBADC_INPUT_SHORT 10
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#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
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#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
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#define I2C_BBPLL_ENT_PLL 10
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#define I2C_BBPLL_ENT_PLL_MSB 3
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#define I2C_BBPLL_ENT_PLL_LSB 3
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#define I2C_BBPLL_DTEST 10
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#define I2C_BBPLL_DTEST_MSB 5
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#define I2C_BBPLL_DTEST_LSB 4
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#define I2C_BBPLL_ENT_ADC 10
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#define I2C_BBPLL_ENT_ADC_MSB 7
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#define I2C_BBPLL_ENT_ADC_LSB 6
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@ -0,0 +1,30 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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/**
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* @file regi2c_bias.h
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* @brief Register definitions for bias
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*
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* This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
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* bootloader_hardware_init function in bootloader_esp32c3.c.
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*/
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#define I2C_BIAS 0X6A
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#define I2C_BIAS_HOSTID 0
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#define I2C_BIAS_DREG_1P1_PVT 1
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#define I2C_BIAS_DREG_1P1_PVT_MSB 3
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#define I2C_BIAS_DREG_1P1_PVT_LSB 0
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@ -0,0 +1,30 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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/**
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* @file regi2c_brownout.h
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* @brief Register definitions for brownout detector
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*
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* This file lists register fields of the brownout detector, located on an internal configuration
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* bus. These definitions are used via macros defined in regi2c_ctrl.h.
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*/
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#define I2C_BOD 0x61
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#define I2C_BOD_HOSTID 1
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#define I2C_BOD_THRESHOLD 0x5
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#define I2C_BOD_THRESHOLD_MSB 2
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#define I2C_BOD_THRESHOLD_LSB 0
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@ -0,0 +1,68 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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/**
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* @file regi2c_dig_reg.h
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* @brief Register definitions for digital to get rtc voltage & digital voltage
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* by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
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*/
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#define I2C_DIG_REG 0x6D
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#define I2C_DIG_REG_HOSTID 0
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#define I2C_DIG_REG_EXT_RTC_DREG 4
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#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
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#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
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#define I2C_DIG_REG_ENX_RTC_DREG 4
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#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
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#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7
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#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
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#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
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#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
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#define I2C_DIG_REG_ENX_RTC_DREG_SLEEP 5
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#define I2C_DIG_REG_ENX_RTC_DREG_SLEEP_MSB 7
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#define I2C_DIG_REG_ENX_RTC_DREG_SLEEP_LSB 7
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#define I2C_DIG_REG_EXT_DIG_DREG 6
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#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4
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#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0
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#define I2C_DIG_REG_ENX_DIG_DREG 6
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#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7
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#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7
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#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
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#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
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#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
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#define I2C_DIG_REG_ENX_DIG_DREG_SLEEP 7
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#define I2C_DIG_REG_ENX_DIG_DREG_SLEEP_MSB 7
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#define I2C_DIG_REG_ENX_DIG_DREG_SLEEP_LSB 7
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#define I2C_DIG_REG_OR_EN_CONT_CAL 9
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#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
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#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
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#define I2C_DIG_REG_XPD_RTC_REG 13
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#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
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#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
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#define I2C_DIG_REG_XPD_DIG_REG 13
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#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
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#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
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@ -0,0 +1,43 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
|
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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/**
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* @file regi2c_lp_bias.h
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* @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
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*
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* This file lists register fields of low power dbais, located on an internal configuration
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* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
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* rtc_init function in rtc_init.c.
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*/
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#define I2C_ULP 0x61
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#define I2C_ULP_HOSTID 0
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#define I2C_ULP_IR_RESETB 0
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#define I2C_ULP_IR_RESETB_MSB 0
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#define I2C_ULP_IR_RESETB_LSB 0
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#define I2C_ULP_O_DONE_FLAG 3
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#define I2C_ULP_O_DONE_FLAG_MSB 0
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#define I2C_ULP_O_DONE_FLAG_LSB 0
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#define I2C_ULP_BG_O_DONE_FLAG 3
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#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
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#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
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#define I2C_ULP_IR_FORCE_XPD_IPH 0
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#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
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#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
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@ -0,0 +1,83 @@
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// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
|
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// You may obtain a copy of the License at
|
||||
//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
|
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// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
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#pragma once
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/**
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* @file regi2c_saradc.h
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* @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
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*
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* This file lists register fields of SAR, located on an internal configuration
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* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
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* function in adc_ll.h.
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*/
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#define I2C_SAR_ADC 0X69
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#define I2C_SAR_ADC_HOSTID 1
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#define ADC_SAR1_ENCAL_GND_ADDR 0x7
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#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
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#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
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#define ADC_SAR2_ENCAL_GND_ADDR 0x7
|
||||
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
|
||||
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
|
||||
|
||||
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
|
||||
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
|
||||
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
|
||||
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
|
||||
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR1_DREF_ADDR 0x2
|
||||
#define ADC_SAR1_DREF_ADDR_MSB 0x6
|
||||
#define ADC_SAR1_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_SAR2_DREF_ADDR 0x5
|
||||
#define ADC_SAR2_DREF_ADDR_MSB 0x6
|
||||
#define ADC_SAR2_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
|
||||
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
|
||||
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SARADC_DTEST_RTC_ADDR 0x7
|
||||
#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
|
||||
#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
|
||||
|
||||
#define ADC_SARADC_ENT_TSENS_ADDR 0x7
|
||||
#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
|
||||
#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
|
||||
|
||||
#define ADC_SARADC_ENT_RTC_ADDR 0x7
|
||||
#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
|
||||
#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
|
||||
|
||||
#define ADC_SARADC_ENCAL_REF_ADDR 0x7
|
||||
#define ADC_SARADC_ENCAL_REF_ADDR_MSB 4
|
||||
#define ADC_SARADC_ENCAL_REF_ADDR_LSB 4
|
||||
|
||||
#define I2C_SARADC_TSENS_DAC 0x6
|
||||
#define I2C_SARADC_TSENS_DAC_MSB 3
|
||||
#define I2C_SARADC_TSENS_DAC_LSB 0
|
||||
80
components/esp_hw_support/port/esp32c3/regi2c_ctrl.h
Normal file
80
components/esp_hw_support/port/esp32c3/regi2c_ctrl.h
Normal file
@ -0,0 +1,80 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "regi2c_bbpll.h"
|
||||
#include "regi2c_lp_bias.h"
|
||||
#include "regi2c_dig_reg.h"
|
||||
#include "regi2c_bias.h"
|
||||
#include "regi2c_saradc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Analog function control register */
|
||||
#define ANA_CONFIG_REG 0x6000E044
|
||||
#define ANA_CONFIG_S (8)
|
||||
#define ANA_CONFIG_M (0x3FF)
|
||||
/* Clear to enable APLL */
|
||||
#define I2C_APLL_M (BIT(14))
|
||||
/* Clear to enable BBPLL */
|
||||
#define I2C_BBPLL_M (BIT(17))
|
||||
|
||||
#define SAR_I2C_FORCE_PD BIT(18)
|
||||
#define SAR_I2C_FORCE_PU BIT(16)
|
||||
|
||||
#define ANA_CONFIG2_REG 0x6000E048
|
||||
#define ANA_CONFIG2_M (BIT(18))
|
||||
|
||||
/* ROM functions which read/write internal control bus */
|
||||
uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
|
||||
uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
|
||||
void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
|
||||
void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
|
||||
|
||||
/* Convenience macros for the above functions, these use register definitions
|
||||
* from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/regi2c_bias.h header files.
|
||||
*/
|
||||
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
|
||||
rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
|
||||
|
||||
#define REGI2C_READ_MASK(block, reg_add) \
|
||||
rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
|
||||
|
||||
#define REGI2C_WRITE(block, reg_add, indata) \
|
||||
rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
|
||||
|
||||
#define REGI2C_READ(block, reg_add) \
|
||||
rom_i2c_readReg(block, block##_HOSTID, reg_add)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -902,30 +902,7 @@ static inline void adc_ll_disable_sleep_controller(void)
|
||||
*/
|
||||
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd)
|
||||
{
|
||||
// /* Enable i2s_write_reg function. */
|
||||
// void phy_get_romfunc_addr(void);
|
||||
// phy_get_romfunc_addr();
|
||||
// //CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
|
||||
// //SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
// CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
// SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
// /* Enable/disable internal connect GND (for calibration). */
|
||||
// if (adc_n == ADC_NUM_1) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_DREF_ADDR, 4);
|
||||
// if (internal_gnd) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_ENCAL_GND_ADDR, 1);
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0);
|
||||
// }
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_DREF_ADDR, 4);
|
||||
// if (internal_gnd) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_ENCAL_GND_ADDR, 1);
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0);
|
||||
// }
|
||||
// }
|
||||
abort(); // TODO ESP32-C3 IDF-2526
|
||||
}
|
||||
|
||||
/**
|
||||
@ -935,11 +912,7 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
|
||||
*/
|
||||
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
|
||||
{
|
||||
// if (adc_n == ADC_NUM_1) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0);
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0);
|
||||
// }
|
||||
abort(); // TODO ESP32-C3 IDF-2526
|
||||
}
|
||||
|
||||
/**
|
||||
@ -951,24 +924,8 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
|
||||
*/
|
||||
static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param)
|
||||
{
|
||||
// uint8_t msb = param >> 8;
|
||||
// uint8_t lsb = param & 0xFF;
|
||||
// /* Enable i2s_write_reg function. */
|
||||
// void phy_get_romfunc_addr(void);
|
||||
// phy_get_romfunc_addr();
|
||||
// //SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
// CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
// SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
// if (adc_n == ADC_NUM_1) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
// }
|
||||
abort(); // TODO ESP32-C3 IDF-2526
|
||||
}
|
||||
/* Temp code end. */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user