Merge branch 'docs/update_spi_features' into 'master'

docs: Review and update spi_features

Closes DOC-4575

See merge request espressif/esp-idf!22249

docs/en/api-reference/peripherals/spi_features.rst

@@ -11,18 +11,18 @@ SPI Master
 SPI Bus Lock
 ^^^^^^^^^^^^
 
-To realize the multiplexing of different devices from different drivers, including SPI Master, SPI Flash, etc., an SPI bus lock is applied on each SPI bus. Drivers can attach their devices onto the bus with the arbitration of the lock.
+To realize the multiplexing of different devices from different drivers, including SPI Master, SPI Flash, etc., an SPI bus lock is applied on each SPI bus. Drivers can attach their devices to the bus with the arbitration of the lock.
 
 Each bus lock is initialized with a BG (background) service registered. All devices that request transactions on the bus should wait until the BG is successfully disabled.
 
-- For SPI1 bus, the BG is the cache. The bus lock will disable the cache before device operations start, and enable it again after device releases the lock. No devices on SPI1 is allowed to use ISR, since it is meaningless for the task to yield to other tasks when the cache is disabled.
+- For the SPI1 bus, the BG is the cache. The bus lock will disable the cache before device operations start, and enable it again after the device releases the lock. No devices on SPI1 are allowed to use ISR, since it is meaningless for the task to yield to other tasks when the cache is disabled.
 
   .. only:: esp32
 
-      There are quite a few limitations when using SPI Master driver on the SPI1 bus. See :ref:`spi_master_on_spi1_bus`.
+      There are quite a few limitations when using the SPI Master driver on the SPI1 bus. See :ref:`spi_master_on_spi1_bus`.
 
   .. only:: not esp32
 
-      The SPI Master driver hasn't supported SPI1 bus. Only SPI Flash driver can attach to the bus.
+      The SPI Master driver hasn't supported SPI1 bus. Only the SPI Flash driver can attach to the bus.
 
-- For other buses, the driver may register its ISR as the BG. When a device task requests for exclusive use of the bus, the bus lock will block the task and try to disable ISR. After ISR is successfully disabled, the bus lock will then unblock the device task and allow it to exclusively use the bus. When the task releases the lock, the lock will also try to resume ISR if there are pending transactions in ISR.
+- For other buses, the driver can register the ISR as a BG. If a device task requests exclusive bus access, the bus lock will block the task, disable the ISR, and then unblock the task. After the task releases the lock, the lock will try to re-enable the ISR if there are still pending transactions in the ISR.

docs/zh_CN/api-reference/peripherals/spi_features.rst

@@ -11,18 +11,18 @@ SPI 主机
 SPI 总线锁
 ^^^^^^^^^^^^
 
-为了多路复用来自不同驱动的不同设备，包括 SPI 主机、SPI Flash 等驱动，每个 SPI 总线上都有一个 SPI 总线锁。驱动程序可以通过对锁的仲裁，将设备连接到总线上。
+为了多路复用来自 SPI 主机、SPI flash 等不同驱动的设备，每个 SPI 总线上都配有 SPI 总线锁。驱动程序可以通过对锁实施仲裁，将设备连接到总线上。
 
-每个总线锁都已初始化并注册了后台服务 (BG)。所有请求在总线上进行传输的设备都应等到 BG 被成功禁用后再开始传输。
+每个总线锁都已初始化并注册了后台服务 (BG)。设备应在 BG 禁用后，再在总线上进行传输。
 
-- 在 SPI1 总线上，BG 为高速缓存。总线锁可以在设备操作开始前禁用高速缓存，并在设备释放锁后再次启用它。SPI1 上的任何设备都无法使用 ISR，因为当高速缓存被禁用时，让出当前任务的执行权是没有意义的。
+- SPI1 总线的后台服务为高速缓存。在设备操作开始前，总线锁可以禁用高速缓存，并在设备释放锁后将其再次启用。高速缓存处于禁用状态时，让出当前任务的执行权毫无意义，因此，该情况下 SPI1 总线上的任何设备都无法使用 ISR。
 
   .. only:: esp32
 
-      在 SPI1 总线上使用 SPI 主机驱动程序时，存在一些限制。请参见 :ref:`spi_master_on_spi1_bus`。
+      在 SPI1 总线上使用 SPI 主机驱动程序存在一些限制。请参见 :ref:`spi_master_on_spi1_bus`。
 
   .. only:: not esp32
 
-      SPI 主机驱动程序暂不支持 SPI1 总线。只有 SPI Flash 驱动程序可以连接到该总线。
+      SPI 主机驱动程序暂不支持 SPI1 总线。只有 SPI flash 驱动程序可以连接到该总线。
 
-- 对于其他总线，驱动程序可以将其 ISR 注册为 BG。当一个设备任务要求独占总线时，总线锁将阻塞该任务，同时禁用 ISR，并在 ISR 被成功禁用后，解除对该任务的阻塞。当任务释放锁时，如果 ISR 中还有待处理的事务，锁也将尝试恢复 ISR。
+- 对于其他总线，驱动程序可以将 ISR 注册为后台服务。若设备任务要求独占总线，则总线锁将阻塞该任务，同时禁用 ISR，随即解除对该任务的阻塞。任务释放锁后，如果 ISR 中还有待处理的事务，则锁将尝试重新启用 ISR。