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newlib: stdatomic: emulate 64-bit atomics on 32-bit SMP SoCs
Closes https://github.com/espressif/esp-idf/issues/3163
This commit is contained in:
Ivan Grokhotkov
parent
32fcd4f02a
commit
742102079a
@ -1,4 +1,4 @@
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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@ -17,61 +17,78 @@
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#include "sdkconfig.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "freertos/FreeRTOS.h"
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#ifdef __XTENSA__
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#include "xtensa/config/core-isa.h"
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#include "xtensa/xtruntime.h"
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// This allows nested interrupts disabling and restoring via local registers or stack.
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// They can be called from interrupts too.
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// WARNING: Only applies to current CPU.
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#define _ATOMIC_ENTER_CRITICAL(void) ({ \
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unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); \
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atomic_benchmark_intr_disable(); \
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state; \
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})
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#define _ATOMIC_EXIT_CRITICAL(state) do { \
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atomic_benchmark_intr_restore(state); \
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XTOS_RESTORE_JUST_INTLEVEL(state); \
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} while (0)
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#ifndef XCHAL_HAVE_S32C1I
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#error "XCHAL_HAVE_S32C1I not defined, include correct header!"
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#endif
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#define NO_ATOMICS_SUPPORT (XCHAL_HAVE_S32C1I == 0)
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#define HAS_ATOMICS_32 (XCHAL_HAVE_S32C1I == 1)
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// no 64-bit atomics on Xtensa
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#define HAS_ATOMICS_64 0
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#else // RISCV
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#include "freertos/portmacro.h"
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// This allows nested interrupts disabling and restoring via local registers or stack.
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// They can be called from interrupts too.
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// WARNING: Only applies to current CPU.
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#define _ATOMIC_ENTER_CRITICAL(void) ({ \
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unsigned state = portENTER_CRITICAL_NESTED(); \
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atomic_benchmark_intr_disable(); \
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state; \
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})
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#define _ATOMIC_EXIT_CRITICAL(state) do { \
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atomic_benchmark_intr_restore(state); \
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portEXIT_CRITICAL_NESTED(state); \
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} while (0)
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#ifndef __riscv_atomic // GCC toolchain will define this pre-processor if "A" extension is supported
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// GCC toolchain will define this pre-processor if "A" extension is supported
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#ifndef __riscv_atomic
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#define __riscv_atomic 0
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#endif
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#define NO_ATOMICS_SUPPORT (__riscv_atomic == 0)
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#define HAS_ATOMICS_32 (__riscv_atomic == 1)
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#define HAS_ATOMICS_64 ((__riscv_atomic == 1) && (__riscv_xlen == 64))
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#endif // (__XTENSA__, __riscv)
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#endif
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#if SOC_CPU_CORES_NUM == 1
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// Single core SoC: atomics can be implemented using portENTER_CRITICAL_NESTED
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// and portEXIT_CRITICAL_NESTED, which disable and enable interrupts.
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#define _ATOMIC_ENTER_CRITICAL() ({ \
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unsigned state = portENTER_CRITICAL_NESTED(); \
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state; \
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})
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//reserved to measure atomic operation time
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#define atomic_benchmark_intr_disable()
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#define atomic_benchmark_intr_restore(STATE)
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#define _ATOMIC_EXIT_CRITICAL(state) do { \
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portEXIT_CRITICAL_NESTED(state); \
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} while (0)
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#else // SOC_CPU_CORES_NUM
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_Static_assert(HAS_ATOMICS_32, "32-bit atomics should be supported if SOC_CPU_CORES_NUM > 1");
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// Only need to implement 64-bit atomics here. Use a single global portMUX_TYPE spinlock
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// to emulate the atomics.
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static portMUX_TYPE s_atomic_lock = portMUX_INITIALIZER_UNLOCKED;
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// Return value is not used but kept for compatibility with the single-core version above.
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#define _ATOMIC_ENTER_CRITICAL() ({ \
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portENTER_CRITICAL_SAFE(&s_atomic_lock); \
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0; \
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})
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#define _ATOMIC_EXIT_CRITICAL(state) do { \
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(void) (state); \
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portEXIT_CRITICAL_SAFE(&s_atomic_lock); \
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} while(0)
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#endif // SOC_CPU_CORES_NUM
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#define ATOMIC_LOAD(n, type) type __atomic_load_ ## n (const type* mem, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *mem; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define ATOMIC_STORE(n, type) void __atomic_store_ ## n (type* mem, type val, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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*mem = val; \
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_ATOMIC_EXIT_CRITICAL(state); \
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}
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#define ATOMIC_EXCHANGE(n, type) type __atomic_exchange_ ## n (type* mem, type val, int memorder) \
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{ \
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@ -169,76 +186,98 @@
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return ret; \
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}
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#if NO_ATOMICS_SUPPORT
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#if !HAS_ATOMICS_32
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ATOMIC_EXCHANGE(1, uint8_t)
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ATOMIC_EXCHANGE(2, uint16_t)
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ATOMIC_EXCHANGE(4, uint32_t)
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ATOMIC_EXCHANGE(8, uint64_t)
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CMP_EXCHANGE(1, uint8_t)
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CMP_EXCHANGE(2, uint16_t)
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CMP_EXCHANGE(4, uint32_t)
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CMP_EXCHANGE(8, uint64_t)
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FETCH_ADD(1, uint8_t)
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FETCH_ADD(2, uint16_t)
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FETCH_ADD(4, uint32_t)
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FETCH_ADD(8, uint64_t)
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FETCH_SUB(1, uint8_t)
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FETCH_SUB(2, uint16_t)
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FETCH_SUB(4, uint32_t)
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FETCH_SUB(8, uint64_t)
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FETCH_AND(1, uint8_t)
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FETCH_AND(2, uint16_t)
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FETCH_AND(4, uint32_t)
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FETCH_AND(8, uint64_t)
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FETCH_OR(1, uint8_t)
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FETCH_OR(2, uint16_t)
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FETCH_OR(4, uint32_t)
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FETCH_OR(8, uint64_t)
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FETCH_XOR(1, uint8_t)
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FETCH_XOR(2, uint16_t)
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FETCH_XOR(4, uint32_t)
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FETCH_XOR(8, uint64_t)
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SYNC_FETCH_OP(add, 1, uint8_t)
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SYNC_FETCH_OP(add, 2, uint16_t)
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SYNC_FETCH_OP(add, 4, uint32_t)
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SYNC_FETCH_OP(add, 8, uint64_t)
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SYNC_FETCH_OP(sub, 1, uint8_t)
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SYNC_FETCH_OP(sub, 2, uint16_t)
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SYNC_FETCH_OP(sub, 4, uint32_t)
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SYNC_FETCH_OP(sub, 8, uint64_t)
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SYNC_FETCH_OP(and, 1, uint8_t)
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SYNC_FETCH_OP(and, 2, uint16_t)
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SYNC_FETCH_OP(and, 4, uint32_t)
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SYNC_FETCH_OP(and, 8, uint64_t)
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SYNC_FETCH_OP(or, 1, uint8_t)
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SYNC_FETCH_OP(or, 2, uint16_t)
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SYNC_FETCH_OP(or, 4, uint32_t)
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SYNC_FETCH_OP(or, 8, uint64_t)
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SYNC_FETCH_OP(xor, 1, uint8_t)
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SYNC_FETCH_OP(xor, 2, uint16_t)
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SYNC_FETCH_OP(xor, 4, uint32_t)
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SYNC_FETCH_OP(xor, 8, uint64_t)
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SYNC_BOOL_CMP_EXCHANGE(1, uint8_t)
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SYNC_BOOL_CMP_EXCHANGE(2, uint16_t)
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SYNC_BOOL_CMP_EXCHANGE(4, uint32_t)
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SYNC_BOOL_CMP_EXCHANGE(8, uint64_t)
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SYNC_VAL_CMP_EXCHANGE(1, uint8_t)
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SYNC_VAL_CMP_EXCHANGE(2, uint16_t)
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SYNC_VAL_CMP_EXCHANGE(4, uint32_t)
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#endif // !HAS_ATOMICS_32
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#if !HAS_ATOMICS_64
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ATOMIC_LOAD(8, uint64_t)
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ATOMIC_STORE(8, uint64_t)
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ATOMIC_EXCHANGE(8, uint64_t)
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CMP_EXCHANGE(8, uint64_t)
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FETCH_ADD(8, uint64_t)
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FETCH_SUB(8, uint64_t)
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FETCH_AND(8, uint64_t)
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FETCH_OR(8, uint64_t)
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FETCH_XOR(8, uint64_t)
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SYNC_FETCH_OP(add, 8, uint64_t)
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SYNC_FETCH_OP(sub, 8, uint64_t)
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SYNC_FETCH_OP(and, 8, uint64_t)
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SYNC_FETCH_OP(or, 8, uint64_t)
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SYNC_FETCH_OP(xor, 8, uint64_t)
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SYNC_BOOL_CMP_EXCHANGE(8, uint64_t)
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SYNC_VAL_CMP_EXCHANGE(8, uint64_t)
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#endif
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#endif // !HAS_ATOMICS_64
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