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hal: avoid generate 8/16 bits intruction for register access

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This commit is contained in:
SalimTerryLi 2021-10-09 14:14:15 +08:00 committed by suda-morris
parent 5595042c16
commit 72bb572df1
78 changed files with 311 additions and 703 deletions
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3
.gitignore vendored
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@ -83,3 +83,6 @@ build
# lock files for examples and components
dependencies.lock
# managed_components for examples
managed_components

37
components/soc/include/hal/hal_defs.h
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@ -28,3 +28,40 @@
#define HAL_LOGV(...) ESP_LOGV(__VA_ARGS__)
#define STATIC_HAL_REG_CHECK(TAG, ENUM, VAL) _Static_assert((ENUM) == (VAL), #TAG" "#ENUM" definition no longer matches register value")
/**
* @brief Macro to force a 32-bit read, modify, then write on a peripheral register
*
* Due to a GCC bug, the compiler may still try to optimize read/writes to peripheral register fields by using 8/16 bit
* access, even if they are marked volatile (i.e., -fstrict-volatile-bitfields has no effect).
*
* For ESP chips, the peripheral bus only allows 32-bit read/writes. The following macro works around the compiler issue
* by forcing a 32-bit read/modify/write.
*
* @note This macro should only be called on register fields of xxx_struct.h type headers, as it depends on the presence
* of a 'val' field of the register union.
* @note Current implementation reads into a uint32_t instead of copy base_reg direclty to temp_reg. The reason being
* that C++ does not create a copy constructor for volatile structs.
*/
#define HAL_FORCE_MODIFY_U32_REG_FIELD(base_reg, reg_field, field_val) \
{ \
uint32_t temp_val = base_reg.val; \
typeof(base_reg) temp_reg; \
temp_reg.val = temp_val; \
temp_reg.reg_field = (field_val); \
(base_reg).val = temp_reg.val; \
}
/**
* @brief Macro to force a 32-bit read on a peripheral register
*
* @note This macro should only be called on register fields of xxx_struct.h type headers. See description above for
* more details.
* @note Current implementation reads into a uint32_t. See description above for more details.
*/
#define HAL_FORCE_READ_U32_REG_FIELD(base_reg, reg_field) ({ \
uint32_t temp_val = base_reg.val; \
typeof(base_reg) temp_reg; \
temp_reg.val = temp_val; \
temp_reg.reg_field; \
})

2
components/soc/soc/esp32/include/soc/emac_dma_struct.h
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@ -20,7 +20,7 @@ extern "C"
#include <stdint.h>
typedef volatile struct {
typedef volatile struct emac_dma_dev_s {
union {
struct {
uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit.*/

2
components/soc/soc/esp32/include/soc/emac_ext_struct.h
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@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct emac_ext_dev_s {
union {
struct {
uint32_t div_num : 4;

2
components/soc/soc/esp32/include/soc/emac_mac_struct.h
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@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct emac_mac_dev_s {
union {
struct {
uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/

2
components/soc/soc/esp32/include/soc/pcnt_struct.h
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@ -21,7 +21,7 @@ extern "C" {
#endif
typedef volatile struct pcnt_dev_s {
struct{
struct {
union {
struct {
uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/

2
components/soc/soc/esp32/include/soc/rmt_struct.h
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@ -24,7 +24,7 @@ typedef volatile struct rmt_dev_s {
uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.
Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
struct{
struct {
union {
struct {
uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/

37
components/soc/soc/esp32/include/soc/sdmmc_struct.h
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@ -23,18 +23,22 @@ extern "C" {
#endif
typedef struct sdmmc_desc_s {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
};
struct {
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
};
void* buffer1_ptr;
union {
void* buffer2_ptr;
@ -146,8 +150,10 @@ typedef volatile struct sdmmc_dev_s {
uint32_t val;
} ctype;
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t : 16;
struct {
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t reserved: 16;
};
uint32_t bytcnt; ///< number of bytes to be transferred
@ -326,6 +332,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t ces: 1; ///< card error summary
uint32_t reserved2: 2;
uint32_t nis: 1; ///< normal interrupt summary
uint32_t ais: 1; ///< abnormal interrupt summary
uint32_t fbe_code: 3; ///< code of fatal bus error
uint32_t fsm: 4; ///< DMAC FSM state
uint32_t reserved3: 15;
@ -362,6 +369,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes
uint32_t reserved1 : 13;
uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes
uint32_t reserved2 : 4;
};
uint32_t val;
} cardthrctl;
@ -378,6 +386,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
uint32_t reserved1 : 11;
};
uint32_t val;
} clock;

2
components/soc/soc/esp32/include/soc/timer_group_struct.h
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@ -21,7 +21,7 @@ extern "C" {
#endif
typedef volatile struct timg_dev_s {
struct{
struct {
union {
struct {
uint32_t reserved0: 10;

2
components/soc/soc/esp32/include/soc/twai_struct.h
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@ -178,7 +178,7 @@ typedef volatile struct twai_dev_s {
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/
//Misc Registers
union {

3
components/soc/soc/esp32/include/soc/uart_struct.h
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@ -23,8 +23,7 @@ extern "C" {
typedef volatile struct uart_dev_s {
union {
struct {
uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/
uint8_t reserved[3];
uint32_t rw_byte; /*This register stores one byte data read by rx fifo.*/
};
uint32_t val;
} fifo;

2
components/soc/soc/esp32/include/soc/uhci_struct.h
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@ -277,7 +277,7 @@ typedef volatile struct uhci_dev_s {
};
uint32_t val;
} quick_sent;
struct{
struct {
uint32_t w_data[2]; /*This register stores the content of short packet's dword*/
} q_data[7];
union {

2
components/soc/soc/esp32s2/include/soc/apb_ctrl_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_ctrl_dev_s {
union {
struct {
uint32_t pre_div: 10;

2
components/soc/soc/esp32s2/include/soc/apb_saradc_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force: 1;

2
components/soc/soc/esp32s2/include/soc/efuse_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0; /**/
union {
struct {

2
components/soc/soc/esp32s2/include/soc/gpio_sd_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_sd_dev_s {
union {
struct {
uint32_t duty: 8;

2
components/soc/soc/esp32s2/include/soc/gpio_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_dev_s {
uint32_t bt_select; /**/
uint32_t out; /**/
uint32_t out_w1ts; /**/

2
components/soc/soc/esp32s2/include/soc/hinf_struct.h
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@ -18,7 +18,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct hinf_dev_s {
union {
struct {
uint32_t user_id_fn1: 16;

2
components/soc/soc/esp32s2/include/soc/host_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct host_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;

2
components/soc/soc/esp32s2/include/soc/i2c_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2c_dev_s {
union {
struct {
uint32_t period: 14;

2
components/soc/soc/esp32s2/include/soc/i2s_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
union {

2
components/soc/soc/esp32s2/include/soc/ledc_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct ledc_dev_s {
struct {
struct {
union {

2
components/soc/soc/esp32s2/include/soc/mcp_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct mcp_dev_s {
union {
struct {
uint32_t in_done: 1;

2
components/soc/soc/esp32s2/include/soc/pcnt_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct pcnt_dev_s {
struct {
union {
struct {

19
components/soc/soc/esp32s2/include/soc/rmt_struct.h
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@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rmt_dev_s {
uint32_t data_ch[4]; /* Data FIFO, Can only be accessed by PeriBus2 */
struct {
union {
@ -299,23 +299,10 @@ typedef struct {
};
} rmt_item32_t;
typedef struct {
union {
struct {
uint16_t duration :15;
uint16_t level :1;
};
uint16_t val;
};
} rmt_item16_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct {
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[64];
rmt_item16_t data16[128];
};
rmt_item32_t data32[64];
} chan[4];
} rmt_mem_t;
extern rmt_mem_t RMTMEM;

2
components/soc/soc/esp32s2/include/soc/rtc_cntl_struct.h
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@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/

2
components/soc/soc/esp32s2/include/soc/rtc_i2c_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/

2
components/soc/soc/esp32s2/include/soc/rtc_io_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_io_dev_s {
union {
struct {
uint32_t reserved0: 10;

38
components/soc/soc/esp32s2/include/soc/sdmmc_pins.h
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@ -1,38 +0,0 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SDMMC_PINS_H_
#define _SOC_SDMMC_PINS_H_
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK 12
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD 11
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0 13
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1 14
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2 9
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3 10
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4 16
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5 17
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6 5
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7 18
#define SDMMC_SLOT0_FUNC 0
#define SDMMC_SLOT1_IOMUX_PIN_NUM_CLK 36
#define SDMMC_SLOT1_IOMUX_PIN_NUM_CMD 35
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D0 37
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D1 38
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D2 33
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D3 34
#define SDMMC_SLOT1_FUNC 3
#endif /* _SOC_SDMMC_PINS_H_ */

96
components/soc/soc/esp32s2/include/soc/sdmmc_reg.h
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@ -1,96 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SDMMC_REG_H_
#define _SOC_SDMMC_REG_H_
#include "soc.h"
#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00)
#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04)
#define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08)
#define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c)
#define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10)
#define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14)
#define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18)
#define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c)
#define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20)
#define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24)
#define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28)
#define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c)
#define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30)
#define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34)
#define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38)
#define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c)
#define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40)
#define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44)
#define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48)
#define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c)
#define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50)
#define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54)
#define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58)
#define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c)
#define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60)
#define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64)
#define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68)
#define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c)
#define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70)
#define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74)
#define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78)
#define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80)
#define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84)
#define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88)
#define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c)
#define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c)
#define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90)
#define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94)
#define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98)
#define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c)
#define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0)
#define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4)
#define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100)
#define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104)
#define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108)
#define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c)
#define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110)
#define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800)
#define SDMMC_INTMASK_IO_SLOT1 BIT(17)
#define SDMMC_INTMASK_IO_SLOT0 BIT(16)
#define SDMMC_INTMASK_EBE BIT(15)
#define SDMMC_INTMASK_ACD BIT(14)
#define SDMMC_INTMASK_SBE BIT(13)
#define SDMMC_INTMASK_HLE BIT(12)
#define SDMMC_INTMASK_FRUN BIT(11)
#define SDMMC_INTMASK_HTO BIT(10)
#define SDMMC_INTMASK_DTO BIT(9)
#define SDMMC_INTMASK_RTO BIT(8)
#define SDMMC_INTMASK_DCRC BIT(7)
#define SDMMC_INTMASK_RCRC BIT(6)
#define SDMMC_INTMASK_RXDR BIT(5)
#define SDMMC_INTMASK_TXDR BIT(4)
#define SDMMC_INTMASK_DATA_OVER BIT(3)
#define SDMMC_INTMASK_CMD_DONE BIT(2)
#define SDMMC_INTMASK_RESP_ERR BIT(1)
#define SDMMC_INTMASK_CD BIT(0)
#define SDMMC_IDMAC_INTMASK_AI BIT(9)
#define SDMMC_IDMAC_INTMASK_NI BIT(8)
#define SDMMC_IDMAC_INTMASK_CES BIT(5)
#define SDMMC_IDMAC_INTMASK_DU BIT(4)
#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
#define SDMMC_IDMAC_INTMASK_RI BIT(1)
#define SDMMC_IDMAC_INTMASK_TI BIT(0)
#endif /* _SOC_SDMMC_REG_H_ */

377
components/soc/soc/esp32s2/include/soc/sdmmc_struct.h
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@ -1,377 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SDMMC_STRUCT_H_
#define _SOC_SDMMC_STRUCT_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
void* buffer1_ptr;
union {
void* buffer2_ptr;
void* next_desc_ptr;
};
} sdmmc_desc_t;
#define SDMMC_DMA_MAX_BUF_LEN 4096
_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
typedef struct {
uint32_t cmd_index: 6; ///< Command index
uint32_t response_expect: 1; ///< set if response is expected
uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
uint32_t check_response_crc: 1; ///< set if controller should check response CRC
uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected
uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected)
uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected)
uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer
uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete
uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer
uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1)
uint32_t card_num: 5; ///< card number
uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers
uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device
uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device
uint32_t enable_boot: 1; ///< set for mandatory boot mode
uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern
uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot)
uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation
uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only)
uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register
uint32_t reserved: 1;
uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared.
} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values
_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
typedef volatile struct {
union {
struct {
uint32_t controller_reset: 1;
uint32_t fifo_reset: 1;
uint32_t dma_reset: 1;
uint32_t reserved1: 1;
uint32_t int_enable: 1;
uint32_t dma_enable: 1;
uint32_t read_wait: 1;
uint32_t send_irq_response: 1;
uint32_t abort_read_data: 1;
uint32_t send_ccsd: 1;
uint32_t send_auto_stop_ccsd: 1;
uint32_t ceata_device_interrupt_status: 1;
uint32_t reserved2: 4;
uint32_t card_voltage_a: 4;
uint32_t card_voltage_b: 4;
uint32_t enable_od_pullup: 1;
uint32_t use_internal_dma: 1;
uint32_t reserved3: 6;
};
uint32_t val;
} ctrl;
uint32_t pwren; ///< 1: enable power to card, 0: disable power to card
union {
struct {
uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
};
uint32_t val;
} clkdiv;
union {
struct {
uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3
uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3
uint32_t reserved: 28;
};
uint32_t val;
} clksrc;
union {
struct {
uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock
uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating
};
uint32_t val;
} clkena;
union {
struct {
uint32_t response: 8; ///< response timeout, in card output clock cycles
uint32_t data: 24; ///< data read timeout, in card output clock cycles
};
uint32_t val;
} tmout;
union {
struct {
uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode
uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored)
};
uint32_t val;
} ctype;
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t : 16;
uint32_t bytcnt; ///< number of bytes to be transferred
union {
struct {
uint32_t cd: 1; ///< Card detect interrupt enable
uint32_t re: 1; ///< Response error interrupt enable
uint32_t cmd_done: 1; ///< Command done interrupt enable
uint32_t dto: 1; ///< Data transfer over interrupt enable
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable
uint32_t rcrc: 1; ///< Response CRC error interrupt enable
uint32_t dcrc: 1; ///< Data CRC error interrupt enable
uint32_t rto: 1; ///< Response timeout interrupt enable
uint32_t drto: 1; ///< Data read timeout interrupt enable
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable
uint32_t hle: 1; ///< Hardware locked write error interrupt enable
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable
uint32_t acd: 1; ///< Auto command done interrupt enable
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable
uint32_t sdio: 16; ///< SDIO interrupt enable
};
uint32_t val;
} intmask;
uint32_t cmdarg; ///< Command argument to be passed to card
sdmmc_hw_cmd_t cmd;
uint32_t resp[4]; ///< Response from card
union {
struct {
uint32_t cd: 1; ///< Card detect interrupt masked status
uint32_t re: 1; ///< Response error interrupt masked status
uint32_t cmd_done: 1; ///< Command done interrupt masked status
uint32_t dto: 1; ///< Data transfer over interrupt masked status
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status
uint32_t rcrc: 1; ///< Response CRC error interrupt masked status
uint32_t dcrc: 1; ///< Data CRC error interrupt masked status
uint32_t rto: 1; ///< Response timeout interrupt masked status
uint32_t drto: 1; ///< Data read timeout interrupt masked status
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status
uint32_t hle: 1; ///< Hardware locked write error interrupt masked status
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status
uint32_t acd: 1; ///< Auto command done interrupt masked status
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status
uint32_t sdio: 16; ///< SDIO interrupt masked status
};
uint32_t val;
} mintsts;
union {
struct {
uint32_t cd: 1; ///< Card detect raw interrupt status
uint32_t re: 1; ///< Response error raw interrupt status
uint32_t cmd_done: 1; ///< Command done raw interrupt status
uint32_t dto: 1; ///< Data transfer over raw interrupt status
uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status
uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status
uint32_t rcrc: 1; ///< Response CRC error raw interrupt status
uint32_t dcrc: 1; ///< Data CRC error raw interrupt status
uint32_t rto: 1; ///< Response timeout raw interrupt status
uint32_t drto: 1; ///< Data read timeout raw interrupt status
uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status
uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status
uint32_t hle: 1; ///< Hardware locked write error raw interrupt status
uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status
uint32_t acd: 1; ///< Auto command done raw interrupt status
uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status
uint32_t sdio: 16; ///< SDIO raw interrupt status
};
uint32_t val;
} rintsts; ///< interrupts can be cleared by writing this register
union {
struct {
uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level
uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level
uint32_t fifo_empty: 1; ///< FIFO is empty
uint32_t fifo_full: 1; ///< FIFO is full
uint32_t cmd_fsm_state: 4; ///< command FSM state
uint32_t data3_status: 1; ///< this bit reads 1 if card is present
uint32_t data_busy: 1; ///< this bit reads 1 if card is busy
uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy
uint32_t response_index: 6; ///< index of the previous response
uint32_t fifo_count: 13; ///< number of filled locations in the FIFO
uint32_t dma_ack: 1; ///< DMA acknowledge signal
uint32_t dma_req: 1; ///< DMA request signal
};
uint32_t val;
} status;
union {
struct {
uint32_t tx_watermark: 12; ///< FIFO TX watermark level
uint32_t reserved1: 4;
uint32_t rx_watermark: 12; ///< FIFO RX watermark level
uint32_t dw_dma_mts: 3;
uint32_t reserved2: 1;
};
uint32_t val;
} fifoth;
union {
struct {
uint32_t cards: 2; ///< bit N reads 0 if card N is present
uint32_t reserved: 30;
};
uint32_t val;
} cdetect;
union {
struct {
uint32_t cards: 2; ///< bit N reads 1 if card N is write protected
uint32_t reserved: 30;
};
uint32_t val;
} wrtprt;
uint32_t gpio; ///< unused
uint32_t tcbcnt; ///< transferred (to card) byte count
uint32_t tbbcnt; ///< transferred from host to FIFO byte count
union {
struct {
uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms
uint32_t reserved: 8;
};
} debnce;
uint32_t usrid; ///< user ID
uint32_t verid; ///< IP block version
uint32_t hcon; ///< compile-time IP configuration
uint32_t uhs; ///< TBD
union {
struct {
uint32_t cards: 2; ///< bit N resets card N, active low
uint32_t reserved: 30;
};
} rst_n;
uint32_t reserved_7c;
union {
struct {
uint32_t sw_reset: 1; ///< set to reset DMA controller
uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers
uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors
uint32_t enable: 1; ///< set to enable IDMAC
uint32_t pbl: 3; ///< programmable burst length
uint32_t reserved: 21;
};
uint32_t val;
} bmod;
uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state
sdmmc_desc_t* dbaddr; ///< descriptor list base
union {
struct {
uint32_t ti: 1; ///< transmit interrupt status
uint32_t ri: 1; ///< receive interrupt status
uint32_t fbe: 1; ///< fatal bus error
uint32_t reserved1: 1;
uint32_t du: 1; ///< descriptor unavailable
uint32_t ces: 1; ///< card error summary
uint32_t reserved2: 2;
uint32_t nis: 1; ///< normal interrupt summary
uint32_t fbe_code: 3; ///< code of fatal bus error
uint32_t fsm: 4; ///< DMAC FSM state
uint32_t reserved3: 15;
};
uint32_t val;
} idsts;
union {
struct {
uint32_t ti: 1; ///< transmit interrupt enable
uint32_t ri: 1; ///< receive interrupt enable
uint32_t fbe: 1; ///< fatal bus error interrupt enable
uint32_t reserved1: 1;
uint32_t du: 1; ///< descriptor unavailable interrupt enable
uint32_t ces: 1; ///< card error interrupt enable
uint32_t reserved2: 2;
uint32_t ni: 1; ///< normal interrupt interrupt enable
uint32_t ai: 1; ///< abnormal interrupt enable
uint32_t reserved3: 22;
};
uint32_t val;
} idinten;
uint32_t dscaddr; ///< current host descriptor address
uint32_t dscaddrl; ///< unused
uint32_t dscaddru; ///< unused
uint32_t bufaddrl; ///< unused
uint32_t bufaddru; ///< unused
uint32_t reserved_a8[22];
uint32_t cardthrctl;
uint32_t back_end_power;
uint32_t uhs_reg_ext;
uint32_t emmc_ddr_reg;
uint32_t enable_shift;
uint32_t reserved_114[443];
union {
struct {
uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
uint32_t phase_din: 3; ///< phase of data input clock
uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
};
uint32_t val;
} clock;
} sdmmc_dev_t;
extern sdmmc_dev_t SDMMC;
_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
#ifdef __cplusplus
}
#endif
#endif //_SOC_SDMMC_STRUCT_H_

2
components/soc/soc/esp32s2/include/soc/sens_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct sens_dev_s {
union {
struct {
uint32_t sar1_clk_div: 8; /*clock divider*/

2
components/soc/soc/esp32s2/include/soc/slc_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct slc_dev_s {
union {
struct {
uint32_t slc0_tx_rst: 1;

2
components/soc/soc/esp32s2/include/soc/syscon_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct syscon_dev_s {
union {
struct {
uint32_t pre_div: 10;

2
components/soc/soc/esp32s2/include/soc/timer_group_struct.h
View File

@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct timg_dev_s {
struct {
union {
struct {

2
components/soc/soc/esp32s2/include/soc/twai_struct.h
View File

@ -178,7 +178,7 @@ typedef volatile struct twai_dev_s {
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/
//Misc Registers
union {

2
components/soc/soc/esp32s2/include/soc/uart_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte;/*note: rw_byte is a uint8_t field, however, ESP32-S2 do not support 8 bits read/write*/

2
components/soc/soc/esp32s2/include/soc/uhci_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uhci_dev_s {
union {
struct {
uint32_t in_rst: 1;

1
components/soc/soc/esp32s2/include/soc/usb_wrap_struct.h
View File

@ -153,6 +153,7 @@ typedef union {
* USB D- rx value in test.
*/
uint32_t test_rx_dm:1;
uint32_t reserved:25;
};
uint32_t val;
} usb_wrap_test_conf_reg_t;

35
components/soc/src/esp32/include/hal/adc_ll.h
View File

@ -2,7 +2,12 @@
#include "soc/adc_periph.h"
#include "hal/adc_types.h"
#include "soc/syscon_struct.h"
#include "soc/sens_struct.h"
#include "soc/rtc_io_struct.h"
#include "soc/rtc_cntl_struct.h"
#include <stdbool.h>
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -51,11 +56,11 @@ typedef enum {
static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
{
// Internal FSM reset wait time
SYSCON.saradc_fsm.rstb_wait = rst_wait;
HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, rstb_wait, rst_wait);
// Internal FSM start wait time
SYSCON.saradc_fsm.start_wait = start_wait;
HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, start_wait, start_wait);
// Internal FSM standby wait time
SYSCON.saradc_fsm.standby_wait = standby_wait;
HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, standby_wait, standby_wait);
}
/**
@ -66,7 +71,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
*/
static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
{
SYSCON.saradc_fsm.sample_cycle = sample_cycle;
HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, sample_cycle, sample_cycle);
}
/**
@ -77,7 +82,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
static inline void adc_ll_digi_set_clk_div(uint32_t div)
{
/* ADC clock divided from APB clk, e.g. 80 / 2 = 40Mhz, */
SYSCON.saradc_ctrl.sar_clk_div = div;
HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl, sar_clk_div, div);
}
/**
@ -98,7 +103,7 @@ static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format
*/
static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
{
SYSCON.saradc_ctrl2.max_meas_num = meas_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl2, max_meas_num, meas_num);
}
/**
@ -320,7 +325,7 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n, int channel)
static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
{
if (adc_n == ADC_NUM_1) {
while (SENS.sar_slave_addr1.meas_status != 0);
while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0);
SENS.sar_meas_start1.meas1_start_sar = 0;
SENS.sar_meas_start1.meas1_start_sar = 1;
} else { // adc_n == ADC_NUM_2
@ -359,9 +364,9 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
{
int ret_val = 0;
if (adc_n == ADC_NUM_1) {
ret_val = SENS.sar_meas_start1.meas1_data_sar;
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start1, meas1_data_sar);
} else { // adc_n == ADC_NUM_2
ret_val = SENS.sar_meas_start2.meas2_data_sar;
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start2, meas2_data_sar);
}
return ret_val;
}
@ -444,9 +449,9 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void)
static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
{
if (adc_n == ADC_NUM_1) {
SENS.sar_read_ctrl.sar1_clk_div = div;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div);
} else { // adc_n == ADC_NUM_2
SENS.sar_read_ctrl2.sar2_clk_div = div;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div);
}
}
@ -563,9 +568,9 @@ static inline void adc_ll_amp_disable(void)
SENS.sar_meas_ctrl.amp_rst_fb_fsm = 0;
SENS.sar_meas_ctrl.amp_short_ref_fsm = 0;
SENS.sar_meas_ctrl.amp_short_ref_gnd_fsm = 0;
SENS.sar_meas_wait1.sar_amp_wait1 = 1;
SENS.sar_meas_wait1.sar_amp_wait2 = 1;
SENS.sar_meas_wait2.sar_amp_wait3 = 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait1, 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait2, 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait2, sar_amp_wait3, 1);
}
/*---------------------------------------------------------------
@ -657,4 +662,4 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
#ifdef __cplusplus
}
#endif
#endif

9
components/soc/src/esp32/include/hal/dac_ll.h
View File

@ -20,8 +20,11 @@
#pragma once
#include "hal/hal_defs.h"
#include <stdlib.h>
#include "soc/dac_periph.h"
#include "soc/sens_struct.h"
#include "soc/rtc_io_struct.h"
#include "hal/dac_types.h"
#ifdef __cplusplus
@ -124,7 +127,7 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable)
static inline void dac_ll_cw_set_freq(uint32_t freq)
{
uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX;
SENS.sar_dac_ctrl1.sw_fstep = (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq);
}
/**
@ -171,12 +174,12 @@ static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_CW_PHASE_180) {
offset = 0 - offset;
}
SENS.sar_dac_ctrl2.dac_dc1 = offset ? offset : (-128 - offset);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset ? offset : (-128 - offset));
} else if (channel == DAC_CHANNEL_2) {
if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_CW_PHASE_180) {
offset = 0 - offset;
}
SENS.sar_dac_ctrl2.dac_dc2 = offset ? offset : (-128 - offset);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset ? offset : (-128 - offset));
}
}

18
components/soc/src/esp32/include/hal/gpio_ll.h
View File

@ -22,8 +22,10 @@
#pragma once
#include "hal/hal_defs.h"
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"
#include "hal/gpio_types.h"
@ -112,7 +114,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
*/
static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
*status = (core_id == 0) ? hw->pcpu_int1.intr : hw->acpu_int1.intr;
*status = (core_id == 0) ? HAL_FORCE_READ_U32_REG_FIELD(hw->pcpu_int1, intr) : HAL_FORCE_READ_U32_REG_FIELD(hw->acpu_int1, intr);
}
/**
@ -134,7 +136,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
*/
static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
{
hw->status1_w1tc.intr_st = mask;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->status1_w1tc, intr_st, mask);
}
/**
@ -197,7 +199,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
if (gpio_num < 32) {
hw->enable_w1tc = (0x1 << gpio_num);
} else {
hw->enable1_w1tc.data = (0x1 << (gpio_num - 32));
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1tc, data, (0x1 << (gpio_num - 32)));
}
// Ensure no other output signal is routed via GPIO matrix to this pin
@ -216,7 +218,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
if (gpio_num < 32) {
hw->enable_w1ts = (0x1 << gpio_num);
} else {
hw->enable1_w1ts.data = (0x1 << (gpio_num - 32));
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1ts, data, (0x1 << (gpio_num - 32)));
}
}
@ -255,13 +257,13 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32
if (gpio_num < 32) {
hw->out_w1ts = (1 << gpio_num);
} else {
hw->out1_w1ts.data = (1 << (gpio_num - 32));
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1ts, data, (1 << (gpio_num - 32)));
}
} else {
if (gpio_num < 32) {
hw->out_w1tc = (1 << gpio_num);
} else {
hw->out1_w1tc.data = (1 << (gpio_num - 32));
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1tc, data, (1 << (gpio_num - 32)));
}
}
}
@ -283,7 +285,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
if (gpio_num < 32) {
return (hw->in >> gpio_num) & 0x1;
} else {
return (hw->in1.data >> (gpio_num - 32)) & 0x1;
return (HAL_FORCE_READ_U32_REG_FIELD(hw->in1, data) >> (gpio_num - 32)) & 0x1;
}
}
@ -408,4 +410,4 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
#ifdef __cplusplus
}
#endif
#endif

2
components/soc/src/esp32/include/hal/i2c_ll.h
View File

@ -15,7 +15,9 @@
// The LL layer for I2C register operations
#pragma once
#include "hal/hal_defs.h"
#include "soc/i2c_periph.h"
#include "soc/i2c_struct.h"
#include "hal/i2c_types.h"
#ifdef __cplusplus

4
components/soc/src/esp32/include/hal/i2s_ll.h
View File

@ -22,11 +22,13 @@
#pragma once
#include "hal/hal_defs.h"
#include <stdbool.h>
#include "soc/rtc_periph.h"
#include "soc/rtc.h"
#include "soc/efuse_periph.h"
#include "soc/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "hal/i2s_types.h"
#ifdef __cplusplus
@ -453,7 +455,7 @@ static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val)
*/
static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val)
{
hw->clkm_conf.clkm_div_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, val);
}
/**

4
components/soc/src/esp32/include/hal/ledc_ll.h
View File

@ -17,8 +17,10 @@
#pragma once
#include "hal/hal_defs.h"
#include "hal/ledc_types.h"
#include "soc/ledc_periph.h"
#include "soc/ledc_struct.h"
#define LEDC_LL_GET_HW() &LEDC
@ -463,4 +465,4 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
#ifdef __cplusplus
}
#endif
#endif

5
components/soc/src/esp32/include/hal/mcpwm_ll.h
View File

@ -22,8 +22,9 @@
#pragma once
#include <soc/mcpwm_periph.h>
#include "hal/hal_defs.h"
#include "soc/mcpwm_periph.h"
#include "soc/mcpwm_struct.h"
#include "hal/mcpwm_types.h"
#include "soc/mcpwm_caps.h"
#include "hal/hal_defs.h"
@ -61,7 +62,7 @@ static inline void mcpwm_ll_init(mcpwm_dev_t *mcpwm)
*/
static inline void mcpwm_ll_set_clock_prescale(mcpwm_dev_t *mcpwm, int prescale)
{
mcpwm->clk_cfg.prescale = prescale;
HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->clk_cfg, prescale, prescale);
}
STATIC_HAL_REG_CHECK(MCPWM, MCPWM_LL_INTR_CAP0, MCPWM_CAP0_INT_RAW);

4
components/soc/src/esp32/include/hal/mwdt_ll.h
View File

@ -23,7 +23,9 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#include "hal/hal_defs.h"
#include "soc/timer_periph.h"
#include "soc/timer_group_struct.h"
#include "hal/wdt_types.h"
#include "esp_attr.h"
@ -201,7 +203,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
{
hw->wdt_config1.clk_prescale = prescaler;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config1, clk_prescale, prescaler);
}
/**

4
components/soc/src/esp32/include/hal/pcnt_ll.h
View File

@ -22,7 +22,9 @@
#pragma once
#include "hal/hal_defs.h"
#include "soc/pcnt_periph.h"
#include "soc/pcnt_struct.h"
#include "hal/pcnt_types.h"
#ifdef __cplusplus
@ -298,4 +300,4 @@ static inline void pcnt_ll_filter_disable(pcnt_dev_t *hw, pcnt_unit_t unit)
#ifdef __cplusplus
}
#endif
#endif

4
components/soc/src/esp32/include/hal/rtc_io_ll.h
View File

@ -21,7 +21,9 @@
#pragma once
#include <stdlib.h>
#include "hal/hal_defs.h"
#include "soc/rtc_io_periph.h"
#include "soc/rtc_io_struct.h"
#include "hal/rtc_io_types.h"
#include "hal/gpio_types.h"
@ -355,4 +357,4 @@ static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
#ifdef __cplusplus
}
#endif
#endif

2
components/soc/src/esp32/include/hal/rwdt_ll.h
View File

@ -23,8 +23,10 @@ extern "C" {
#include <stdlib.h>
#include <stdbool.h>
#include "hal/hal_defs.h"
#include "hal/wdt_types.h"
#include "soc/rtc_cntl_periph.h"
#include "soc/rtc_cntl_struct.h"
#include "esp_attr.h"
//Type check wdt_stage_action_t

4
components/soc/src/esp32/include/hal/sigmadelta_ll.h
View File

@ -22,7 +22,9 @@
#pragma once
#include <stdbool.h>
#include "hal/hal_defs.h"
#include "soc/sigmadelta_periph.h"
#include "soc/gpio_sd_struct.h"
#include "hal/sigmadelta_types.h"
#ifdef __cplusplus
@ -70,4 +72,4 @@ static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_chan
#ifdef __cplusplus
}
#endif
#endif

6
components/soc/src/esp32/include/hal/spi_flash_ll.h
View File

@ -23,7 +23,9 @@
#pragma once
#include <stdlib.h>
#include "hal/hal_defs.h"
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include <sys/param.h> // For MIN/MAX
@ -385,7 +387,7 @@ static inline void spi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
static inline void spi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
{
dev->user.usr_dummy = dummy_n ? 1 : 0;
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
}
static inline void spi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
@ -396,4 +398,4 @@ static inline void spi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_t
#ifdef __cplusplus
}
#endif
#endif

9
components/soc/src/esp32/include/hal/spi_ll.h
View File

@ -24,6 +24,7 @@
#include "hal/hal_defs.h"
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "esp32/rom/lldesc.h"
#include <string.h>
#include <esp_types.h>
@ -661,7 +662,7 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela
static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
{
hw->user.usr_dummy = dummy_n ? 1 : 0;
hw->user1.usr_dummy_cyclelen = dummy_n - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
}
/**
@ -819,13 +820,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
{
if (lsbfirst) {
// The output command start from bit0 to bit 15, kept as is.
hw->user2.usr_command_value = cmd;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd);
} else {
/* Output command will be sent from bit 7 to 0 of command_value, and
* then bit 15 to 8 of the same register field. Shift and swap to send
* more straightly.
*/
hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen));
}
}
@ -881,4 +882,4 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
#ifdef __cplusplus
}
#endif
#endif

2
components/soc/src/esp32/include/hal/timer_ll.h
View File

@ -24,6 +24,8 @@ extern "C" {
#include <stdlib.h>
#include "hal/timer_types.h"
#include "soc/timer_periph.h"
#include "soc/timer_group_struct.h"
#include "hal/hal_defs.h"
_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
_Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");

14
components/soc/src/esp32/include/hal/touch_sensor_ll.h
View File

@ -25,7 +25,11 @@
#include <stdlib.h>
#include <stdbool.h>
#include "soc/touch_sensor_periph.h"
#include "soc/sens_struct.h"
#include "soc/rtc_io_struct.h"
#include "soc/rtc_cntl_struct.h"
#include "hal/touch_sensor_types.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
@ -60,9 +64,9 @@ static inline touch_pad_t touch_ll_num_wrap(touch_pad_t touch_num)
static inline void touch_ll_set_meas_time(uint16_t meas_time)
{
//touch sensor measure time= meas_cycle / 8Mhz
SENS.sar_touch_ctrl1.touch_meas_delay = meas_time;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay, meas_time);
//the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
SENS.sar_touch_ctrl1.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_xpd_wait, SOC_TOUCH_PAD_MEASURE_WAIT);
}
/**
@ -72,7 +76,7 @@ static inline void touch_ll_set_meas_time(uint16_t meas_time)
*/
static inline void touch_ll_get_meas_time(uint16_t *meas_time)
{
*meas_time = SENS.sar_touch_ctrl1.touch_meas_delay;
*meas_time = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay);
}
/**
@ -86,7 +90,7 @@ static inline void touch_ll_get_meas_time(uint16_t *meas_time)
static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
{
//touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK( can be 150k or 32k depending on the options)
SENS.sar_touch_ctrl2.touch_sleep_cycles = sleep_time;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl2, touch_sleep_cycles, sleep_time);
}
/**
@ -96,7 +100,7 @@ static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
*/
static inline void touch_ll_get_sleep_time(uint16_t *sleep_time)
{
*sleep_time = SENS.sar_touch_ctrl1.touch_meas_delay;
*sleep_time = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay);
}
/**

8
components/soc/src/esp32/include/hal/twai_ll.h
View File

@ -31,6 +31,8 @@ extern "C" {
#include "sdkconfig.h"
#include "hal/twai_types.h"
#include "soc/twai_periph.h"
#include "soc/twai_struct.h"
#include "hal/hal_defs.h"
/* ------------------------- Defines and Typedefs --------------------------- */
@ -421,7 +423,7 @@ static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw)
*/
static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl)
{
hw->error_warning_limit_reg.ewl = ewl;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl);
}
/**
@ -461,7 +463,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
*/
static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
{
hw->rx_error_counter_reg.rxerr = rec;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec);
}
/* ------------------------ TX Error Count Register ------------------------- */
@ -489,7 +491,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw)
*/
static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
{
hw->tx_error_counter_reg.txerr = tec;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec);
}
/* ---------------------- Acceptance Filter Registers ----------------------- */

26
components/soc/src/esp32/include/hal/uart_ll.h
View File

@ -20,6 +20,8 @@
#include "esp_attr.h"
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "soc/uart_struct.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -210,7 +212,7 @@ FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
//Get the UART APB fifo addr
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2);
do {
fifo_cnt = hw->status.rxfifo_cnt;
fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
rxmem_sta.val = hw->mem_rx_status.val;
if(fifo_cnt != 0 || (rxmem_sta.rd_addr != rxmem_sta.wr_addr)) {
READ_PERI_REG(fifo_addr);
@ -248,7 +250,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
{
uint32_t fifo_cnt = hw->status.rxfifo_cnt;
uint32_t fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
typeof(hw->mem_rx_status) rx_status = hw->mem_rx_status;
uint32_t len = 0;
@ -274,7 +276,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
{
return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
return UART_LL_FIFO_DEF_LEN - HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt);
}
/**
@ -414,7 +416,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
{
if(break_num > 0) {
hw->idle_conf.tx_brk_num = break_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num);
hw->conf0.txd_brk = 1;
} else {
hw->conf0.txd_brk = 0;
@ -479,10 +481,10 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
if(sw_flow_ctrl_en) {
hw->flow_conf.xonoff_del = 1;
hw->flow_conf.sw_flow_con_en = 1;
hw->swfc_conf.xon_threshold = flow_ctrl->xon_thrd;
hw->swfc_conf.xoff_threshold = flow_ctrl->xoff_thrd;
hw->swfc_conf.xon_char = flow_ctrl->xon_char;
hw->swfc_conf.xoff_char = flow_ctrl->xoff_char;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_threshold, flow_ctrl->xon_thrd);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_threshold, flow_ctrl->xoff_thrd);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_char, flow_ctrl->xon_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_char, flow_ctrl->xoff_char);
} else {
hw->flow_conf.sw_flow_con_en = 0;
hw->flow_conf.xonoff_del = 0;
@ -504,8 +506,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
*/
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
{
hw->at_cmd_char.data = cmd_char->cmd_char;
hw->at_cmd_char.char_num = cmd_char->char_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout;
@ -703,8 +705,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
*/
FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
{
*cmd_char = hw->at_cmd_char.data;
*char_num = hw->at_cmd_char.char_num;
*cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
*char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
}
/**

30
components/soc/src/esp32s2/include/hal/adc_ll.h
View File

@ -7,7 +7,9 @@
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/sens_struct.h"
#include "regi2c_ctrl.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -83,11 +85,11 @@ typedef enum {
static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
{
// Internal FSM reset wait time
APB_SARADC.fsm_wait.rstb_wait = rst_wait;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait);
// Internal FSM start wait time
APB_SARADC.fsm_wait.xpd_wait = start_wait;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait);
// Internal FSM standby wait time
APB_SARADC.fsm_wait.standby_wait = standby_wait;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait);
}
/**
@ -115,7 +117,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
static inline void adc_ll_digi_set_clk_div(uint32_t div)
{
/* ADC clock devided from digital controller clock clk */
APB_SARADC.ctrl.sar_clk_div = div;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div);
}
/**
@ -136,7 +138,7 @@ static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format
*/
static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
{
APB_SARADC.ctrl2.max_meas_num = meas_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num);
}
/**
@ -307,7 +309,7 @@ static inline void adc_ll_digi_trigger_disable(void)
*/
static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
{
APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num);
APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b;
APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a;
}
@ -427,9 +429,9 @@ static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable)
static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n)
{
if (adc_n == ADC_NUM_1) {
return APB_SARADC.filter_status.adc1_filter_data;
return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc1_filter_data);
} else { // adc_n == ADC_NUM_2
return APB_SARADC.filter_status.adc2_filter_data;
return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc2_filter_data);
}
}
@ -595,7 +597,7 @@ static inline uint32_t adc_ll_digi_get_intr_status(adc_ll_num_t adc_n)
*/
static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
{
APB_SARADC.dma_conf.apb_adc_eof_num = num;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num);
}
/**
@ -710,7 +712,7 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n, int channel)
static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
{
if (adc_n == ADC_NUM_1) {
while (SENS.sar_slave_addr1.meas_status != 0);
while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0);
SENS.sar_meas1_ctrl2.meas1_start_sar = 0;
SENS.sar_meas1_ctrl2.meas1_start_sar = 1;
} else { // adc_n == ADC_NUM_2
@ -749,9 +751,9 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
{
int ret_val = 0;
if (adc_n == ADC_NUM_1) {
ret_val = SENS.sar_meas1_ctrl2.meas1_data_sar;
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas1_ctrl2, meas1_data_sar);
} else { // adc_n == ADC_NUM_2
ret_val = SENS.sar_meas2_ctrl2.meas2_data_sar;
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas2_ctrl2, meas2_data_sar);
}
return ret_val;
}
@ -906,9 +908,9 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void)
static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
{
if (adc_n == ADC_NUM_1) {
SENS.sar_reader1_ctrl.sar1_clk_div = div;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div);
} else { // adc_n == ADC_NUM_2
SENS.sar_reader2_ctrl.sar2_clk_div = div;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div);
}
}

11
components/soc/src/esp32s2/include/hal/dac_ll.h
View File

@ -25,6 +25,9 @@
#include "hal/dac_types.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/sens_struct.h"
#include "soc/rtc_io_struct.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -145,7 +148,7 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable)
static inline void dac_ll_cw_set_freq(uint32_t freq)
{
uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX;
SENS.sar_dac_ctrl1.sw_fstep = (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq;
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq);
}
/**
@ -192,12 +195,12 @@ static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_CW_PHASE_180) {
offset = 0 - offset;
}
SENS.sar_dac_ctrl2.dac_dc1 = offset ? offset : (-128 - offset);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset ? offset : (-128 - offset));
} else if (channel == DAC_CHANNEL_2) {
if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_CW_PHASE_180) {
offset = 0 - offset;
}
SENS.sar_dac_ctrl2.dac_dc2 = offset ? offset : (-128 - offset);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset ? offset : (-128 - offset));
}
}
@ -285,4 +288,4 @@ static inline void dac_ll_digi_reset(void)
#ifdef __cplusplus
}
#endif
#endif

4
components/soc/src/esp32s2/include/hal/gpio_ll.h
View File

@ -24,9 +24,11 @@
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"
#include "hal/gpio_types.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -419,4 +421,4 @@ static inline void gpio_ll_force_unhold_all(gpio_dev_t *hw)
#ifdef __cplusplus
}
#endif
#endif

4
components/soc/src/esp32s2/include/hal/gpspi_flash_ll.h
View File

@ -23,7 +23,9 @@
#pragma once
#include <stdlib.h>
#include "hal/hal_defs.h"
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include <sys/param.h> // For MIN/MAX
@ -343,7 +345,7 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
{
dev->user.usr_dummy = dummy_n ? 1 : 0;
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
}
/**

6
components/soc/src/esp32s2/include/hal/i2c_ll.h
View File

@ -16,7 +16,9 @@
#pragma once
#include "soc/i2c_periph.h"
#include "soc/i2c_struct.h"
#include "hal/i2c_types.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -493,7 +495,7 @@ static inline void i2c_ll_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
{
*setup_time = hw->scl_rstart_setup.time;
*hold_time = hw->scl_start_hold.time+1;
*hold_time = hw->scl_start_hold.time + 1;
}
/**
@ -888,4 +890,4 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
#ifdef __cplusplus
}
#endif
#endif

4
components/soc/src/esp32s2/include/hal/i2s_ll.h
View File

@ -24,7 +24,9 @@
#include <stdbool.h>
#include "soc/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "hal/i2s_types.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -416,7 +418,7 @@ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val)
{
hw->clkm_conf.clkm_div_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, val);
}
/**

4
components/soc/src/esp32s2/include/hal/ledc_ll.h
View File

@ -19,6 +19,8 @@
#include "hal/ledc_types.h"
#include "soc/ledc_periph.h"
#include "soc/ledc_struct.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -484,4 +486,4 @@ static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_m
#ifdef __cplusplus
}
#endif
#endif

4
components/soc/src/esp32s2/include/hal/mwdt_ll.h
View File

@ -24,8 +24,10 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#include "soc/timer_periph.h"
#include "soc/timer_group_struct.h"
#include "hal/wdt_types.h"
#include "esp_attr.h"
#include "hal/hal_defs.h"
//Type check wdt_stage_action_t
_Static_assert(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
@ -201,7 +203,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
{
hw->wdt_config1.clk_prescale = prescaler;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config1, clk_prescale, prescaler);
}
/**

4
components/soc/src/esp32s2/include/hal/pcnt_ll.h
View File

@ -23,7 +23,9 @@
#pragma once
#include "soc/pcnt_periph.h"
#include "soc/pcnt_struct.h"
#include "hal/pcnt_types.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -298,4 +300,4 @@ static inline void pcnt_ll_filter_disable(pcnt_dev_t *hw, pcnt_unit_t unit)
#ifdef __cplusplus
}
#endif
#endif

5
components/soc/src/esp32s2/include/hal/rtc_io_ll.h
View File

@ -23,7 +23,10 @@
#include <stdlib.h>
#include "soc/rtc_io_periph.h"
#include "hal/rtc_io_types.h"
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "hal/gpio_types.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -358,4 +361,4 @@ static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
#ifdef __cplusplus
}
#endif
#endif

4
components/soc/src/esp32s2/include/hal/rwdt_ll.h
View File

@ -25,8 +25,10 @@ extern "C" {
#include <stdbool.h>
#include "hal/wdt_types.h"
#include "soc/rtc_cntl_periph.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/efuse_reg.h"
#include "esp_attr.h"
#include "hal/hal_defs.h"
//Type check wdt_stage_action_t
_Static_assert(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
@ -239,7 +241,7 @@ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t* hw, bool enable
*/
FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width)
{
hw->wdt_config0.chip_reset_width = width;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config0, chip_reset_width, width);
}
/**

4
components/soc/src/esp32s2/include/hal/sigmadelta_ll.h
View File

@ -23,7 +23,9 @@
#include <stdbool.h>
#include "soc/sigmadelta_periph.h"
#include "soc/gpio_sd_struct.h"
#include "hal/sigmadelta_types.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -70,4 +72,4 @@ static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_chan
#ifdef __cplusplus
}
#endif
#endif

4
components/soc/src/esp32s2/include/hal/spi_flash_ll.h
View File

@ -23,7 +23,9 @@
#pragma once
#include "gpspi_flash_ll.h"
#include "soc/spi_struct.h"
#include "spimem_flash_ll.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -104,4 +106,4 @@ typedef union {
#ifdef __cplusplus
}
#endif
#endif

21
components/soc/src/esp32s2/include/hal/spi_ll.h
View File

@ -27,6 +27,7 @@
#include "hal/hal_defs.h"
#include "esp_types.h"
#include "soc/spi_periph.h"
#include "soc/spi_struct.h"
#include "esp32s2/rom/lldesc.h"
#ifdef __cplusplus
@ -431,10 +432,10 @@ static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode)
static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_mode)
{
if (io_mode == SPI_LL_IO_MODE_DIO || io_mode == SPI_LL_IO_MODE_DUAL) {
hw->ctrl.fcmd_dual= (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0;
hw->ctrl.faddr_dual= (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0;
hw->ctrl.fread_dual=1;
hw->user.fwrite_dual=1;
hw->ctrl.fcmd_dual = (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0;
hw->ctrl.faddr_dual = (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0;
hw->ctrl.fread_dual = 1;
hw->user.fwrite_dual = 1;
hw->ctrl.fcmd_quad = 0;
hw->ctrl.faddr_quad = 0;
hw->ctrl.fread_quad = 0;
@ -442,8 +443,8 @@ static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_
} else if (io_mode == SPI_LL_IO_MODE_QIO || io_mode == SPI_LL_IO_MODE_QUAD) {
hw->ctrl.fcmd_quad = (io_mode == SPI_LL_IO_MODE_QIO) ? 1 : 0;
hw->ctrl.faddr_quad = (io_mode == SPI_LL_IO_MODE_QIO) ? 1 : 0;
hw->ctrl.fread_quad=1;
hw->user.fwrite_quad=1;
hw->ctrl.fread_quad = 1;
hw->user.fwrite_quad = 1;
hw->ctrl.fcmd_dual = 0;
hw->ctrl.faddr_dual = 0;
hw->ctrl.fread_dual = 0;
@ -642,7 +643,7 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela
static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
{
hw->user.usr_dummy = dummy_n ? 1 : 0;
hw->user1.usr_dummy_cyclelen = dummy_n - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
}
/**
@ -803,13 +804,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
{
if (lsbfirst) {
// The output command start from bit0 to bit 15, kept as is.
hw->user2.usr_command_value = cmd;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd);
} else {
/* Output command will be sent from bit 7 to 0 of command_value, and
* then bit 15 to 8 of the same register field. Shift and swap to send
* more straightly.
*/
hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen));
}
}
@ -865,4 +866,4 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
#ifdef __cplusplus
}
#endif
#endif

4
components/soc/src/esp32s2/include/hal/spimem_flash_ll.h
View File

@ -27,7 +27,9 @@
#include <stdbool.h>
#include <string.h>
#include "hal/hal_defs.h"
#include "soc/spi_periph.h"
#include "soc/spi_mem_struct.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
@ -366,7 +368,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
{
dev->user.usr_dummy = dummy_n ? 1 : 0;
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
}
/**

1
components/soc/src/esp32s2/include/hal/systimer_ll.h
View File

@ -21,6 +21,7 @@ extern "C" {
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/systimer_reg.h"
#include "hal/hal_defs.h"
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions even no gcc optimization is applied.

2
components/soc/src/esp32s2/include/hal/timer_ll.h
View File

@ -24,6 +24,8 @@ extern "C" {
#include <stdlib.h>
#include "hal/timer_types.h"
#include "soc/timer_periph.h"
#include "soc/timer_group_struct.h"
#include "hal/hal_defs.h"
_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
_Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");

28
components/soc/src/esp32s2/include/hal/touch_sensor_ll.h
View File

@ -26,6 +26,10 @@
#include <stdbool.h>
#include "soc/touch_sensor_periph.h"
#include "hal/touch_sensor_types.h"
#include "soc/sens_struct.h"
#include "soc/rtc_io_struct.h"
#include "soc/rtc_cntl_struct.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -46,9 +50,9 @@ extern "C" {
static inline void touch_ll_set_meas_times(uint16_t meas_time)
{
//The times of charge and discharge in each measure process of touch channels.
RTCCNTL.touch_ctrl1.touch_meas_num = meas_time;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num, meas_time);
//the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT; //wait volt stable
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl2, touch_xpd_wait, SOC_TOUCH_PAD_MEASURE_WAIT); //wait volt stable
}
/**
@ -58,7 +62,7 @@ static inline void touch_ll_set_meas_times(uint16_t meas_time)
*/
static inline void touch_ll_get_measure_times(uint16_t *meas_time)
{
*meas_time = RTCCNTL.touch_ctrl1.touch_meas_num;
*meas_time = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num);
}
/**
@ -72,7 +76,7 @@ static inline void touch_ll_get_measure_times(uint16_t *meas_time)
static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
{
// touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK(90k)
RTCCNTL.touch_ctrl1.touch_sleep_cycles = sleep_time;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles, sleep_time);
}
/**
@ -82,7 +86,7 @@ static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
*/
static inline void touch_ll_get_sleep_time(uint16_t *sleep_time)
{
*sleep_time = RTCCNTL.touch_ctrl1.touch_sleep_cycles;
*sleep_time = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles);
}
/**
@ -989,7 +993,7 @@ static inline void touch_ll_proximity_get_channel_num(touch_pad_t prox_pad[])
*/
static inline void touch_ll_proximity_set_meas_times(uint32_t times)
{
RTCCNTL.touch_approach.touch_approach_meas_time = times;
HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time, times);
}
/**
@ -999,7 +1003,7 @@ static inline void touch_ll_proximity_set_meas_times(uint32_t times)
*/
static inline void touch_ll_proximity_get_meas_times(uint32_t *times)
{
*times = RTCCNTL.touch_approach.touch_approach_meas_time;
*times = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time);
}
/**
@ -1010,11 +1014,11 @@ static inline void touch_ll_proximity_get_meas_times(uint32_t *times)
static inline void touch_ll_proximity_read_meas_cnt(touch_pad_t touch_num, uint32_t *cnt)
{
if (SENS.sar_touch_conf.touch_approach_pad0 == touch_num) {
*cnt = SENS.sar_touch_appr_status.touch_approach_pad0_cnt;
*cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad0_cnt);
} else if (SENS.sar_touch_conf.touch_approach_pad1 == touch_num) {
*cnt = SENS.sar_touch_appr_status.touch_approach_pad1_cnt;
*cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad1_cnt);
} else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) {
*cnt = SENS.sar_touch_appr_status.touch_approach_pad2_cnt;
*cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad2_cnt);
}
}
@ -1162,7 +1166,7 @@ static inline void touch_ll_sleep_read_debounce(uint32_t *debounce)
*/
static inline void touch_ll_sleep_read_proximity_cnt(uint32_t *approach_cnt)
{
*approach_cnt = SENS.sar_touch_appr_status.touch_slp_approach_cnt;
*approach_cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_slp_approach_cnt);
}
/**
@ -1177,4 +1181,4 @@ static inline void touch_ll_get_wakeup_status(touch_pad_t *pad_num)
#ifdef __cplusplus
}
#endif
#endif

14
components/soc/src/esp32s2/include/hal/twai_ll.h
View File

@ -30,6 +30,8 @@ extern "C" {
#include <stdbool.h>
#include "hal/twai_types.h"
#include "soc/twai_periph.h"
#include "soc/twai_struct.h"
#include "hal/hal_defs.h"
/* ------------------------- Defines and Typedefs --------------------------- */
@ -406,7 +408,7 @@ static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw)
*/
static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl)
{
hw->error_warning_limit_reg.ewl = ewl;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl);
}
/**
@ -446,7 +448,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
*/
static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
{
hw->rx_error_counter_reg.rxerr = rec;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec);
}
/* ------------------------ TX Error Count Register ------------------------- */
@ -474,7 +476,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw)
*/
static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
{
hw->tx_error_counter_reg.txerr = tec;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec);
}
/* ---------------------- Acceptance Filter Registers ----------------------- */
@ -659,14 +661,14 @@ static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider)
{
if (divider >= 2 && divider <= 490) {
hw->clock_divider_reg.co = 0;
hw->clock_divider_reg.cd = (divider / 2) - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1);
} else if (divider == 1) {
//Setting the divider reg to max value (255) means a divider of 1
hw->clock_divider_reg.co = 0;
hw->clock_divider_reg.cd = 255;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255);
} else {
hw->clock_divider_reg.co = 1;
hw->clock_divider_reg.cd = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0);
}
}

24
components/soc/src/esp32s2/include/hal/uart_ll.h
View File

@ -19,7 +19,9 @@
#pragma once
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "esp_attr.h"
#include "soc/uart_struct.h"
#include "esp_attr.h"
#include "hal/hal_defs.h"
#ifdef __cplusplus
extern "C" {
@ -364,7 +366,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
{
if(break_num > 0) {
hw->idle_conf.tx_brk_num = break_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num);
hw->conf0.txd_brk = 1;
} else {
hw->conf0.txd_brk = 0;
@ -431,8 +433,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
hw->flow_conf.sw_flow_con_en = 1;
hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd;
hw->swfc_conf1.xon_char = flow_ctrl->xon_char;
hw->swfc_conf0.xoff_char = flow_ctrl->xoff_char;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char);
} else {
hw->flow_conf.sw_flow_con_en = 0;
hw->flow_conf.xonoff_del = 0;
@ -454,11 +456,11 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
*/
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
{
hw->at_cmd_char.data = cmd_char->cmd_char;
hw->at_cmd_char.char_num = cmd_char->char_num;
hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout);
}
/**
@ -653,8 +655,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
*/
FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
{
*cmd_char = hw->at_cmd_char.data;
*char_num = hw->at_cmd_char.char_num;
*cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
*char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
}
/**

1
components/soc/src/esp32s2/include/hal/usb_ll.h
View File

@ -17,6 +17,7 @@
#include "soc/system_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/usb_periph.h"
#include "soc/usb_wrap_struct.h"
static inline void usb_ll_int_phy_enable(void)
{