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fix(rmt): power up memory block

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morris 2024-06-20 23:46:21 +08:00
parent 8d34993193
commit 722ce211af
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GPG Key ID: FFB9C5DC0B9DF7A6
15 changed files with 240 additions and 125 deletions
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8
components/driver/deprecated/driver/rmt.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -152,10 +152,10 @@ esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t hi
esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en);
/**
* @brief Get RMT memory low power mode.
* @brief Check if the RMT memory is force powered down
*
* @param channel RMT channel
* @param pd_en Pointer to accept RMT memory low power mode.
* @param channel RMT channel (actually this function is configured for all channels)
* @param pd_en Pointer to accept the result
*
* @return
* - ESP_ERR_INVALID_ARG Parameter error

8
components/driver/deprecated/rmt_legacy.c
View File

@ -252,7 +252,11 @@ esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en)
{
ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
RMT_ENTER_CRITICAL();
rmt_ll_power_down_mem(rmt_contex.hal.regs, pd_en);
if (pd_en) {
rmt_ll_mem_force_power_off(rmt_contex.hal.regs);
} else {
rmt_ll_mem_power_by_pmu(rmt_contex.hal.regs);
}
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -261,7 +265,7 @@ esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en)
{
ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
RMT_ENTER_CRITICAL();
*pd_en = rmt_ll_is_mem_powered_down(rmt_contex.hal.regs);
*pd_en = rmt_ll_is_mem_force_powered_down(rmt_contex.hal.regs);
RMT_EXIT_CRITICAL();
return ESP_OK;
}

31
components/hal/esp32/include/hal/rmt_ll.h
View File

@ -88,14 +88,33 @@ static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
}
/**
* @brief Power down memory
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
* @param enable True to power down, False to power up
*/
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
{
dev->conf_ch[0].conf0.mem_pd = enable; // Only conf0 register of channel0 has `mem_pd`
(void)dev;
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
{
dev->conf_ch[0].conf0.mem_pd = 1;
}
/**
* @brief Power control the RMT memory block by the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
{
dev->conf_ch[0].conf0.mem_pd = 0;
}
/**
@ -120,7 +139,7 @@ static inline void rmt_ll_enable_mem_access_nonfifo(rmt_dev_t *dev, bool enable)
* @param divider_numerator Numerator part of the divider
*/
static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t src,
uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator)
uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator)
{
(void)divider_integral;
(void)divider_denominator;
@ -631,7 +650,7 @@ static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel
return dev->conf_ch[channel].conf1.idle_out_lv;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline bool rmt_ll_is_mem_force_powered_down(rmt_dev_t *dev)
{
// Only conf0 register of channel0 has `mem_pd`
return dev->conf_ch[0].conf0.mem_pd;

38
components/hal/esp32c3/include/hal/rmt_ll.h
View File

@ -87,15 +87,36 @@ static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
}
/**
* @brief Power down memory
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
* @param enable True to power down, False to power up
*/
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pu = !enable;
dev->sys_conf.mem_force_pd = enable;
dev->sys_conf.mem_force_pu = 1;
dev->sys_conf.mem_force_pd = 0;
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Power control the RMT memory block by the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 0;
dev->sys_conf.mem_force_pu = 0;
}
/**
@ -812,12 +833,9 @@ static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel
return dev->tx_conf[channel].idle_out_lv;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline bool rmt_ll_is_mem_force_powered_down(rmt_dev_t *dev)
{
// the RTC domain can also power down RMT memory
// so it's probably not enough to detect whether it's powered down or not
// mem_force_pd has higher priority than mem_force_pu
return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu);
return dev->sys_conf.mem_force_pd;
}
__attribute__((always_inline))

40
components/hal/esp32c5/include/hal/rmt_ll.h
View File

@ -79,15 +79,36 @@ static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
}
/**
* @brief Power down memory
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
* @param enable True to power down, False to power up
*/
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pu = !enable;
dev->sys_conf.mem_force_pd = enable;
PCR.rmt_pd_ctrl.rmt_mem_force_pu = 1;
PCR.rmt_pd_ctrl.rmt_mem_force_pd = 0;
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
{
PCR.rmt_pd_ctrl.rmt_mem_force_pd = 1;
PCR.rmt_pd_ctrl.rmt_mem_force_pu = 0;
}
/**
* @brief Power control the RMT memory block by the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
{
PCR.rmt_pd_ctrl.rmt_mem_force_pd = 0;
PCR.rmt_pd_ctrl.rmt_mem_force_pu = 0;
}
/**
@ -112,7 +133,7 @@ static inline void rmt_ll_enable_mem_access_nonfifo(rmt_dev_t *dev, bool enable)
* @param divider_numerator Numerator part of the divider
*/
static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t src,
uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator)
uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator)
{
// Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b)
(void)channel; // the source clock is set for all channels
@ -818,12 +839,9 @@ static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel
return dev->chnconf0[channel].idle_out_lv_chn;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline bool rmt_ll_is_mem_force_powered_down(rmt_dev_t *dev)
{
// the RTC domain can also power down RMT memory
// so it's probably not enough to detect whether it's powered down or not
// mem_force_pd has higher priority than mem_force_pu
return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu);
return PCR.rmt_pd_ctrl.rmt_mem_force_pd;
}
__attribute__((always_inline))

38
components/hal/esp32c6/include/hal/rmt_ll.h
View File

@ -82,15 +82,36 @@ static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
}
/**
* @brief Power down memory
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
* @param enable True to power down, False to power up
*/
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pu = !enable;
dev->sys_conf.mem_force_pd = enable;
dev->sys_conf.mem_force_pu = 1;
dev->sys_conf.mem_force_pd = 0;
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Power control the RMT memory block by the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 0;
dev->sys_conf.mem_force_pu = 0;
}
/**
@ -821,12 +842,9 @@ static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel
return dev->chnconf0[channel].idle_out_lv_chn;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline bool rmt_ll_is_mem_force_powered_down(rmt_dev_t *dev)
{
// the RTC domain can also power down RMT memory
// so it's probably not enough to detect whether it's powered down or not
// mem_force_pd has higher priority than mem_force_pu
return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu);
return dev->sys_conf.mem_force_pd;
}
__attribute__((always_inline))

38
components/hal/esp32h2/include/hal/rmt_ll.h
View File

@ -82,15 +82,36 @@ static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
}
/**
* @brief Power down memory
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
* @param enable True to power down, False to power up
*/
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pu = !enable;
dev->sys_conf.mem_force_pd = enable;
dev->sys_conf.mem_force_pu = 1;
dev->sys_conf.mem_force_pd = 0;
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Power control the RMT memory block by the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 0;
dev->sys_conf.mem_force_pu = 0;
}
/**
@ -815,12 +836,9 @@ static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel
return dev->chnconf0[channel].idle_out_lv_chn;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline bool rmt_ll_is_mem_force_powered_down(rmt_dev_t *dev)
{
// the RTC domain can also power down RMT memory
// so it's probably not enough to detect whether it's powered down or not
// mem_force_pd has higher priority than mem_force_pu
return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu);
return dev->sys_conf.mem_force_pd;
}
__attribute__((always_inline))

40
components/hal/esp32p4/include/hal/rmt_ll.h
View File

@ -87,7 +87,7 @@ static inline void rmt_ll_reset_register(int group_id)
* @param divider_numerator Numerator part of the divider
*/
static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t src,
uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator)
uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator)
{
(void)dev;
// Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b)
@ -145,15 +145,36 @@ static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
}
/**
* @brief Power down memory
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
* @param enable True to power down, False to power up
*/
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pu = !enable;
dev->sys_conf.mem_force_pd = enable;
dev->sys_conf.mem_force_pu = 1;
dev->sys_conf.mem_force_pd = 0;
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Power control the RMT memory block by the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 0;
dev->sys_conf.mem_force_pu = 0;
}
/**
@ -862,12 +883,9 @@ static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel
return dev->chnconf0[channel].idle_out_lv_chn;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline bool rmt_ll_is_mem_force_powered_down(rmt_dev_t *dev)
{
// the RTC domain can also power down RMT memory
// so it's probably not enough to detect whether it's powered down or not
// mem_force_pd has higher priority than mem_force_pu
return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu);
return dev->sys_conf.mem_force_pd;
}
__attribute__((always_inline))

38
components/hal/esp32s2/include/hal/rmt_ll.h
View File

@ -90,15 +90,36 @@ static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
}
/**
* @brief Power down memory
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
* @param enable True to power down, False to power up
*/
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
{
dev->apb_conf.mem_force_pu = !enable;
dev->apb_conf.mem_force_pd = enable;
dev->apb_conf.mem_force_pu = 1;
dev->apb_conf.mem_force_pd = 0;
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
{
dev->apb_conf.mem_force_pd = 1;
dev->apb_conf.mem_force_pu = 0;
}
/**
* @brief Power control the RMT memory block by the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
{
dev->apb_conf.mem_force_pd = 0;
dev->apb_conf.mem_force_pu = 0;
}
/**
@ -774,12 +795,9 @@ static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel
return dev->conf_ch[channel].conf1.idle_out_lv_chn;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline bool rmt_ll_is_mem_force_powered_down(rmt_dev_t *dev)
{
// the RTC domain can also power down RMT memory
// so it's probably not enough to detect whether it's powered down or not
// mem_force_pd has higher priority than mem_force_pu
return (dev->apb_conf.mem_force_pd) || !(dev->apb_conf.mem_force_pu);
return dev->apb_conf.mem_force_pd;
}
__attribute__((always_inline))

40
components/hal/esp32s3/include/hal/rmt_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -87,15 +87,36 @@ static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
}
/**
* @brief Power down memory
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
* @param enable True to power down, False to power up
*/
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pu = !enable;
dev->sys_conf.mem_force_pd = enable;
dev->sys_conf.mem_force_pu = 1;
dev->sys_conf.mem_force_pd = 0;
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Power control the RMT memory block by the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 0;
dev->sys_conf.mem_force_pu = 0;
}
/**
@ -850,12 +871,9 @@ static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel
return dev->chnconf0[channel].idle_out_lv_chn;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline bool rmt_ll_is_mem_force_powered_down(rmt_dev_t *dev)
{
// the RTC domain can also power down RMT memory
// so it's probably not enough to detect whether it's powered down or not
// mem_force_pd has higher priority than mem_force_pu
return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu);
return dev->sys_conf.mem_force_pd;
}
__attribute__((always_inline))

4
components/hal/rmt_hal.c
View File

@ -10,7 +10,7 @@
void rmt_hal_init(rmt_hal_context_t *hal)
{
hal->regs = &RMT;
rmt_ll_power_down_mem(hal->regs, false); // turn on RMTMEM power domain
rmt_ll_mem_power_by_pmu(hal->regs);
rmt_ll_enable_mem_access_nonfifo(hal->regs, true); // APB access the RMTMEM in nonfifo mode
rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interrupt events
rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX); // clear all pending events
@ -23,7 +23,7 @@ void rmt_hal_deinit(rmt_hal_context_t *hal)
{
rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interrupt events
rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX); // clear all pending events
rmt_ll_power_down_mem(hal->regs, true); // turn off RMTMEM power domain
rmt_ll_mem_force_power_off(hal->regs); // power off RMTMEM power domain forcefully
hal->regs = NULL;
}

36
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@ -168,11 +168,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6)
* }
* @endcode
*/
#if SOC_CLK_TREE_SUPPORTED
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
#else
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL}
#endif
/**
* @brief Type of GPTimer clock source
@ -181,11 +177,7 @@ typedef enum {
GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
#else
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
#endif // SOC_CLK_TREE_SUPPORTED
} soc_periph_gptimer_clk_src_t;
/**
@ -194,11 +186,7 @@ typedef enum {
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
#if SOC_CLK_TREE_SUPPORTED
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
#else
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Timer group clock source default choice is XTAL */
#endif // SOC_CLK_TREE_SUPPORTED
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
@ -257,11 +245,7 @@ typedef enum {
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
#if SOC_CLK_TREE_SUPPORTED
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
#else
UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< UART source clock default choice is XTAL for FPGA environment*/
#endif
} soc_periph_uart_clk_src_legacy_t;
/**
@ -293,11 +277,7 @@ typedef enum {
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_mcpwm_timer_clk_src_t;
/**
@ -311,11 +291,7 @@ typedef enum {
typedef enum {
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_mcpwm_capture_clk_src_t;
/**
@ -329,11 +305,7 @@ typedef enum {
typedef enum {
MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
@ -400,11 +372,7 @@ typedef enum {
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
#if SOC_CLK_TREE_SUPPORTED
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_80M as SPI source clock */
#else
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL_80M as SPI source clock */
#endif
} soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
@ -523,11 +491,7 @@ typedef enum {
PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */
#if SOC_CLK_TREE_SUPPORTED // TODO: [ESP32C5] IDF-8642 remove when clock tree is supported
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
#else
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_parlio_clk_src_t;
//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////

2
components/soc/esp32c5/include/soc/rmt_struct.h
View File

@ -827,7 +827,7 @@ typedef struct rmt_dev_t {
volatile struct {
rmt_chmconf0_reg_t conf0;
rmt_chmconf1_reg_t conf1;
} chmconf[2];;
} chmconf[2];
volatile rmt_chnstatus_reg_t chnstatus[2];
volatile rmt_chmstatus_reg_t chmstatus[2];
volatile rmt_int_raw_reg_t int_raw;

2
examples/get-started/blink/sdkconfig.defaults.esp32c5
View File

@ -1,2 +1,2 @@
CONFIG_BLINK_GPIO=6
CONFIG_BLINK_GPIO=27
CONFIG_BLINK_LED_STRIP=y

2
examples/peripherals/.build-test-rules.yml
View File

@ -299,12 +299,14 @@ examples/peripherals/rmt/ir_nec_transceiver:
examples/peripherals/rmt/musical_buzzer:
disable:
- if: SOC_RMT_SUPPORTED != 1
- if: SOC_RMT_SUPPORT_TX_LOOP_COUNT != 1
depends_components:
- esp_driver_rmt
examples/peripherals/rmt/stepper_motor:
disable:
- if: SOC_RMT_SUPPORTED != 1
- if: SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP != 1
depends_components:
- esp_driver_rmt