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refactor(usb/host): Make private hal types USB_DWC specific

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This commit is contained in:
Tomas Rezucha 2023-11-29 16:30:04 +08:00
parent 42277ac868
commit 71cd4df75a
8 changed files with 65 additions and 95 deletions
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14
components/hal/include/hal/usb_dwc_hal.h
View File

@ -22,7 +22,7 @@ NOTE: Thread safety is the responsibility fo the HAL user. All USB Host HAL
#include "soc/usb_dwc_struct.h"
#include "hal/usb_dwc_ll.h"
#endif
#include "hal/usb_types_private.h"
#include "hal/usb_dwc_types.h"
#include "hal/assert.h"
#if SOC_USB_OTG_SUPPORTED
@ -107,7 +107,7 @@ typedef enum {
typedef struct {
union {
struct {
usb_priv_xfer_type_t type: 2; /**< The type of endpoint */
usb_dwc_xfer_type_t type: 2; /**< The type of endpoint */
uint32_t bEndpointAddress: 8; /**< Endpoint address (containing endpoint number and direction) */
uint32_t mps: 11; /**< Maximum Packet Size */
uint32_t dev_addr: 8; /**< Device Address */
@ -138,9 +138,9 @@ typedef struct {
};
uint32_t val;
} flags; /**< Flags regarding channel's status and information */
usb_dwc_host_chan_regs_t *regs; /**< Pointer to the channel's register set */
usb_dwc_hal_chan_error_t error; /**< The last error that occurred on the channel */
usb_priv_xfer_type_t type; /**< The transfer type of the channel */
usb_dwc_host_chan_regs_t *regs; /**< Pointer to the channel's register set */
usb_dwc_hal_chan_error_t error; /**< The last error that occurred on the channel */
usb_dwc_xfer_type_t type; /**< The transfer type of the channel */
void *chan_ctx; /**< Context variable for the owner of the channel */
} usb_dwc_hal_chan_t;
@ -473,9 +473,9 @@ static inline bool usb_dwc_hal_port_check_if_connected(usb_dwc_hal_context_t *ha
* @note This function should only be called after confirming that a device is connected to the host port
*
* @param hal Context of the HAL layer
* @return usb_priv_speed_t Speed of the connected device
* @return usb_dwc_speed_t Speed of the connected device
*/
static inline usb_priv_speed_t usb_dwc_hal_port_get_conn_speed(usb_dwc_hal_context_t *hal)
static inline usb_dwc_speed_t usb_dwc_hal_port_get_conn_speed(usb_dwc_hal_context_t *hal)
{
return usb_dwc_ll_hprt_get_speed(hal->dev);
}

47
components/hal/include/hal/usb_dwc_ll.h
View File

@ -16,7 +16,7 @@ extern "C" {
#if SOC_USB_OTG_SUPPORTED
#include "soc/usb_dwc_struct.h"
#endif
#include "hal/usb_types_private.h"
#include "hal/usb_dwc_types.h"
#include "hal/misc.h"
@ -450,7 +450,7 @@ static inline void usb_dwc_ll_hcfg_set_fsls_pclk_sel(usb_dwc_dev_t *hw)
* @param hw Start address of the DWC_OTG registers
* @param speed Speed to initialize the host port at
*/
static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_priv_speed_t speed)
static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
{
hw->hcfg_reg.descdma = 1; //Enable scatt/gatt
hw->hcfg_reg.fslssupp = 1; //FS/LS support only
@ -459,13 +459,13 @@ static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_priv_spee
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
*/
hw->hcfg_reg.fslspclksel = (speed == USB_PRIV_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only
hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only
hw->hcfg_reg.perschedena = 0; //Disable perio sched
}
// ----------------------------- HFIR Register ---------------------------------
static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_priv_speed_t speed)
static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
{
usb_dwc_hfir_reg_t hfir;
hfir.val = hw->hfir_reg.val;
@ -475,7 +475,7 @@ static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_priv_spee
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
*/
hfir.frint = (speed == USB_PRIV_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS
hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS
hw->hfir_reg.val = hfir.val;
}
@ -558,21 +558,9 @@ static inline uint32_t usb_dwc_ll_hflbaddr_get_base_addr(usb_dwc_dev_t *hw)
// ----------------------------- HPRT Register ---------------------------------
static inline usb_priv_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw)
static inline usb_dwc_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw)
{
usb_priv_speed_t speed = USB_PRIV_SPEED_HIGH;
switch (hw->hprt_reg.prtspd) {
case 0:
speed = USB_PRIV_SPEED_HIGH;
break;
case 1:
speed = USB_PRIV_SPEED_FULL;
break;
case 2:
speed = USB_PRIV_SPEED_LOW;
break;
}
return speed;
return (usb_dwc_speed_t)hw->hprt_reg.prtspd;
}
static inline uint32_t usb_dwc_ll_hprt_get_test_ctl(usb_dwc_dev_t *hw)
@ -731,24 +719,9 @@ static inline void usb_dwc_ll_hcchar_set_dev_addr(volatile usb_dwc_host_chan_reg
chan->hcchar_reg.devaddr = addr;
}
static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_priv_xfer_type_t type)
static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_dwc_xfer_type_t type)
{
uint32_t ep_type;
switch (type) {
case USB_PRIV_XFER_TYPE_CTRL:
ep_type = 0;
break;
case USB_PRIV_XFER_TYPE_ISOCHRONOUS:
ep_type = 1;
break;
case USB_PRIV_XFER_TYPE_BULK:
ep_type = 2;
break;
default: //USB_PRIV_XFER_TYPE_INTR
ep_type = 3;
break;
}
chan->hcchar_reg.eptype = ep_type;
chan->hcchar_reg.eptype = (uint32_t)type;
}
//Indicates whether channel is commuunicating with a LS device connected via a FS hub. Setting this bit to 1 will cause
@ -773,7 +746,7 @@ static inline void usb_dwc_ll_hcchar_set_mps(volatile usb_dwc_host_chan_regs_t *
chan->hcchar_reg.mps = mps;
}
static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_priv_xfer_type_t type, bool is_in, bool is_ls)
static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_dwc_xfer_type_t type, bool is_in, bool is_ls)
{
//Sets all persistent fields of the channel over its lifetimez
usb_dwc_ll_hcchar_set_dev_addr(chan, dev_addr);

22
components/hal/include/hal/usb_types_private.h → components/hal/include/hal/usb_dwc_types.h
View File

@ -20,22 +20,26 @@ extern "C"
/**
* @brief USB speeds supported by the DWC OTG controller
*
* @note usb_dwc_speed_t enum values must match the values of the DWC_OTG prtspd register field
*/
typedef enum {
USB_PRIV_SPEED_HIGH,
USB_PRIV_SPEED_FULL,
USB_PRIV_SPEED_LOW,
} usb_priv_speed_t;
USB_DWC_SPEED_HIGH = 0,
USB_DWC_SPEED_FULL = 1,
USB_DWC_SPEED_LOW = 2,
} usb_dwc_speed_t;
/**
* @brief USB transfer types supported by the DWC OTG controller
*
* @note usb_dwc_xfer_type_t enum values must match the values of the DWC_OTG hcchar register field
*/
typedef enum {
USB_PRIV_XFER_TYPE_CTRL,
USB_PRIV_XFER_TYPE_ISOCHRONOUS,
USB_PRIV_XFER_TYPE_BULK,
USB_PRIV_XFER_TYPE_INTR,
} usb_priv_xfer_type_t;
USB_DWC_XFER_TYPE_CTRL = 0,
USB_DWC_XFER_TYPE_ISOCHRONOUS = 1,
USB_DWC_XFER_TYPE_BULK = 2,
USB_DWC_XFER_TYPE_INTR = 3,
} usb_dwc_xfer_type_t;
/**
* @brief Enumeration of different possible lengths of the periodic frame list

4
components/hal/include/hal/usb_phy_hal.h
View File

@ -7,7 +7,7 @@
#pragma once
#include <stdbool.h>
#include "usb_types_private.h"
#include "usb_dwc_types.h"
#include "usb_phy_types.h"
#include "soc/soc_caps.h"
#if SOC_USB_OTG_SUPPORTED
@ -72,7 +72,7 @@ void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal);
* @param hal Context of the HAL layer
* @param speed USB speed
*/
void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_priv_speed_t speed);
void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed);
/**
* @brief Enable/Disable test mode for internal PHY to mimick host-device disconnection

6
components/hal/usb_dwc_hal.c
View File

@ -193,7 +193,7 @@ static inline void debounce_lock_enable(usb_dwc_hal_context_t *hal)
void usb_dwc_hal_port_enable(usb_dwc_hal_context_t *hal)
{
usb_priv_speed_t speed = usb_dwc_ll_hprt_get_speed(hal->dev);
usb_dwc_speed_t speed = usb_dwc_ll_hprt_get_speed(hal->dev);
//Host Configuration
usb_dwc_ll_hcfg_set_defaults(hal->dev, speed);
//Configure HFIR
@ -238,7 +238,7 @@ bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan
void usb_dwc_hal_chan_free(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj)
{
if (chan_obj->type == USB_PRIV_XFER_TYPE_INTR || chan_obj->type == USB_PRIV_XFER_TYPE_ISOCHRONOUS) {
if (chan_obj->type == USB_DWC_XFER_TYPE_INTR || chan_obj->type == USB_DWC_XFER_TYPE_ISOCHRONOUS) {
//Unschedule this channel
for (int i = 0; i < hal->frame_list_len; i++) {
hal->periodic_frame_list[i] &= ~(1 << chan_obj->flags.chan_idx);
@ -271,7 +271,7 @@ void usb_dwc_hal_chan_set_ep_char(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t
//Save channel type
chan_obj->type = ep_char->type;
//If this is a periodic endpoint/channel, set its schedule in the frame list
if (ep_char->type == USB_PRIV_XFER_TYPE_ISOCHRONOUS || ep_char->type == USB_PRIV_XFER_TYPE_INTR) {
if (ep_char->type == USB_DWC_XFER_TYPE_ISOCHRONOUS || ep_char->type == USB_DWC_XFER_TYPE_INTR) {
HAL_ASSERT((int)ep_char->periodic.interval <= (int)hal->frame_list_len); //Interval cannot exceed the length of the frame list
//Find the effective offset in the frame list (in case the phase_offset_frames > interval)
int offset = ep_char->periodic.phase_offset_frames % ep_char->periodic.interval;

4
components/hal/usb_phy_hal.c
View File

@ -42,10 +42,10 @@ void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal)
usb_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true);
}
void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_priv_speed_t speed)
void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed)
{
// DEVICE - downstream
if (speed == USB_PRIV_SPEED_LOW) {
if (speed == USB_PHY_SPEED_LOW) {
// LS: dm_pu = 1
usb_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false);
} else {

54
components/usb/hcd_dwc.c
View File

@ -16,7 +16,7 @@
#include "esp_err.h"
#include "esp_log.h"
#include "hal/usb_dwc_hal.h"
#include "hal/usb_types_private.h"
#include "hal/usb_dwc_types.h"
#include "hcd.h"
#include "usb_private.h"
#include "usb/usb_types_ch9.h"
@ -373,7 +373,7 @@ static void _buffer_exec(pipe_t *pipe);
*/
static inline bool _buffer_check_done(pipe_t *pipe)
{
if (pipe->ep_char.type != USB_PRIV_XFER_TYPE_CTRL) {
if (pipe->ep_char.type != USB_DWC_XFER_TYPE_CTRL) {
return true;
}
// Only control transfers need to be continued
@ -731,12 +731,12 @@ static bool _internal_pipe_event_notify(pipe_t *pipe, bool from_isr)
// ----------------- Interrupt Handlers --------------------
static usb_speed_t speed_priv_to_public(usb_priv_speed_t priv)
static usb_speed_t get_usb_port_speed(usb_dwc_speed_t priv)
{
switch (priv) {
case USB_PRIV_SPEED_LOW: return USB_SPEED_LOW;
case USB_PRIV_SPEED_FULL: return USB_SPEED_FULL;
case USB_PRIV_SPEED_HIGH: return USB_SPEED_HIGH;
case USB_DWC_SPEED_LOW: return USB_SPEED_LOW;
case USB_DWC_SPEED_FULL: return USB_SPEED_FULL;
case USB_DWC_SPEED_HIGH: return USB_SPEED_HIGH;
default: abort();
}
}
@ -766,7 +766,7 @@ static hcd_port_event_t _intr_hdlr_hprt(port_t *port, usb_dwc_hal_port_event_t h
}
case USB_DWC_HAL_PORT_EVENT_ENABLED: {
usb_dwc_hal_port_enable(port->hal); // Initialize remaining host port registers
port->speed = speed_priv_to_public(usb_dwc_hal_port_get_conn_speed(port->hal));
port->speed = get_usb_port_speed(usb_dwc_hal_port_get_conn_speed(port->hal));
port->state = HCD_PORT_STATE_ENABLED;
port->flags.conn_dev_ena = 1;
// This was triggered by a command, so no event needs to be propagated.
@ -1407,7 +1407,7 @@ esp_err_t hcd_port_get_speed(hcd_port_handle_t port_hdl, usb_speed_t *speed)
HCD_ENTER_CRITICAL();
// Device speed is only valid if there is device connected to the port that has been reset
HCD_CHECK_FROM_CRIT(port->flags.conn_dev_ena, ESP_ERR_INVALID_STATE);
*speed = speed_priv_to_public(usb_dwc_hal_port_get_conn_speed(port->hal));
*speed = get_usb_port_speed(usb_dwc_hal_port_get_conn_speed(port->hal));
HCD_EXIT_CRITICAL();
return ESP_OK;
}
@ -1636,19 +1636,19 @@ static bool pipe_alloc_hcd_support_verification(const usb_ep_desc_t * ep_desc, c
static void pipe_set_ep_char(const hcd_pipe_config_t *pipe_config, usb_transfer_type_t type, bool is_default_pipe, int pipe_idx, usb_speed_t port_speed, usb_dwc_hal_ep_char_t *ep_char)
{
// Initialize EP characteristics
usb_priv_xfer_type_t hal_xfer_type;
usb_dwc_xfer_type_t hal_xfer_type;
switch (type) {
case USB_TRANSFER_TYPE_CTRL:
hal_xfer_type = USB_PRIV_XFER_TYPE_CTRL;
hal_xfer_type = USB_DWC_XFER_TYPE_CTRL;
break;
case USB_TRANSFER_TYPE_ISOCHRONOUS:
hal_xfer_type = USB_PRIV_XFER_TYPE_ISOCHRONOUS;
hal_xfer_type = USB_DWC_XFER_TYPE_ISOCHRONOUS;
break;
case USB_TRANSFER_TYPE_BULK:
hal_xfer_type = USB_PRIV_XFER_TYPE_BULK;
hal_xfer_type = USB_DWC_XFER_TYPE_BULK;
break;
default: // USB_TRANSFER_TYPE_INTR
hal_xfer_type = USB_PRIV_XFER_TYPE_INTR;
hal_xfer_type = USB_DWC_XFER_TYPE_INTR;
break;
}
ep_char->type = hal_xfer_type;
@ -1749,7 +1749,7 @@ static esp_err_t _pipe_cmd_flush(pipe_t *pipe)
// URBs were never executed, Update the actual_num_bytes and status
urb->transfer.actual_num_bytes = 0;
urb->transfer.status = (canceled) ? USB_TRANSFER_STATUS_CANCELED : USB_TRANSFER_STATUS_NO_DEVICE;
if (pipe->ep_char.type == USB_PRIV_XFER_TYPE_ISOCHRONOUS) {
if (pipe->ep_char.type == USB_DWC_XFER_TYPE_ISOCHRONOUS) {
// Update the URB's isoc packet descriptors as well
for (int pkt_idx = 0; pkt_idx < urb->transfer.num_isoc_packets; pkt_idx++) {
urb->transfer.isoc_packet_desc[pkt_idx].actual_num_bytes = 0;
@ -2198,11 +2198,11 @@ static void _buffer_fill(pipe_t *pipe)
int mps = pipe->ep_char.mps;
usb_transfer_t *transfer = &urb->transfer;
switch (pipe->ep_char.type) {
case USB_PRIV_XFER_TYPE_CTRL: {
case USB_DWC_XFER_TYPE_CTRL: {
_buffer_fill_ctrl(buffer_to_fill, transfer);
break;
}
case USB_PRIV_XFER_TYPE_ISOCHRONOUS: {
case USB_DWC_XFER_TYPE_ISOCHRONOUS: {
uint32_t start_idx;
if (pipe->multi_buffer_control.buffer_num_to_exec == 0) {
// There are no more previously filled buffers to execute. We need to calculate a new start index based on HFNUM and the pipe's schedule
@ -2228,11 +2228,11 @@ static void _buffer_fill(pipe_t *pipe)
_buffer_fill_isoc(buffer_to_fill, transfer, is_in, mps, (int)pipe->ep_char.periodic.interval, start_idx);
break;
}
case USB_PRIV_XFER_TYPE_BULK: {
case USB_DWC_XFER_TYPE_BULK: {
_buffer_fill_bulk(buffer_to_fill, transfer, is_in, mps);
break;
}
case USB_PRIV_XFER_TYPE_INTR: {
case USB_DWC_XFER_TYPE_INTR: {
_buffer_fill_intr(buffer_to_fill, transfer, is_in, mps);
break;
}
@ -2258,7 +2258,7 @@ static void _buffer_exec(pipe_t *pipe)
uint32_t start_idx;
int desc_list_len;
switch (pipe->ep_char.type) {
case USB_PRIV_XFER_TYPE_CTRL: {
case USB_DWC_XFER_TYPE_CTRL: {
start_idx = 0;
desc_list_len = XFER_LIST_LEN_CTRL;
// Set the channel's direction to OUT and PID to 0 respectively for the the setup stage
@ -2266,17 +2266,17 @@ static void _buffer_exec(pipe_t *pipe)
usb_dwc_hal_chan_set_pid(pipe->chan_obj, 0); // Setup stage always has a PID of DATA0
break;
}
case USB_PRIV_XFER_TYPE_ISOCHRONOUS: {
case USB_DWC_XFER_TYPE_ISOCHRONOUS: {
start_idx = buffer_to_exec->flags.isoc.start_idx;
desc_list_len = XFER_LIST_LEN_ISOC;
break;
}
case USB_PRIV_XFER_TYPE_BULK: {
case USB_DWC_XFER_TYPE_BULK: {
start_idx = 0;
desc_list_len = (buffer_to_exec->flags.bulk.zero_len_packet) ? XFER_LIST_LEN_BULK : 1;
break;
}
case USB_PRIV_XFER_TYPE_INTR: {
case USB_DWC_XFER_TYPE_INTR: {
start_idx = 0;
desc_list_len = (buffer_to_exec->flags.intr.zero_len_packet) ? buffer_to_exec->flags.intr.num_qtds + 1 : buffer_to_exec->flags.intr.num_qtds;
break;
@ -2297,7 +2297,7 @@ static void _buffer_exec(pipe_t *pipe)
static void _buffer_exec_cont(pipe_t *pipe)
{
// This should only ever be called on control transfers
assert(pipe->ep_char.type == USB_PRIV_XFER_TYPE_CTRL);
assert(pipe->ep_char.type == USB_DWC_XFER_TYPE_CTRL);
dma_buffer_block_t *buffer_inflight = pipe->buffers[pipe->multi_buffer_control.rd_idx];
bool next_dir_is_in;
int next_pid;
@ -2481,19 +2481,19 @@ static void _buffer_parse(pipe_t *pipe)
if (buffer_to_parse->status_flags.pipe_event == HCD_PIPE_EVENT_URB_DONE) {
// URB was successful
switch (pipe->ep_char.type) {
case USB_PRIV_XFER_TYPE_CTRL: {
case USB_DWC_XFER_TYPE_CTRL: {
_buffer_parse_ctrl(buffer_to_parse);
break;
}
case USB_PRIV_XFER_TYPE_ISOCHRONOUS: {
case USB_DWC_XFER_TYPE_ISOCHRONOUS: {
_buffer_parse_isoc(buffer_to_parse, is_in);
break;
}
case USB_PRIV_XFER_TYPE_BULK: {
case USB_DWC_XFER_TYPE_BULK: {
_buffer_parse_bulk(buffer_to_parse);
break;
}
case USB_PRIV_XFER_TYPE_INTR: {
case USB_DWC_XFER_TYPE_INTR: {
_buffer_parse_intr(buffer_to_parse, is_in, mps);
break;
}

9
components/usb/usb_phy.c
View File

@ -147,14 +147,7 @@ esp_err_t usb_phy_otg_dev_set_speed(usb_phy_handle_t handle, usb_phy_speed_t spe
USBPHY_TAG, "set speed not supported");
handle->otg_speed = speed;
usb_priv_speed_t hal_speed;
switch (speed) {
case USB_PHY_SPEED_LOW: hal_speed = USB_PRIV_SPEED_LOW; break;
case USB_PHY_SPEED_FULL: hal_speed = USB_PRIV_SPEED_FULL; break;
case USB_PHY_SPEED_HIGH: hal_speed = USB_PRIV_SPEED_HIGH; break;
default: abort();
}
usb_phy_hal_int_load_conf_dev(&(handle->hal_context), hal_speed);
usb_phy_hal_int_load_conf_dev(&(handle->hal_context), speed);
return ESP_OK;
}