Merge branch 'feat/c6lite_c61_final_helloworld' into 'master'

feat(esp32c61): birth and say hello world 🎄 (stage 8/8) Closes IDF-9290 See merge request espressif/esp-idf!29751
2024-10-05 20:47:46 -04:00 · 2024-04-02 14:11:36 +08:00 · 2024-04-02 14:11:36 +08:00 · 7116671f4d
commit 7116671f4d
parent 4989cc0d9f 20c18ac52b
57 changed files with 3414 additions and 319 deletions
--- a/.gitlab/ci/default-build-test-rules.yml
+++ b/.gitlab/ci/default-build-test-rules.yml
@ -7,11 +7,11 @@
 #
 # This file should ONLY be used during bringup. Should be reset to empty after the bringup process
 extra_default_build_targets:
- - esp32p4
+  - esp32p4

 bypass_check_test_targets:
  - esp32c5
-#  - esp32p4
+  - esp32c61
 #
 # These lines would
 # - enable the README.md check for esp32c6. Don't forget to add the build jobs in .gitlab/ci/build.yml
--- a/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32c61/bootloader.ld
@ -0,0 +1,255 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *
+ *  ESP32-C61 ROM static data usage is as follows:
+ *  - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
+ *
+ *  The 2nd stage bootloader can take space up to the end of ROM shared
+ *  buffers area (0x4087c610).
+ */
+
+/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+ * and work out iram_seg and iram_loader_seg addresses from there, backwards.
+ */
+
+/* These lengths can be adjusted, if necessary: */
+bootloader_usable_dram_end = 0x4084c9f0;
+bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
+bootloader_dram_seg_len = 0x5000;
+bootloader_iram_loader_seg_len = 0x7000;
+bootloader_iram_seg_len = 0x2500;
+
+/* Start of the lower region is determined by region size and the end of the higher region */
+bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
+bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
+bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
+bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
+  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
+  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
+}
+
+/* The app may use RAM for static allocations up to the start of iram_loader_seg.
+ * If you have changed something above and this assert fails:
+ * 1. Check what the new value of bootloader_iram_loader_seg start is.
+ * 2. Update the value in this assert.
+ * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c61/memory.ld.in to the same value.
+ */
+ASSERT(bootloader_iram_loader_seg_start == 0x4083E9F0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    /* we use either libgcc or compiler-rt, so put similar entries for them here */
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libclang_rt.builtins.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.bootdesc : ALIGN(0x10)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data_bootloader_desc .data_bootloader_desc.*)               /* Should be the first.  Bootloader version info.        DO NOT PUT ANYTHING BEFORE IT! */
+  } > dram_seg
+
+  .dram0.data :
+  {
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.sdata2 .sdata2.* .srodata .srodata.*)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+
+    /** CPU will try to prefetch up to 16 bytes of
+      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+      * safe access to up to 16 bytes after the last real instruction, add
+      * dummy bytes to ensure this
+      */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+}
+
+
+/** TODO: [ESP32C61] IDF-9405, update after rom freeze
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ * 0x4086ad08 ------------------> _dram0_0_start
+ *            |               |
+ *            |               |
+ *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
+ *            |               |
+ *            |               |
+ * 0x4087c610 ------------------> __stack_sentry
+ *            |               |
+ *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
+ *            |               |
+ * 0x4087e610 ------------------> __stack (pro cpu)
+ *            |               |
+ *            |               |
+ *            |               |   3. Shared memory only used in startup code or nonos/early boot*
+ *            |               |      (can be freed when IDF runs)
+ *            |               |
+ *            |               |
+ * 0x4087f564 ------------------> _dram0_rtos_reserved_start
+ *            |               |
+ *            |               |
+ *            |               |   4. Shared memory used in startup code and when IDF runs
+ *            |               |
+ *            |               |
+ * 0x4087fab0 ------------------> _dram0_rtos_reserved_end
+ *            |               |
+ * 0x4087fce8 ------------------> _data_start_interface
+ *            |               |
+ *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
+ *            |               |
+ * 0x40880000 ------------------> _data_end_interface
+ */
--- a/components/bootloader/subproject/main/ld/esp32c61/bootloader.rom.ld
+++ b/components/bootloader/subproject/main/ld/esp32c61/bootloader.rom.ld
@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* No definition for ESP32-C61 target */
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
@ -0,0 +1,283 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "string.h"
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp_rom_gpio.h"
+#include "esp32c61/rom/spi_flash.h"
+#include "soc/gpio_periph.h"
+#include "soc/spi_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/soc_caps.h"
+#include "flash_qio_mode.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_common.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_init.h"
+#include "hal/mmu_hal.h"
+#include "hal/mmu_ll.h"
+#include "hal/cache_hal.h"
+#include "hal/cache_ll.h"
+
+static const char *TAG __attribute__((unused))  = "boot.esp32c61";
+
+void bootloader_flash_update_id()
+{
+    esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
+    chip->device_id = bootloader_read_flash_id();
+}
+
+void bootloader_flash_update_size(uint32_t size)
+{
+    rom_spiflash_legacy_data->chip.chip_size = size;
+}
+
+void IRAM_ATTR bootloader_flash_cs_timing_config()
+{
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
+}
+
+void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
+{
+    uint32_t spi_clk_div = 0;
+    switch (pfhdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        spi_clk_div = 1;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        spi_clk_div = 2;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        spi_clk_div = 3;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+        spi_clk_div = 4;
+        break;
+    default:
+        break;
+    }
+    esp_rom_spiflash_config_clk(spi_clk_div, 0);
+}
+
+void IRAM_ATTR bootloader_configure_spi_pins(int drv)
+{
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
+    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
+}
+
+static void update_flash_config(const esp_image_header_t *bootloader_hdr)
+{
+    uint32_t size;
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        size = 1;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        size = 2;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        size = 4;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        size = 8;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        size = 16;
+        break;
+    default:
+        size = 2;
+    }
+    // Set flash chip size
+    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
+}
+
+static void print_flash_info(const esp_image_header_t *bootloader_hdr)
+{
+    ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
+    ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
+    ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
+    ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
+    ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
+
+    const char *str;
+    switch (bootloader_hdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        str = "80MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        str = "40MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        str = "26.7MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+    default:
+        str = "20MHz";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Speed      : %s", str);
+
+    /* SPI mode could have been set to QIO during boot already,
+       so test the SPI registers not the flash header */
+    esp_rom_spiflash_read_mode_t spi_mode = bootloader_flash_get_spi_mode();
+    switch (spi_mode) {
+    case ESP_ROM_SPIFLASH_QIO_MODE:
+        str = "QIO";
+        break;
+    case ESP_ROM_SPIFLASH_QOUT_MODE:
+        str = "QOUT";
+        break;
+    case ESP_ROM_SPIFLASH_DIO_MODE:
+        str = "DIO";
+        break;
+    case ESP_ROM_SPIFLASH_DOUT_MODE:
+        str = "DOUT";
+        break;
+    case ESP_ROM_SPIFLASH_FASTRD_MODE:
+        str = "FAST READ";
+        break;
+    default:
+        str = "SLOW READ";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Mode       : %s", str);
+
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        str = "1MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        str = "2MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        str = "4MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        str = "8MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        str = "16MB";
+        break;
+    default:
+        str = "2MB";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
+}
+
+static void IRAM_ATTR bootloader_init_flash_configure(void)
+{
+    bootloader_configure_spi_pins(1);
+    bootloader_flash_cs_timing_config();
+}
+
+static void bootloader_spi_flash_resume(void)
+{
+    bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
+    esp_rom_spiflash_wait_idle(&g_rom_flashchip);
+}
+
+esp_err_t bootloader_init_spi_flash(void)
+{
+    bootloader_init_flash_configure();
+    bootloader_spi_flash_resume();
+    bootloader_flash_unlock();
+
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+    bootloader_enable_qio_mode();
+#endif
+
+    print_flash_info(&bootloader_image_hdr);
+
+    cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+    update_flash_config(&bootloader_image_hdr);
+    cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+
+    //ensure the flash is write-protected
+    bootloader_enable_wp();
+    return ESP_OK;
+}
+
+#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr)
+{
+    esp_rom_spiflash_read_mode_t mode;
+    switch(pfhdr->spi_mode) {
+    case ESP_IMAGE_SPI_MODE_QIO:
+        mode = ESP_ROM_SPIFLASH_QIO_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_QOUT:
+        mode = ESP_ROM_SPIFLASH_QOUT_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_DIO:
+        mode = ESP_ROM_SPIFLASH_DIO_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_FAST_READ:
+        mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
+        break;
+    case ESP_IMAGE_SPI_MODE_SLOW_READ:
+        mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
+        break;
+    default:
+        mode = ESP_ROM_SPIFLASH_DIO_MODE;
+    }
+    esp_rom_spiflash_config_readmode(mode);
+}
+
+void bootloader_flash_hardware_init(void)
+{
+    esp_rom_spiflash_attach(0, false);
+
+    //init cache hal
+    cache_hal_init();
+    //init mmu
+    mmu_hal_init();
+    // update flash ID
+    bootloader_flash_update_id();
+    // Check and run XMC startup flow
+    esp_err_t ret = bootloader_flash_xmc_startup();
+    assert(ret == ESP_OK);
+
+    /* Alternative of bootloader_init_spi_flash */
+    // RAM app doesn't have headers in the flash. Make a default one for it.
+    esp_image_header_t WORD_ALIGNED_ATTR hdr = {
+        .spi_mode = ESP_IMAGE_SPI_MODE_DIO,
+        .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2,
+        .spi_size = ESP_IMAGE_FLASH_SIZE_2MB,
+    };
+
+    bootloader_configure_spi_pins(1);
+    bootloader_flash_set_spi_mode(&hdr);
+    bootloader_flash_clock_config(&hdr);
+    // TODO: set proper dummy output
+    bootloader_flash_cs_timing_config();
+
+    bootloader_spi_flash_resume();
+    bootloader_flash_unlock();
+
+    cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+    update_flash_config(&hdr);
+    cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+
+    //ensure the flash is write-protected
+    bootloader_enable_wp();
+}
+#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
--- a/components/bootloader_support/src/bootloader_clock_init.c
+++ b/components/bootloader_support/src/bootloader_clock_init.c
@ -9,7 +9,7 @@
 #include "soc/chip_revision.h"
 #include "hal/efuse_hal.h"

-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-5645
+#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 &&! CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-5645
 #include "soc/rtc_cntl_reg.h"
 #else
 #include "soc/lp_wdt_reg.h"
@ -66,7 +66,8 @@ __attribute__((weak)) void bootloader_clock_configure(void)
        }
 #endif

-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
+//TODO: [ESP32C61] IDF-9274, basic rtc support
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
        // TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue
        // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
        clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
@ -93,8 +94,8 @@ __attribute__((weak)) void bootloader_clock_configure(void)
 #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL

 // TODO: IDF-8938 Need refactor! Does not belong to clock configuration.
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
-#if CONFIG_IDF_TARGET_ESP32C5
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 #define LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG            LP_ANA_LP_INT_ENA_REG
 #define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA      LP_ANA_BOD_MODE0_LP_INT_ENA
 #define LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG            LP_ANA_LP_INT_CLR_REG
--- a/components/bootloader_support/src/bootloader_efuse.c
+++ b/components/bootloader_support/src/bootloader_efuse.c
@ -30,6 +30,9 @@ int bootloader_clock_get_rated_freq_mhz(void)
 #elif CONFIG_IDF_TARGET_ESP32C6
    return 160;

+#elif CONFIG_IDF_TARGET_ESP32C61    //TODO: [ESP32C61] IDF-9282
+    return 160;
+
 #elif CONFIG_IDF_TARGET_ESP32C5
    return 160;

--- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
+++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
@ -0,0 +1,179 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp_image_format.h"
+#include "flash_qio_mode.h"
+#include "esp_rom_gpio.h"
+#include "esp_rom_uart.h"
+#include "esp_rom_sys.h"
+#include "esp_rom_spiflash.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/io_mux_reg.h"
+#include "soc/assist_debug_reg.h"
+#include "esp_cpu.h"
+#include "soc/rtc.h"
+#include "soc/spi_periph.h"
+#include "soc/cache_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/pcr_reg.h"
+#include "esp32c61/rom/ets_sys.h"
+#include "esp32c61/rom/spi_flash.h"
+#include "bootloader_common.h"
+#include "bootloader_init.h"
+#include "bootloader_clock.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_mem.h"
+#include "esp_private/regi2c_ctrl.h"
+#include "soc/regi2c_lp_bias.h"
+#include "soc/regi2c_bias.h"
+#include "bootloader_console.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_soc.h"
+#include "esp_private/bootloader_flash_internal.h"
+#include "esp_efuse.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "soc/lp_wdt_reg.h"
+#include "hal/efuse_hal.h"
+#include "hal/lpwdt_ll.h"
+
+static const char *TAG = "boot.esp32c61";
+
+static void wdt_reset_cpu0_info_enable(void)
+{
+    REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
+    REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
+    REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
+}
+
+static void wdt_reset_info_dump(int cpu)
+{
+    (void) cpu;
+    // saved PC was already printed by the ROM bootloader.
+    // nothing to do here.
+}
+
+static void bootloader_check_wdt_reset(void)
+{
+    int wdt_rst = 0;
+    soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
+    if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
+        rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
+        ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
+        wdt_rst = 1;
+    }
+    if (wdt_rst) {
+        // if reset by WDT dump info from trace port
+        wdt_reset_info_dump(0);
+    }
+    wdt_reset_cpu0_info_enable();
+}
+
+static void bootloader_super_wdt_auto_feed(void)
+{
+    REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE);
+    REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
+    REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
+}
+
+static inline void bootloader_hardware_init(void)
+{
+    // In 80MHz flash mode, ROM sets the mspi module clk divider to 2, fix it here
+#if CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_APP_BUILD_TYPE_RAM
+    clk_ll_mspi_fast_set_hs_divider(6);
+    esp_rom_spiflash_config_clk(1, 0);
+    esp_rom_spiflash_config_clk(1, 1);
+    esp_rom_spiflash_fix_dummylen(0, 1);
+    esp_rom_spiflash_fix_dummylen(1, 1);
+#endif
+
+//TODO: [ESP32C61] IDF-9276
+#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+    ESP_EARLY_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!");
+#else
+    ESP_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!");
+#endif
+}
+
+static inline void bootloader_ana_reset_config(void)
+{
+    //Enable super WDT reset.
+    bootloader_ana_super_wdt_reset_config(true);
+    //Enable BOD reset
+    bootloader_ana_bod_reset_config(true);
+}
+
+esp_err_t bootloader_init(void)
+{
+    esp_err_t ret = ESP_OK;
+    bootloader_hardware_init();
+    // bootloader_ana_reset_config();   //TODO: [ESP32C61] IDF-9260
+    bootloader_super_wdt_auto_feed();
+
+// In RAM_APP, memory will be initialized in `call_start_cpu0`
+#if !CONFIG_APP_BUILD_TYPE_RAM
+    // protect memory region
+    bootloader_init_mem();
+    /* check that static RAM is after the stack */
+    assert(&_bss_start <= &_bss_end);
+    assert(&_data_start <= &_data_end);
+    // clear bss section
+    bootloader_clear_bss_section();
+#endif // !CONFIG_APP_BUILD_TYPE_RAM
+
+    // init eFuse virtual mode (read eFuses to RAM)
+#ifdef CONFIG_EFUSE_VIRTUAL
+    ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
+#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    esp_efuse_init_virtual_mode_in_ram();
+#endif
+#endif
+    // config clock
+    bootloader_clock_configure();
+    // initialize console, from now on, we can use esp_log
+    bootloader_console_init();
+    /* print 2nd bootloader banner */
+    bootloader_print_banner();
+
+#if !CONFIG_APP_BUILD_TYPE_RAM
+    //init cache hal
+    cache_hal_init();
+    //init mmu
+    mmu_hal_init();
+    // update flash ID
+    bootloader_flash_update_id();
+    // Check and run XMC startup flow
+    if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
+        ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
+        return ret;
+    }
+    // read bootloader header
+    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
+        return ret;
+    }
+    // read chip revision and check if it's compatible to bootloader
+    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
+        return ret;
+    }
+    // initialize spi flash
+    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
+        return ret;
+    }
+#endif // !CONFIG_APP_BUILD_TYPE_RAM
+
+    // check whether a WDT reset happened
+    bootloader_check_wdt_reset();
+    // config WDT
+    bootloader_config_wdt();
+    // enable RNG early entropy source
+    bootloader_enable_random();
+
+    return ret;
+}
--- a/components/bootloader_support/src/esp32c61/bootloader_sha.c
+++ b/components/bootloader_support/src/esp32c61/bootloader_sha.c
@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "bootloader_sha.h"
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+#include <sys/param.h>
+
+#include "esp32c61/rom/sha.h"
+
+static SHA_CTX ctx;
+
+//TODO: [ESP32C61] IDF-9234
+
+bootloader_sha256_handle_t bootloader_sha256_start()
+{
+    // Enable SHA hardware
+    ets_sha_enable();
+    ets_sha_init(&ctx, SHA2_256);
+    return &ctx; // Meaningless non-NULL value
+}
+
+void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
+{
+    assert(handle != NULL);
+    /* C61 secure boot key field consists of 1 byte of curve identifier and 64 bytes of ECDSA public key.
+     * While verifying the signature block, we need to calculate the SHA of this key field which is of 65 bytes.
+     * ets_sha_update handles it cleanly so we can safely remove the check:
+     * assert(data_len % 4) == 0
+     */
+    ets_sha_update(&ctx, data, data_len, false);
+}
+
+void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
+{
+    assert(handle != NULL);
+
+    if (digest == NULL) {
+        bzero(&ctx, sizeof(ctx));
+        return;
+    }
+    ets_sha_finish(&ctx, digest);
+}
--- a/components/bootloader_support/src/esp32c61/bootloader_soc.c
+++ b/components/bootloader_support/src/esp32c61/bootloader_soc.c
@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "soc/soc.h"
+#include "soc/lp_analog_peri_reg.h"
+
+//TODO: [ESP32C61] IDF-9260, commented in verify code, check
+
+void bootloader_ana_super_wdt_reset_config(bool enable)
+{
+    //C61 doesn't support bypass super WDT reset
+    assert(enable);
+    // lp_analog_peri_reg.h updated, now following registers
+    // REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
+}
+
+void bootloader_ana_bod_reset_config(bool enable)
+{
+    // lp_analog_peri_reg.h updated, now following registers
+    // REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
+
+    if (enable) {
+        REG_SET_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA);
+    } else {
+        REG_CLR_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA);
+    }
+}
+
+//Not supported but common bootloader calls the function. Do nothing
+void bootloader_ana_clock_glitch_reset_config(bool enable)
+{
+    (void)enable;
+}
--- a/components/bootloader_support/src/esp32c61/flash_encryption_secure_features.c
+++ b/components/bootloader_support/src/esp32c61/flash_encryption_secure_features.c
@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "flash_encrypt";
+
+esp_err_t esp_flash_encryption_enable_secure_features(void)
+{
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
+    ESP_LOGI(TAG, "Disable UART bootloader encryption...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
+#endif
+
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
+    ESP_LOGI(TAG, "Disable UART bootloader cache...");
+    esp_efuse_write_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
+#endif
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
+
+#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)
+    // This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot
+    // otherwise the Flash Encryption key cannot be read protected
+    esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
+#endif
+
+#ifndef CONFIG_SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE
+    // Set write-protection for DIS_ICACHE to prevent bricking chip in case it will be set accidentally.
+    // esp32c61 has DIS_ICACHE. Write-protection bit = 2.
+    // List of eFuses with the same write protection bit:
+    // SWAP_UART_SDIO_EN, DIS_ICACHE, DIS_USB_JTAG, DIS_DOWNLOAD_ICACHE,
+    // DIS_USB_SERIAL_JTAG, DIS_FORCE_DOWNLOAD, DIS_TWAI, JTAG_SEL_ENABLE,
+    // DIS_PAD_JTAG, DIS_DOWNLOAD_MANUAL_ENCRYPT.
+    esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_ICACHE);
+#endif
+
+    return ESP_OK;
+}
--- a/components/bootloader_support/src/flash_encrypt.c
+++ b/components/bootloader_support/src/flash_encrypt.c
@ -13,6 +13,8 @@
 #include "esp_secure_boot.h"
 #include "hal/efuse_hal.h"

+//TODO:[ESP32C61] IDf-9232
+
 #if CONFIG_IDF_TARGET_ESP32
 #define CRYPT_CNT ESP_EFUSE_FLASH_CRYPT_CNT
 #define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT
--- a/components/esp_hw_support/CMakeLists.txt
+++ b/components/esp_hw_support/CMakeLists.txt
@ -26,11 +26,11 @@ if(NOT BOOTLOADER_BUILD)
                     "periph_ctrl.c"
                     "revision.c"
                     "rtc_module.c"
+                     "sleep_modem.c"
                     "sleep_modes.c"
                     "sleep_console.c"
                     "sleep_gpio.c"
                     "sleep_event.c"
-                     "sleep_modem.c"
                     "regi2c_ctrl.c"
                     "esp_gpio_reserve.c"
                     "sar_periph_ctrl_common.c"
@ -158,6 +158,16 @@ if(NOT BOOTLOADER_BUILD)
                "port/esp_clk_tree_common.c"    # TODO: [ESP32C5] IDF-8638, IDF-8640
            )
    endif()
+    if(CONFIG_IDF_TARGET_ESP32C61)  # TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-9248
+        list(REMOVE_ITEM srcs
+                "sleep_cpu.c"
+                "sleep_modem.c"
+                "sleep_modes.c"
+                "sleep_wake_stub.c"
+                "sleep_gpio.c"
+                "port/esp_clk_tree_common.c"
+            )
+    endif()
 else()
    # Requires "_esp_error_check_failed()" function
    list(APPEND priv_requires "esp_system")
--- a/components/esp_hw_support/cpu.c
+++ b/components/esp_hw_support/cpu.c
@ -11,7 +11,7 @@
 #include "soc/soc_caps.h"

 // TODO: IDF-5645
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 #include "soc/lp_aon_reg.h"
 #include "soc/pcr_reg.h"
 #define SYSTEM_CPU_PER_CONF_REG PCR_CPU_WAITI_CONF_REG
@ -87,7 +87,7 @@ void esp_cpu_unstall(int core_id)
    CLEAR_PERI_REG_MASK(PMU_CPU_SW_STALL_REG, pmu_core_stall_mask);
 #else
    /*
-    We need to write clear the value "0x86" to unstall a particular core. The location of this value is split into
+    We need to write clear the value "0x86" to uninstall a particular core. The location of this value is split into
    two separate bit fields named "c0" and "c1", and the two fields are located in different registers. Each core has
    its own pair of "c0" and "c1" bit fields.

@ -112,7 +112,7 @@ void esp_cpu_reset(int core_id)
    else
        REG_SET_BIT(LP_CLKRST_HPCPU_RESET_CTRL0_REG, LP_CLKRST_HPCORE1_SW_RESET);
 #else
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-5645
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-5645
    SET_PERI_REG_MASK(LP_AON_CPUCORE0_CFG_REG, LP_AON_CPU_CORE0_SW_RESET);
 #else
    assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM);
@ -307,7 +307,7 @@ bool esp_cpu_compare_and_set(volatile uint32_t *addr, uint32_t compare_value, ui
        // Release the external RAM CAS lock
        external_ram_cas_lock = 0;
 exit:
-        // Reenable interrupts
+        // Re-enable interrupts
        __asm__ __volatile__ ("memw \n"
                              "wsr %0, ps\n"
                              :: "r"(intr_level));
--- a/components/esp_hw_support/esp_clk.c
+++ b/components/esp_hw_support/esp_clk.c
@ -36,6 +36,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/rtc.h"
 #include "esp32c6/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C61    //TODO: IDF-9526, refactor this
+#include "esp32c61/rom/rtc.h"
+#include "esp32c61/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/rtc.h"
 #include "esp32h2/rtc.h"
@ -93,7 +96,7 @@ int IRAM_ATTR esp_clk_cpu_freq(void)
 int IRAM_ATTR esp_clk_apb_freq(void)
 {
    // TODO: IDF-5173 Require cleanup, implementation should be unified
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C61
    return rtc_clk_apb_freq_get();
 #else
    return MIN(s_get_cpu_freq_mhz() * MHZ, APB_CLK_FREQ);
--- a/components/esp_hw_support/include/soc/esp32c61/.gitkeep
+++ b/components/esp_hw_support/include/soc/esp32c61/.gitkeep
--- a/components/esp_hw_support/include/soc/esp32c61/rtc.h
+++ b/components/esp_hw_support/include/soc/esp32c61/rtc.h
@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file esp32c61/rtc.h
+ *
+ * This file contains declarations of rtc related functions.
+ */
+
+/**
+ * @brief Get current value of RTC counter in microseconds
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter in microseconds
+ */
+uint64_t esp_rtc_get_time_us(void);
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/esp_hw_support/periph_ctrl.c
+++ b/components/esp_hw_support/periph_ctrl.c
@ -11,7 +11,8 @@
 #include "hal/clk_gate_ll.h"
 #endif

-#if SOC_MODEM_CLOCK_IS_INDEPENDENT
+// TODO: [ESP32C61] IDF-9513, modem support
+#if SOC_MODEM_CLOCK_IS_INDEPENDENT && SOC_MODEM_CLOCK_SUPPORTED
 #include "esp_private/esp_modem_clock.h"
 #endif

--- a/components/esp_hw_support/port/esp32c61/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32c61/CMakeLists.txt
@ -1 +1,36 @@
-target_include_directories(${COMPONENT_LIB} PUBLIC . include)
+set(srcs "rtc_clk_init.c"
+         "rtc_clk.c"
+         "pmu_param.c"
+         "pmu_init.c"
+         "pmu_sleep.c"
+         "rtc_time.c"
+         "chip_info.c"
+         "ocode_init.c"
+         )
+
+if(NOT BOOTLOADER_BUILD)
+    list(APPEND srcs "sar_periph_ctrl.c"
+                     "esp_crypto_lock.c")
+
+    if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
+        list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
+    endif()
+
+endif()
+
+# TODO: [ESP32C61] IDF-9250, [ESP32C61] IDF-9276
+if(CONFIG_IDF_TARGET_ESP32C61)
+    list(REMOVE_ITEM srcs
+        "pmu_param.c"
+        "pmu_init.c"
+        "pmu_sleep.c"
+        "sar_periph_ctrl.c"
+        "esp_crypto_lock.c"
+        "ocode_init.c"
+    )
+endif()
+
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+
+target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
+target_include_directories(${COMPONENT_LIB} PUBLIC . include private_include)
--- a/components/esp_hw_support/port/esp32c61/Kconfig.hw_support
+++ b/components/esp_hw_support/port/esp32c61/Kconfig.hw_support
@ -0,0 +1,41 @@
+choice ESP32C61_REV_MIN
+    prompt "Minimum Supported ESP32-C61 Revision"
+    default ESP32C61_REV_MIN_0
+    help
+        Required minimum chip revision. ESP-IDF will check for it and
+        reject to boot if the chip revision fails the check.
+        This ensures the chip used will have some modifications (features, or bugfixes).
+
+        The complied binary will only support chips above this revision,
+        this will also help to reduce binary size.
+
+    config ESP32C61_REV_MIN_0
+        bool "Rev v0.0"
+endchoice
+
+config ESP32C61_REV_MIN_FULL
+    int
+    default 0 if ESP32C61_REV_MIN_0
+
+config ESP_REV_MIN_FULL
+    int
+    default ESP32C61_REV_MIN_FULL
+
+    #
+    # MAX Revision
+    #
+
+    comment "Maximum Supported ESP32-C61 Revision (Rev v0.99)"
+    # Maximum revision that IDF supports.
+    # It can not be changed by user.
+    # Only Espressif can change it when a new version will be supported in IDF.
+    # Supports all chips starting from ESP32C61_REV_MIN_FULL to ESP32C61_REV_MAX_FULL
+
+config ESP32C61_REV_MAX_FULL
+    int
+    default 99
+    # keep in sync the "Maximum Supported Revision" description with this value
+
+config ESP_REV_MAX_FULL
+    int
+    default ESP32C61_REV_MAX_FULL
--- a/components/esp_hw_support/port/esp32c61/Kconfig.rtc
+++ b/components/esp_hw_support/port/esp32c61/Kconfig.rtc
@ -0,0 +1,39 @@
+choice RTC_CLK_SRC
+    prompt "RTC clock source"
+    default RTC_CLK_SRC_INT_RC
+    help
+        Choose which clock is used as RTC clock source.
+
+    config RTC_CLK_SRC_INT_RC
+        bool "Internal 150 kHz RC oscillator"
+    config RTC_CLK_SRC_EXT_CRYS
+        bool "External 32kHz crystal"
+        select ESP_SYSTEM_RTC_EXT_XTAL
+    config RTC_CLK_SRC_EXT_OSC
+        bool "External 32kHz oscillator at 32K_XP pin"
+        select ESP_SYSTEM_RTC_EXT_OSC
+    config RTC_CLK_SRC_INT_RC32K
+        bool "Internal 32kHz RC oscillator"
+endchoice
+
+config RTC_CLK_CAL_CYCLES
+    int "Number of cycles for RTC_SLOW_CLK calibration"
+    default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K
+    default 1024 if RTC_CLK_SRC_INT_RC
+    range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K
+    range 0 32766 if RTC_CLK_SRC_INT_RC
+    help
+        When the startup code initializes RTC_SLOW_CLK, it can perform
+        calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
+        frequency. This option sets the number of RTC_SLOW_CLK cycles measured
+        by the calibration routine. Higher numbers increase calibration
+        precision, which may be important for applications which spend a lot of
+        time in deep sleep. Lower numbers reduce startup time.
+
+        When this option is set to 0, clock calibration will not be performed at
+        startup, and approximate clock frequencies will be assumed:
+
+        - 136000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
+        - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
+            In case more value will help improve the definition of the launch of the crystal.
+            If the crystal could not start, it will be switched to internal RC.
--- a/components/esp_hw_support/port/esp32c61/chip_info.c
+++ b/components/esp_hw_support/port/esp32c61/chip_info.c
@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include "esp_chip_info.h"
+#include "hal/efuse_hal.h"
+
+void esp_chip_info(esp_chip_info_t *out_info)
+{
+    assert(out_info);
+    memset(out_info, 0, sizeof(*out_info));
+    out_info->model = CHIP_ESP32C61;
+    out_info->revision = efuse_hal_chip_revision();
+    out_info->cores = 1;
+    out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
+}
--- a/components/esp_hw_support/port/esp32c61/cpu_region_protect.c
+++ b/components/esp_hw_support/port/esp32c61/cpu_region_protect.c
@ -0,0 +1,174 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "esp_cpu.h"
+#include "esp_fault.h"
+
+#ifdef BOOTLOADER_BUILD
+// Without L bit set
+#define CONDITIONAL_NONE        0x0
+#define CONDITIONAL_RX          PMP_R | PMP_X
+#define CONDITIONAL_RW          PMP_R | PMP_W
+#define CONDITIONAL_RWX         PMP_R | PMP_W | PMP_X
+#else
+// With L bit set
+#define CONDITIONAL_NONE        NONE
+#define CONDITIONAL_RX          RX
+#define CONDITIONAL_RW          RW
+#define CONDITIONAL_RWX         RWX
+#endif
+
+static void esp_cpu_configure_invalid_regions(void)
+{
+    //TODO: [ESP32C61] IDF-9580
+    abort();
+}
+
+void esp_cpu_configure_region_protection(void)
+{
+    // ROM has configured the MSPI region with RX permission, we should add W attribute for psram
+    PMA_ENTRY_SET_NAPOT(0, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X);
+    return;
+    /* Notes on implementation:
+     *
+     * 1) Note: ESP32-C61 CPU doesn't support overlapping PMP regions
+     *
+     * 2) ESP32-C61 supports 16 PMA regions so we use this feature to block all the invalid address ranges
+     *
+     * 3) We use combination of NAPOT (Naturally Aligned Power Of Two) and TOR (top of range)
+     * entries to map all the valid address space, bottom to top. This leaves us with some extra PMP entries
+     * which can be used to provide more granular access
+     *
+     * 4) Entries are grouped in order with some static asserts to try and verify everything is
+     * correct.
+     */
+
+    /* There are 4 configuration scenarios for SRAM
+     *
+     * 1. Bootloader build:
+     *    - We cannot set the lock bit as we need to reconfigure it again for the application.
+     *      We configure PMP to cover entire valid IRAM and DRAM range.
+     *
+     * 2. Application build with CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT enabled
+     *    - We split the SRAM into IRAM and DRAM such that IRAM region cannot be written to
+     *      and DRAM region cannot be executed. We use _iram_end and _data_start markers to set the boundaries.
+     *      We also lock these entries so the R/W/X permissions are enforced even for machine mode
+     *
+     * 3. Application build with CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT disabled
+     *    - The IRAM-DRAM split is not enabled so we just need to ensure that access to only valid address ranges are successful
+     *      so for that we set PMP to cover entire valid IRAM and DRAM region.
+     *      We also lock these entries so the R/W/X permissions are enforced even for machine mode
+     *
+     * 4. CPU is in OCD debug mode
+     *    - The IRAM-DRAM split is not enabled so that OpenOCD can write and execute from IRAM.
+     *      We set PMP to cover entire valid IRAM and DRAM region.
+     *      We also lock these entries so the R/W/X permissions are enforced even for machine mode
+     */
+    const unsigned NONE    = PMP_L;
+    const unsigned R       = PMP_L | PMP_R;
+    const unsigned RW      = PMP_L | PMP_R | PMP_W;
+    const unsigned RX      = PMP_L | PMP_R | PMP_X;
+    const unsigned RWX     = PMP_L | PMP_R | PMP_W | PMP_X;
+
+    //
+    // Configure all the invalid address regions using PMA
+    //
+    esp_cpu_configure_invalid_regions();
+    //
+    // Configure all the valid address regions using PMP
+    //
+
+    // 1. CPU Subsystem region - contains debug mode code and interrupt config registers
+    const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_CPU_SUBSYSTEM_LOW, SOC_CPU_SUBSYSTEM_HIGH);
+    PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX);
+    _Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
+
+    // 2.1 I-ROM
+    PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);
+    PMP_ENTRY_SET(2, SOC_IROM_MASK_HIGH, PMP_TOR | RX);
+    _Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I-ROM region");
+
+    // 2.2 D-ROM
+    PMP_ENTRY_SET(3, SOC_DROM_MASK_LOW, NONE);
+    PMP_ENTRY_SET(4, SOC_DROM_MASK_HIGH, PMP_TOR | R);
+    _Static_assert(SOC_DROM_MASK_LOW < SOC_DROM_MASK_HIGH, "Invalid D-ROM region");
+
+    if (esp_cpu_dbgr_is_attached()) {
+        // Anti-FI check that cpu is really in ocd mode
+        ESP_FAULT_ASSERT(esp_cpu_dbgr_is_attached());
+
+        // 5. IRAM and DRAM
+        // const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
+        const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, 0x40880000);
+        PMP_ENTRY_SET(5, pmpaddr5, PMP_NAPOT | RWX);
+        _Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
+    } else {
+#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
+        extern int _iram_end;
+        // 5. IRAM and DRAM
+        /* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
+         * Bootloader might have given extra permissions and those won't be cleared
+         */
+        PMP_ENTRY_CFG_RESET(5);
+        PMP_ENTRY_CFG_RESET(6);
+        PMP_ENTRY_CFG_RESET(7);
+        PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
+        PMP_ENTRY_SET(6, (int)&_iram_end, PMP_TOR | RX);
+        PMP_ENTRY_SET(7, SOC_DRAM_HIGH, PMP_TOR | RW);
+#else
+        // 5. IRAM and DRAM
+        // const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
+        const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, 0x40880000);
+        PMP_ENTRY_SET(5, pmpaddr5, PMP_NAPOT | CONDITIONAL_RWX);
+        _Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
+#endif
+    }
+
+    // 4. I_Cache (flash)
+    const uint32_t pmpaddr8 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
+    PMP_ENTRY_SET(8, pmpaddr8, PMP_NAPOT | RX);
+    _Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I_Cache region");
+
+    // 5. D_Cache (flash)
+    const uint32_t pmpaddr9 = PMPADDR_NAPOT(SOC_DROM_LOW, SOC_DROM_HIGH);
+    PMP_ENTRY_SET(9, pmpaddr9, PMP_NAPOT | R);
+    _Static_assert(SOC_DROM_LOW < SOC_DROM_HIGH, "Invalid D_Cache region");
+
+    // 6. LP memory
+#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
+    extern int _rtc_text_end;
+    /* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
+     * Bootloader might have given extra permissions and those won't be cleared
+     */
+    PMP_ENTRY_CFG_RESET(10);
+    PMP_ENTRY_CFG_RESET(11);
+    PMP_ENTRY_CFG_RESET(12);
+    PMP_ENTRY_CFG_RESET(13);
+    PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW, NONE);
+#if CONFIG_ULP_COPROC_RESERVE_MEM
+    // First part of LP mem is reserved for coprocessor
+    PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW + CONFIG_ULP_COPROC_RESERVE_MEM, PMP_TOR | RW);
+#else // CONFIG_ULP_COPROC_RESERVE_MEM
+    // Repeat same previous entry, to ensure next entry has correct base address (TOR)
+    PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
+#endif // !CONFIG_ULP_COPROC_RESERVE_MEM
+    PMP_ENTRY_SET(12, (int)&_rtc_text_end, PMP_TOR | RX);
+    PMP_ENTRY_SET(13, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
+#else
+    const uint32_t pmpaddr10 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
+    PMP_ENTRY_SET(10, pmpaddr10, PMP_NAPOT | CONDITIONAL_RWX);
+    _Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
+#endif
+
+
+    // 7. Peripheral addresses
+    const uint32_t pmpaddr14 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
+    PMP_ENTRY_SET(14, pmpaddr14, PMP_NAPOT | RW);
+    _Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
+}
--- a/components/esp_hw_support/port/esp32c61/esp_clk_tree.c
+++ b/components/esp_hw_support/port/esp32c61/esp_clk_tree.c
@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "esp_clk_tree.h"
+#include "esp_err.h"
+#include "esp_check.h"
+#include "soc/rtc.h"
+#include "hal/clk_tree_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "esp_private/esp_clk_tree_common.h"
+
+static const char *TAG = "esp_clk_tree";
+
+//TODO: [ESP32C61] IDF-9249
+
+esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision,
+uint32_t *freq_value)
+{
+    ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src");
+    ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
+    ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer");
+
+    uint32_t clk_src_freq = 0;
+    switch (clk_src) {
+    case SOC_MOD_CLK_PLL_F80M:
+        clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ;
+        break;
+    case SOC_MOD_CLK_PLL_F160M:
+        clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ;
+        break;
+    case SOC_MOD_CLK_PLL_F240M:
+        clk_src_freq = CLK_LL_PLL_240M_FREQ_MHZ * MHZ;
+        break;
+    default:
+        break;
+    }
+
+    ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG,
+                        "freq shouldn't be 0, calibration failed");
+    *freq_value = clk_src_freq;
+    return ESP_OK;
+}
--- a/components/esp_hw_support/port/esp32c61/esp_cpu_intr.c
+++ b/components/esp_hw_support/port/esp32c61/esp_cpu_intr.c
@ -0,0 +1,23 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_cpu.h"
+#include "esp_riscv_intr.h"
+
+//TODO: [ESP32C61] IDF-9262, inherit from C5
+void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
+{
+    /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
+     * interrupts, all the other lines starting from 16 and above can be used by external peripheral.
+     *
+     * Reserve interrupt line 1 for the Wifi controller.
+     * Reserve interrupt line 6 since it is used for disabling interrupts in the interrupt allocator (INT_MUX_DISABLED_INTNO)
+     */
+    const uint32_t rsvd_mask = BIT(1) | BIT(6);
+    intr_desc_ret->priority = 1;
+    intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
+    intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);
+}
--- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
@ -0,0 +1,499 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/clk_tree_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************************************************************************/
+/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
+/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
+/************************************************************************************/
+
+/**
+ * @file rtc.h
+ * @brief Low-level RTC power, clock functions.
+ *
+ * Functions in this file facilitate configuration of ESP32C61's RTC_CNTL peripheral.
+ * RTC_CNTL peripheral handles many functions:
+ * - enables/disables clocks and power to various parts of the chip; this is
+ *   done using direct register access (forcing power up or power down) or by
+ *   allowing state machines to control power and clocks automatically
+ * - handles sleep and wakeup functions
+ * - maintains a 48-bit counter which can be used for timekeeping
+ *
+ * These functions are not thread safe, and should not be viewed as high level
+ * APIs. For example, while this file provides a function which can switch
+ * CPU frequency, this function is on its own is not sufficient to implement
+ * frequency switching in ESP-IDF context: some coordination with RTOS,
+ * peripheral drivers, and WiFi/BT stacks is also required.
+ *
+ * These functions will normally not be used in applications directly.
+ * ESP-IDF provides, or will provide, drivers and other facilities to use
+ * RTC subsystem functionality.
+ *
+ * The functions are loosely split into the following groups:
+ * - rtc_clk: clock switching, calibration
+ * - rtc_time: reading RTC counter, conversion between counter values and time
+ */
+
+#define MHZ (1000000)
+
+#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles)  (cycles << 10)
+#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles)   (cycles << 12)
+#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles)   (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
+
+#define OTHER_BLOCKS_POWERUP        1
+#define OTHER_BLOCKS_WAIT           1
+
+/* Delays for various clock sources to be enabled/switched.
+ * All values are in microseconds.
+ */
+#define SOC_DELAY_RTC_FAST_CLK_SWITCH       3
+#define SOC_DELAY_RTC_SLOW_CLK_SWITCH       300
+#define SOC_DELAY_RC_FAST_ENABLE            50
+#define SOC_DELAY_RC_FAST_DIGI_SWITCH       5
+#define SOC_DELAY_RC32K_ENABLE              300
+
+#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
+#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  100
+
+#define RTC_CNTL_CK8M_DFREQ_DEFAULT  100
+#define RTC_CNTL_SCK_DCAP_DEFAULT    128
+#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
+
+/* Various delays to be programmed into power control state machines */
+#define RTC_CNTL_XTL_BUF_WAIT_SLP_US            (250)
+#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES        (1)
+#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES           (4)
+#define RTC_CNTL_WAKEUP_DELAY_CYCLES            (5)
+#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES    (1)
+#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES       (1)
+#define RTC_CNTL_MIN_SLP_VAL_MIN                (2)
+
+/*
+set sleep_init default param
+*/
+#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT  5
+#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP  0
+#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT  15
+#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_SLEEP_ON  0
+#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT  1
+#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT  0
+#define RTC_CNTL_PD_CUR_SLEEP_ON  0
+#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT  1
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
+
+/*
+The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
+storing in efuse (based on ATE 5k ECO3 chips)
+*/
+#define K_RTC_MID_MUL10000 215
+#define K_DIG_MID_MUL10000 213
+#define V_RTC_MID_MUL10000  10800
+#define V_DIG_MID_MUL10000  10860
+
+/**
+ * @brief CPU clock configuration structure
+ */
+typedef struct rtc_cpu_freq_config_s {
+    soc_cpu_clk_src_t source;       //!< The clock from which CPU clock is derived
+    uint32_t source_freq_mhz;       //!< Source clock frequency
+    uint32_t div;                   //!< Divider, freq_mhz = SOC_ROOT_CLK freq_mhz / div
+    uint32_t freq_mhz;              //!< CPU clock frequency
+} rtc_cpu_freq_config_t;
+
+#define RTC_CLK_CAL_FRACT  19  //!< Number of fractional bits in values returned by rtc_clk_cal
+
+#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
+#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
+
+
+/**
+ * @brief Clock source to be calibrated using rtc_clk_cal function
+ *
+ * @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL
+ *       However, this is not true on ESP32C61. The conversion to register field values is explicitly done in
+ *       rtc_clk_cal_internal
+ */
+typedef enum {
+    RTC_CAL_RTC_MUX = -1,                                  //!< Currently selected RTC_SLOW_CLK
+    RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW,        //!< Internal 150kHz RC oscillator
+    RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K,            //!< Internal 32kHz RC oscillator, as one type of 32k clock
+    RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K,       //!< External 32kHz XTAL, as one type of 32k clock
+    RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW,  //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
+    RTC_CAL_RC_FAST                                        //!< Internal 20MHz RC oscillator
+} rtc_cal_sel_t;
+
+/**
+ * Initialization parameters for rtc_clk_init
+ */
+typedef struct {
+    soc_xtal_freq_t xtal_freq : 8;             //!< Main XTAL frequency
+    uint32_t cpu_freq_mhz : 10;                //!< CPU frequency to set, in MHz
+    soc_rtc_fast_clk_src_t fast_clk_src : 2;   //!< RTC_FAST_CLK clock source to choose
+    soc_rtc_slow_clk_src_t slow_clk_src : 3;   //!< RTC_SLOW_CLK clock source to choose
+    uint32_t clk_rtc_clk_div : 8;
+    uint32_t clk_8m_clk_div : 3;               //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency)
+    uint32_t slow_clk_dcap : 8;                //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency)
+    uint32_t clk_8m_dfreq : 10;                 //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency)
+    uint32_t rc32k_dfreq : 10;                 //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency)
+} rtc_clk_config_t;
+
+/**
+ * Default initializer for rtc_clk_config_t
+ */
+#define RTC_CLK_CONFIG_DEFAULT() { \
+    .xtal_freq = CONFIG_XTAL_FREQ, \
+    .cpu_freq_mhz = 80, \
+    .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
+    .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
+    .clk_rtc_clk_div = 0, \
+    .clk_8m_clk_div = 0, \
+    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
+    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
+    .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
+}
+
+/**
+ * Initialize clocks and set CPU frequency
+ *
+ * @param cfg clock configuration as rtc_clk_config_t
+ */
+void rtc_clk_init(rtc_clk_config_t cfg);
+
+/**
+ * @brief Get main XTAL frequency
+ *
+ * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
+ * rtc_clk_init function
+ *
+ * @return XTAL frequency, one of soc_xtal_freq_t
+ */
+soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
+
+/**
+ * @brief Update XTAL frequency
+ *
+ * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
+ * after startup.
+ *
+ * @param xtal_freq New frequency value
+ */
+void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
+
+/**
+ * @brief Enable or disable 32 kHz XTAL oscillator
+ * @param en  true to enable, false to disable
+ */
+void rtc_clk_32k_enable(bool en);
+
+/**
+ * @brief Configure 32 kHz XTAL oscillator to accept external clock signal
+ */
+void rtc_clk_32k_enable_external(void);
+
+/**
+ * @brief Get the state of 32k XTAL oscillator
+ * @return true if 32k XTAL oscillator has been enabled
+ */
+bool rtc_clk_32k_enabled(void);
+
+/**
+ * @brief Enable 32k oscillator, configuring it for fast startup time.
+ * Note: to achieve higher frequency stability, rtc_clk_32k_enable function
+ * must be called one the 32k XTAL oscillator has started up. This function
+ * will initially disable the 32k XTAL oscillator, so it should not be called
+ * when the system is using 32k XTAL as RTC_SLOW_CLK.
+ *
+ * @param cycle Number of 32kHz cycles to bootstrap external crystal.
+ *              If 0, no square wave will be used to bootstrap crystal oscillation.
+ */
+void rtc_clk_32k_bootstrap(uint32_t cycle);
+
+/**
+ * @brief Enable or disable 32 kHz internal rc oscillator
+ * @param en  true to enable, false to disable
+ */
+void rtc_clk_rc32k_enable(bool enable);
+
+/**
+ * @brief Enable or disable 8 MHz internal oscillator
+ *
+ * @param clk_8m_en true to enable 8MHz generator
+ */
+void rtc_clk_8m_enable(bool clk_8m_en);
+
+/**
+ * @brief Get the state of 8 MHz internal oscillator
+ * @return true if the oscillator is enabled
+ */
+bool rtc_clk_8m_enabled(void);
+
+/**
+ * @brief Select source for RTC_SLOW_CLK
+ * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values)
+ */
+void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src);
+
+/**
+ * @brief Get the RTC_SLOW_CLK source
+ * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values)
+ */
+soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void);
+
+/**
+ * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
+ *
+ * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000
+ * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768
+ * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768
+ * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768
+ *
+ * rtc_clk_cal function can be used to get more precise value by comparing
+ * RTC_SLOW_CLK frequency to the frequency of main XTAL.
+ *
+ * @return RTC_SLOW_CLK frequency, in Hz
+ */
+uint32_t rtc_clk_slow_freq_get_hz(void);
+
+/**
+ * @brief Select source for RTC_FAST_CLK
+ * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values)
+ */
+void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src);
+
+/**
+ * @brief Get the RTC_FAST_CLK source
+ * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values)
+ */
+soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void);
+
+/**
+ * @brief Get CPU frequency config for a given frequency
+ * @param freq_mhz  Frequency in MHz
+ * @param[out] out_config Output, CPU frequency configuration structure
+ * @return true if frequency can be obtained, false otherwise
+ */
+bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU frequency
+ *
+ * This function sets CPU frequency according to the given configuration
+ * structure. It enables PLLs, if necessary.
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Switch CPU frequency (optimized for speed)
+ *
+ * This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
+ * It works faster because it does not disable PLLs when switching from PLL to
+ * XTAL and does not enabled them when switching back. If PLL is not already
+ * enabled when this function is called to switch from XTAL to PLL frequency,
+ * or the PLL which is enabled is the wrong one, this function will fall back
+ * to calling rtc_clk_cpu_freq_set_config.
+ *
+ * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
+ * so it is less safe to use it e.g. from a panic handler (when memory might
+ * be corrupted).
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Get the currently used CPU frequency configuration
+ * @param[out] out_config  Output, CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU clock source to XTAL
+ *
+ * Short form for filling in rtc_cpu_freq_config_t structure and calling
+ * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
+ * Assumes that XTAL frequency has been determined — don't call in startup code.
+ *
+ * @note On ESP32C61, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
+ * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
+ */
+void rtc_clk_cpu_freq_set_xtal(void);
+
+/**
+ * @brief Switch root clock source to PLL (only used by sleep) release root clock source locked by PMU
+ *
+ * wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL
+ * clock, PMU will forcibly lock the root clock source as PLL, when the root
+ * clock source of the software system is selected as PLL, we need to release
+ * the root clock source locking and switch the root clock source to PLL in the
+ * sleep process (a critical section).
+ *
+ * @param[in] Maximum CPU frequency, in MHz
+ */
+void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz);
+
+/**
+ * @brief Get the current APB frequency.
+ * @return The calculated APB frequency value, in Hz.
+ */
+uint32_t rtc_clk_apb_freq_get(void);
+
+/**
+ * @brief Measure RTC slow clock's period, based on main XTAL frequency
+ *
+ * This function will time out and return 0 if the time for the given number
+ * of cycles to be counted exceeds the expected time twice. This may happen if
+ * 32k XTAL is being calibrated, but the oscillator has not started up (due to
+ * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
+ *
+ * @note When 32k CLK is being calibrated, this function will check the accuracy
+ * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if
+ * the check fails, then consider this an invalid 32k clock and return 0. This
+ * check can filter some jamming signal.
+ *
+ * @param cal_clk  clock to be measured
+ * @param slow_clk_cycles  number of slow clock cycles to average
+ * @return average slow clock period in microseconds, Q13.19 fixed point format,
+ *         or 0 if calibration has timed out
+ */
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
+ * @param time_in_us Time interval in microseconds
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return number of slow clock cycles
+ */
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
+
+/**
+ * @brief Convert time interval from RTC_SLOW_CLK to microseconds
+ * @param time_in_us Time interval in RTC_SLOW_CLK cycles
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return time interval in microseconds
+ */
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
+
+/**
+ * @brief Get current value of RTC counter
+ *
+ * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
+ * cycles. Counter value is not writable by software. The value is not adjusted
+ * when switching to a different RTC_SLOW_CLK source.
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter
+ */
+uint64_t rtc_time_get(void);
+
+/**
+ * @brief Busy loop until next RTC_SLOW_CLK cycle
+ *
+ * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
+ * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
+ * one RTC_SLOW_CLK cycle later.
+ */
+void rtc_clk_wait_for_slow_cycle(void);
+
+/**
+ * @brief Enable the rtc digital 8M clock
+ *
+ * This function is used to enable the digital rtc 8M clock to support peripherals.
+ * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above.
+ */
+void rtc_dig_clk8m_enable(void);
+
+/**
+ * @brief Disable the rtc digital 8M clock
+ *
+ * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals.
+ */
+void rtc_dig_clk8m_disable(void);
+
+/**
+ * @brief Get whether the rtc digital 8M clock is enabled
+ */
+bool rtc_dig_8m_enabled(void);
+
+/**
+ * @brief Calculate the real clock value after the clock calibration
+ *
+ * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal`
+ * @return Frequency of the clock in Hz
+ */
+uint32_t rtc_clk_freq_cal(uint32_t cal_val);
+
+
+// -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
+// **WARNING**: The following are only for backwards compatibility.
+// Please use the declarations in soc/clk_tree_defs.h instead.
+/**
+ * @brief CPU clock source
+ */
+typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
+#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL  //!< XTAL
+#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL    //!< PLL (480M)
+#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator
+
+/**
+ * @brief RTC SLOW_CLK frequency values
+ */
+typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
+#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW         //!< Internal 150 kHz RC oscillator
+#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K    //!< External 32 kHz XTAL
+
+/**
+ * @brief RTC FAST_CLK frequency values
+ */
+typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
+
+/**
+ * @brief Possible main XTAL frequency values.
+ */
+typedef soc_xtal_freq_t rtc_xtal_freq_t;
+#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M                 //!< 40 MHz XTAL
+
+/* Alias of frequency related macros */
+#define RTC_FAST_CLK_FREQ_APPROX    SOC_CLK_RC_FAST_FREQ_APPROX
+#define RTC_FAST_CLK_FREQ_8M        SOC_CLK_RC_FAST_FREQ_APPROX
+#define RTC_SLOW_CLK_FREQ_150K      SOC_CLK_RC_SLOW_FREQ_APPROX
+#define RTC_SLOW_CLK_FREQ_32K       SOC_CLK_XTAL32K_FREQ_APPROX
+
+/* Alias of deprecated function names */
+#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq)
+#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get()
+#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq)
+#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get()
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/esp_hw_support/port/esp32c61/io_mux.c
+++ b/components/esp_hw_support/port/esp32c61/io_mux.c
@ -0,0 +1,35 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "freertos/FreeRTOS.h"
+#include "esp_private/io_mux.h"
+#include "hal/gpio_ll.h"
+
+//TODO: [ESP32C61] IDf-9316
+
+static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED;
+static soc_module_clk_t s_io_mux_clk_src = 0; // by default, the clock source is not set explicitly by any consumer (e.g. SDM, Filter)
+
+esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
+{
+    bool clk_conflict = false;
+    // check is the IO MUX has been set to another clock source
+    portENTER_CRITICAL(&s_io_mux_spinlock);
+    if (s_io_mux_clk_src != 0 && s_io_mux_clk_src != clk_src) {
+        clk_conflict = true;
+    } else {
+        s_io_mux_clk_src = clk_src;
+    }
+    portEXIT_CRITICAL(&s_io_mux_spinlock);
+
+    if (clk_conflict) {
+        return ESP_ERR_INVALID_STATE;
+    }
+
+    gpio_ll_iomux_set_clk_src(clk_src);
+
+    return ESP_OK;
+}
--- a/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
@ -0,0 +1,484 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <esp_types.h>
+#include "soc/pmu_struct.h"
+#include "hal/pmu_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32C61] IDF-9250
+
+#define HP_CALI_DBIAS_DEFAULT   25
+#define LP_CALI_DBIAS_DEFAULT   26
+
+// FOR  XTAL FORCE PU IN SLEEP
+#define PMU_PD_CUR_SLEEP_ON    0
+#define PMU_BIASSLP_SLEEP_ON   0
+
+// FOR BOTH LIGHTSLEEP & DEEPSLEEP
+#define PMU_PD_CUR_SLEEP_DEFAULT        1
+#define PMU_BIASSLP_SLEEP_DEFAULT       1
+#define PMU_LP_XPD_SLEEP_DEFAULT        1
+#define PMU_LP_SLP_XPD_SLEEP_DEFAULT    0
+#define PMU_LP_SLP_DBIAS_SLEEP_DEFAULT  0
+
+// FOR LIGHTSLEEP
+#define PMU_HP_DRVB_LIGHTSLEEP      0
+#define PMU_LP_DRVB_LIGHTSLEEP      0
+#define PMU_HP_XPD_LIGHTSLEEP       1
+
+#define PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT    0
+#define PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT 1
+#define PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT 12
+
+// FOR LIGHTSLEEP: XTAL FORCE PU
+#define PMU_DBG_ATTEN_ACTIVE_DEFAULT    0
+
+// FOR DEEPSLEEP
+#define PMU_DBG_HP_DEEPSLEEP    0
+#define PMU_HP_XPD_DEEPSLEEP    0
+#define PMU_LP_DRVB_DEEPSLEEP   0
+
+#define PMU_REGDMA_S2A_WORK_TIME_US     480
+
+#define PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT     12
+#define PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT  23
+
+#define EFUSE_BURN_OFFSET_DSLP_DBG     8
+#define EFUSE_BURN_OFFSET_DSLP_LP_DBIAS   23
+
+uint32_t get_act_hp_dbias(void);
+uint32_t get_act_lp_dbias(void);
+
+typedef struct {
+    pmu_hp_dig_power_reg_t  dig_power;
+    pmu_hp_clk_power_reg_t  clk_power;
+    pmu_hp_xtal_reg_t       xtal;
+} pmu_hp_system_power_param_t;
+
+const pmu_hp_system_power_param_t* pmu_hp_system_power_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    uint32_t                icg_func;
+    uint32_t                icg_apb;
+    pmu_hp_icg_modem_reg_t  icg_modem;
+    pmu_hp_sysclk_reg_t     sysclk;
+} pmu_hp_system_clock_param_t;
+
+const pmu_hp_system_clock_param_t* pmu_hp_system_clock_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_hp_sys_cntl_reg_t   syscntl;
+} pmu_hp_system_digital_param_t;
+
+const pmu_hp_system_digital_param_t* pmu_hp_system_digital_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_hp_bias_reg_t       bias;
+    pmu_hp_regulator0_reg_t regulator0;
+    pmu_hp_regulator1_reg_t regulator1;
+} pmu_hp_system_analog_param_t;
+
+const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_hp_backup_reg_t     retention;
+    uint32_t                backup_clk;
+} pmu_hp_system_retention_param_t;
+
+const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_lp_dig_power_reg_t  dig_power;
+    pmu_lp_clk_power_reg_t  clk_power;
+    pmu_lp_xtal_reg_t       xtal;
+} pmu_lp_system_power_param_t;
+
+const pmu_lp_system_power_param_t* pmu_lp_system_power_param_default(pmu_lp_mode_t mode);
+
+
+
+typedef struct {
+    pmu_lp_bias_reg_t       bias;
+    pmu_lp_regulator0_reg_t regulator0;
+    pmu_lp_regulator1_reg_t regulator1;
+} pmu_lp_system_analog_param_t;
+
+const pmu_lp_system_analog_param_t* pmu_lp_system_analog_param_default(pmu_lp_mode_t mode);
+
+
+
+/* Following software configuration instance type from pmu_struct.h used for the PMU state machine in sleep flow*/
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t vdd_spi_pd_en: 1;
+        uint32_t mem_dslp     : 1;
+        uint32_t mem_pd_en    : 4;
+        uint32_t wifi_pd_en   : 1;
+        uint32_t reserved1    : 1;
+        uint32_t cpu_pd_en    : 1;
+        uint32_t aon_pd_en    : 1;
+        uint32_t top_pd_en    : 1;
+    };
+    struct {
+        uint32_t reserved2    : 26;
+        uint32_t i2c_iso_en   : 1;
+        uint32_t i2c_retention: 1;
+        uint32_t xpd_bb_i2c   : 1;
+        uint32_t xpd_bbpll_i2c: 1;
+        uint32_t xpd_bbpll    : 1;
+        uint32_t reserved3    : 1;
+    };
+    struct {
+        uint32_t reserved4    : 31;
+        uint32_t xpd_xtal     : 1;
+    };
+    uint32_t val;
+} pmu_hp_power_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 30;
+        uint32_t mem_dslp  : 1;
+        uint32_t peri_pd_en: 1;
+    };
+    struct {
+        uint32_t reserved1  : 28;
+        uint32_t xpd_xtal32k: 1;
+        uint32_t xpd_rc32k  : 1;
+        uint32_t xpd_fosc   : 1;
+        uint32_t pd_osc     : 1;
+    };
+    struct {
+        uint32_t reserved2  : 31;
+        uint32_t xpd_xtal   : 1;
+    };
+    uint32_t val;
+} pmu_lp_power_t;
+
+typedef struct {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    struct {
+        uint32_t reserved1      : 16;
+        uint32_t slp_mem_xpd    : 1;
+        uint32_t slp_logic_xpd  : 1;
+        uint32_t xpd            : 1;
+        uint32_t slp_mem_dbias  : 4;
+        uint32_t slp_logic_dbias: 4;
+        uint32_t dbias          : 5;
+    };
+    struct {
+        uint32_t reserved2: 8;
+        uint32_t drv_b    : 24;
+    };
+} pmu_hp_analog_t;
+
+typedef struct {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    struct {
+        uint32_t reserved1: 21;
+        uint32_t slp_xpd  : 1;
+        uint32_t xpd	  : 1;
+        uint32_t slp_dbias: 4;
+        uint32_t dbias    : 5;
+    };
+    struct {
+        uint32_t reserved2: 28;
+        uint32_t drv_b    : 4;
+    };
+} pmu_lp_analog_t;
+
+typedef struct {
+    uint32_t    modem_wakeup_wait_cycle;
+    uint16_t    analog_wait_target_cycle;
+    uint16_t    digital_power_down_wait_cycle;
+    uint16_t    digital_power_supply_wait_cycle;
+    uint16_t    digital_power_up_wait_cycle;
+    uint16_t    pll_stable_wait_cycle;
+    uint8_t     modify_icg_cntl_wait_cycle;
+    uint8_t     switch_icg_cntl_wait_cycle;
+    uint8_t     min_slp_slow_clk_cycle;
+} pmu_hp_param_t;
+
+typedef struct {
+    uint16_t    digital_power_supply_wait_cycle;
+    uint8_t     min_slp_slow_clk_cycle;
+    uint8_t     analog_wait_target_cycle;
+    uint8_t     digital_power_down_wait_cycle;
+    uint8_t     digital_power_up_wait_cycle;
+} pmu_lp_param_t;
+
+typedef struct {
+    union {
+        uint16_t    xtal_stable_wait_slow_clk_cycle;
+        uint16_t    xtal_stable_wait_cycle;
+    };
+} pmu_hp_lp_param_t;
+
+#define PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES        (10)
+#define PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES        (10)
+
+#define PMU_HP_WAKEUP_DELAY_CYCLES              (0)
+#define PMU_HP_XTAL_STABLE_WAIT_CYCLES          (3155)  /* Not used, Fast OSC as PMU work clock source is about 201 us, corresponding to PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES */
+#define PMU_HP_PLL_STABLE_WAIT_CYCLES           (2)
+#define PMU_HP_ANALOG_WAIT_TARGET_CYCLES        (2419)  /* Fast OSC as PMU work clock source is about 154 us */
+#define PMU_HP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES (32)
+#define PMU_HP_DIGITAL_POWER_UP_WAIT_CYCLES     (32)
+#define PMU_HP_MODEM_WAKEUP_WAIT_CYCLES         (20700) /* Fast OSC as PMU work clock source is about 1318.6 us */
+
+#define PMU_LP_WAKEUP_DELAY_CYCLES              (0)
+#define PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES (30)    /* Slow OSC as PMU slow clock source is about 201 us */
+#define PMU_LP_ANALOG_WAIT_TARGET_CYCLES        (23)    /* Slow OSC as PMU slow clock source is about 154 us */
+#define PMU_LP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES (32)    /* Fast OSC as PMU work clock source is about 2 us */
+#define PMU_LP_DIGITAL_POWER_UP_WAIT_CYCLES     (32)    /* Fast OSC as PMU work clock source is about 2 us */
+
+#define PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US  (500)    /* Slow OSC as PMU slow clock source in deepsleep is about 500 us */
+
+typedef struct {
+    struct {
+        pmu_hp_power_t  dig_power;
+        pmu_hp_power_t  clk_power;
+        pmu_hp_power_t  xtal;
+    } hp_sys;
+    struct {
+        pmu_lp_power_t  dig_power;
+        pmu_lp_power_t  clk_power;
+        pmu_lp_power_t  xtal;
+    } lp_sys[PMU_MODE_LP_MAX];
+} pmu_sleep_power_config_t;
+
+#define PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags) {                          \
+    .hp_sys = {                                                             \
+        .dig_power = {                                                      \
+            .vdd_spi_pd_en = ((pd_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 0,   \
+            .wifi_pd_en    = ((pd_flags) & PMU_SLEEP_PD_MODEM)   ? 1 : 0,   \
+            .cpu_pd_en     = ((pd_flags) & PMU_SLEEP_PD_CPU)     ? 1 : 0,   \
+            .aon_pd_en     = ((pd_flags) & PMU_SLEEP_PD_HP_AON)  ? 1 : 0,   \
+            .top_pd_en     = ((pd_flags) & PMU_SLEEP_PD_TOP)     ? 1 : 0,   \
+            .mem_pd_en     = 0,                                             \
+            .mem_dslp      = 0                                              \
+        },                                                                  \
+        .clk_power = {                                                      \
+            .i2c_iso_en    = 1,                                             \
+            .i2c_retention = 1,                                             \
+            .xpd_bb_i2c    = 0,                                             \
+            .xpd_bbpll_i2c = 0,                                             \
+            .xpd_bbpll     = 0                                              \
+        },                                                                  \
+        .xtal = {                                                           \
+            .xpd_xtal      = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1,      \
+        }                                                                   \
+    },                                                                      \
+    .lp_sys[PMU_MODE_LP_ACTIVE] = {                                         \
+        .dig_power = {                                                      \
+            .peri_pd_en    = 0,                                             \
+            .mem_dslp      = 0                                              \
+        },                                                                  \
+        .clk_power = {                                                      \
+            .xpd_xtal32k   = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1,   \
+            .xpd_rc32k     = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1,     \
+            .xpd_fosc      = 1                                              \
+        }                                                                   \
+    },                                                                      \
+    .lp_sys[PMU_MODE_LP_SLEEP] = {                                          \
+        .dig_power = {                                                      \
+            .peri_pd_en    = ((pd_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
+            .mem_dslp      = 1                                              \
+        },                                                                  \
+        .clk_power = {                                                      \
+            .xpd_xtal32k   = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1,   \
+            .xpd_rc32k     = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1,     \
+            .xpd_fosc      = ((pd_flags) & PMU_SLEEP_PD_RC_FAST) ? 0 : 1    \
+        },                                                                  \
+        .xtal = {                                                           \
+            .xpd_xtal      = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1,      \
+        }                                                                   \
+    }                                                                       \
+}
+
+typedef struct {
+    pmu_hp_sys_cntl_reg_t   syscntl;
+} pmu_sleep_digital_config_t;
+
+#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags) {               \
+    .syscntl = {                                                        \
+        .dig_pad_slp_sel = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1,     \
+    }                                                                   \
+}
+
+typedef struct {
+    struct {
+        pmu_hp_analog_t analog;
+    } hp_sys;
+    struct {
+        pmu_lp_analog_t analog;
+    } lp_sys[PMU_MODE_LP_MAX];
+} pmu_sleep_analog_config_t;
+
+#define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags) {            \
+    .hp_sys = {                                                     \
+        .analog = {                                                 \
+            .drv_b           = PMU_HP_DRVB_LIGHTSLEEP,              \
+            .pd_cur          = PMU_PD_CUR_SLEEP_DEFAULT,            \
+            .bias_sleep      = PMU_BIASSLP_SLEEP_DEFAULT,           \
+            .xpd             = PMU_HP_XPD_LIGHTSLEEP,               \
+            .dbg_atten       = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT,    \
+            .dbias           = PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT  \
+        }                                                           \
+    },                                                              \
+    .lp_sys[PMU_MODE_LP_SLEEP] = {                                  \
+        .analog = {                                                 \
+            .drv_b         = PMU_LP_DRVB_DEEPSLEEP,                 \
+            .pd_cur        = PMU_PD_CUR_SLEEP_DEFAULT,              \
+            .bias_sleep    = PMU_BIASSLP_SLEEP_DEFAULT,             \
+            .slp_xpd       = PMU_LP_SLP_XPD_SLEEP_DEFAULT,          \
+            .slp_dbias     = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT,        \
+            .xpd           = PMU_LP_XPD_SLEEP_DEFAULT,              \
+            .dbg_atten     = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT,      \
+            .dbias         = PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT    \
+        }                                                           \
+    }                                                               \
+}
+
+#define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags) {            \
+    .hp_sys = {                                                     \
+        .analog = {                                                 \
+            .pd_cur        = PMU_PD_CUR_SLEEP_ON,                   \
+            .bias_sleep    = PMU_BIASSLP_SLEEP_ON,                  \
+            .xpd           = PMU_HP_XPD_DEEPSLEEP,                  \
+            .dbg_atten     = PMU_DBG_HP_DEEPSLEEP                   \
+        }                                                           \
+    },                                                              \
+    .lp_sys[PMU_MODE_LP_SLEEP] = {                                  \
+        .analog = {                                                 \
+            .drv_b         = PMU_LP_DRVB_DEEPSLEEP,                 \
+            .pd_cur        = PMU_PD_CUR_SLEEP_DEFAULT,              \
+            .bias_sleep    = PMU_BIASSLP_SLEEP_DEFAULT,             \
+            .slp_xpd       = PMU_LP_SLP_XPD_SLEEP_DEFAULT,          \
+            .slp_dbias     = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT,        \
+            .xpd           = PMU_LP_XPD_SLEEP_DEFAULT,              \
+            .dbg_atten     = PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT,       \
+            .dbias         = PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT     \
+        }                                                           \
+    }                                                               \
+}
+
+typedef struct {
+    pmu_hp_param_t      hp_sys;
+    pmu_lp_param_t      lp_sys;
+    pmu_hp_lp_param_t   hp_lp;
+} pmu_sleep_param_config_t;
+
+#define PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags) {                                  \
+    .hp_sys = {                                                                     \
+        .min_slp_slow_clk_cycle          = PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES,        \
+        .analog_wait_target_cycle        = PMU_HP_ANALOG_WAIT_TARGET_CYCLES,        \
+        .digital_power_supply_wait_cycle = PMU_HP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES, \
+        .digital_power_up_wait_cycle     = PMU_HP_DIGITAL_POWER_UP_WAIT_CYCLES,     \
+        .modem_wakeup_wait_cycle         = PMU_HP_MODEM_WAKEUP_WAIT_CYCLES,         \
+        .pll_stable_wait_cycle           = PMU_HP_PLL_STABLE_WAIT_CYCLES            \
+    },                                                                              \
+    .lp_sys = {                                                                     \
+        .min_slp_slow_clk_cycle          = PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES,        \
+        .analog_wait_target_cycle        = PMU_LP_ANALOG_WAIT_TARGET_CYCLES,        \
+        .digital_power_supply_wait_cycle = PMU_LP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES, \
+        .digital_power_up_wait_cycle     = PMU_LP_DIGITAL_POWER_UP_WAIT_CYCLES      \
+    },                                                                              \
+    .hp_lp = {                                                                      \
+        .xtal_stable_wait_slow_clk_cycle = PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES  \
+    }                                                                               \
+}
+
+typedef struct {
+    pmu_sleep_power_config_t    power;
+    pmu_sleep_digital_config_t  digital;
+    pmu_sleep_analog_config_t   analog;
+    pmu_sleep_param_config_t    param;
+} pmu_sleep_config_t;
+
+typedef struct pmu_sleep_machine_constant {
+    struct {
+        uint16_t    min_slp_time_us;            /* Minimum sleep protection time (unit: microsecond) */
+        uint8_t     wakeup_wait_cycle;          /* Modem wakeup signal (WiFi MAC and BEACON wakeup) waits for the slow & fast clock domain synchronization and the wakeup signal triggers the PMU FSM switching wait cycle (unit: slow clock cycle) */
+        uint8_t     reserved0;
+        uint16_t    reserved1;
+        uint16_t    analog_wait_time_us;        /* LP LDO power up wait time (unit: microsecond) */
+        uint16_t    xtal_wait_stable_time_us;   /* Main XTAL stabilization wait time (unit: microsecond) */
+        uint8_t     clk_switch_cycle;           /* Clock switch to FOSC (unit: slow clock cycle) */
+        uint8_t     clk_power_on_wait_cycle;    /* Clock power on wait cycle (unit: slow clock cycle) */
+        uint16_t    power_supply_wait_time_us;  /* (unit: microsecond) */
+        uint16_t    power_up_wait_time_us;      /* (unit: microsecond) */
+    } lp;
+    struct {
+        uint16_t    min_slp_time_us;            /* Minimum sleep protection time (unit: microsecond) */
+        uint16_t    clock_domain_sync_time_us;  /* The Slow OSC clock domain synchronizes time with the Fast OSC domain, at least 4 slow clock cycles (unit: microsecond) */
+        uint16_t    system_dfs_up_work_time_us; /* System DFS up scaling work time (unit: microsecond) */
+        uint16_t    analog_wait_time_us;        /* HP LDO power up wait time (unit: microsecond) */
+        uint16_t    power_supply_wait_time_us;  /* (unit: microsecond) */
+        uint16_t    power_up_wait_time_us;      /* (unit: microsecond) */
+        uint16_t    regdma_s2m_work_time_us;    /* Modem Subsystem (S2M switch) REGDMA restore time (unit: microsecond) */
+        uint16_t    regdma_s2a_work_time_us;    /* SOC System (Digital Peripheral + Modem Subsystem) REGDMA (S2A switch) restore time (unit: microsecond) */
+        uint16_t    regdma_m2a_work_time_us;    /* Digital Peripheral (M2A switch) REGDMA restore time (unit: microsecond) */
+        uint16_t    regdma_a2s_work_time_us;    /* SOC System (Digital Peripheral + Modem Subsystem) REGDMA (A2S switch) backup time (unit: microsecond) */
+        uint16_t    regdma_rf_on_work_time_us;  /* The REGDMA work time of RF enable (unit: microsecond) */
+        uint16_t    regdma_rf_off_work_time_us; /* The REGDMA work time of RF disable (unit: microsecond) */
+        uint16_t    xtal_wait_stable_time_us;   /* Main XTAL stabilization wait time (unit: microsecond) */
+        uint16_t    pll_wait_stable_time_us;    /* PLL stabilization wait time (unit: microsecond) */
+    } hp;
+} pmu_sleep_machine_constant_t;
+
+#define PMU_SLEEP_MC_DEFAULT()      {           \
+    .lp = {                                     \
+        .min_slp_time_us                = 450,  \
+        .wakeup_wait_cycle              = 4,    \
+        .analog_wait_time_us            = 154,  \
+        .xtal_wait_stable_time_us       = 250,  \
+        .clk_switch_cycle               = 1,    \
+        .clk_power_on_wait_cycle        = 1,    \
+        .power_supply_wait_time_us      = 2,    \
+        .power_up_wait_time_us          = 2     \
+    },                                          \
+    .hp = {                                     \
+        .min_slp_time_us                = 450,  \
+        .clock_domain_sync_time_us      = 150,  \
+        .system_dfs_up_work_time_us     = 124,  \
+        .analog_wait_time_us            = 154,  \
+        .power_supply_wait_time_us      = 2,    \
+        .power_up_wait_time_us          = 2,    \
+        .regdma_s2m_work_time_us        = 172,  \
+        .regdma_s2a_work_time_us        = PMU_REGDMA_S2A_WORK_TIME_US, \
+        .regdma_m2a_work_time_us        = 278,  \
+        .regdma_a2s_work_time_us        = 382,  \
+        .regdma_rf_on_work_time_us      = 70,   \
+        .regdma_rf_off_work_time_us     = 23,   \
+        .xtal_wait_stable_time_us       = 250,  \
+        .pll_wait_stable_time_us        = 1     \
+    }                                           \
+}
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/esp_hw_support/port/esp32c61/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c
@ -0,0 +1,452 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <assert.h>
+#include <stdlib.h>
+#include "sdkconfig.h"
+#include "esp32c61/rom/rtc.h"
+#include "soc/rtc.h"
+#include "esp_private/rtc_clk.h"
+#include "esp_hw_log.h"
+#include "esp_rom_sys.h"
+#include "hal/clk_tree_ll.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "soc/io_mux_reg.h"
+#include "soc/lp_aon_reg.h"
+#include "esp_private/sleep_event.h"
+
+#if SOC_MODEM_CLOCK_SUPPORTED   //TODO: [ESP32C61] IDF-9513
+#ifdef BOOTLOADER_BUILD
+#include "hal/modem_lpcon_ll.h"
+#else
+#include "esp_private/esp_modem_clock.h"
+#endif
+#endif
+
+static const char *TAG = "rtc_clk";
+
+// Current PLL frequency, in 480MHz. Zero if PLL is not enabled.
+static int s_cur_pll_freq;
+
+static uint32_t s_bbpll_digi_consumers_ref_count = 0; // Currently, it only tracks whether the 48MHz PHY clock is in-use by USB Serial/JTAG
+
+void rtc_clk_bbpll_add_consumer(void)
+{
+    s_bbpll_digi_consumers_ref_count += 1;
+}
+
+void rtc_clk_bbpll_remove_consumer(void)
+{
+    s_bbpll_digi_consumers_ref_count -= 1;
+}
+
+void rtc_clk_32k_enable(bool enable)
+{
+    if (enable) {
+        clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL);
+    } else {
+        clk_ll_xtal32k_disable();
+    }
+}
+
+void rtc_clk_32k_enable_external(void)
+{
+    // EXT_OSC_SLOW_GPIO_NUM == GPIO_NUM_0
+    // PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG);
+    // REG_SET_BIT(LP_AON_GPIO_HOLD0_REG, BIT(EXT_OSC_SLOW_GPIO_NUM));
+    // clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL);
+}
+
+void rtc_clk_32k_bootstrap(uint32_t cycle)
+{
+    /* No special bootstrapping needed for ESP32-C61, 'cycle' argument is to keep the signature
+     * same as for the ESP32. Just enable the XTAL here.
+     */
+    (void)cycle;
+    rtc_clk_32k_enable(true);
+}
+
+bool rtc_clk_32k_enabled(void)
+{
+    return clk_ll_xtal32k_is_enabled();
+}
+
+void rtc_clk_rc32k_enable(bool enable)
+{
+    if (enable) {
+        clk_ll_rc32k_enable();
+        esp_rom_delay_us(SOC_DELAY_RC32K_ENABLE);
+    } else {
+        clk_ll_rc32k_disable();
+    }
+}
+
+void rtc_clk_8m_enable(bool clk_8m_en)
+{
+    if (clk_8m_en) {
+        clk_ll_rc_fast_enable();
+        esp_rom_delay_us(SOC_DELAY_RC_FAST_ENABLE);
+    } else {
+        clk_ll_rc_fast_disable();
+    }
+}
+
+bool rtc_clk_8m_enabled(void)
+{
+    return clk_ll_rc_fast_is_enabled();
+}
+
+void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
+{
+    clk_ll_rtc_slow_set_src(clk_src);
+    esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH);
+}
+
+soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
+{
+    return clk_ll_rtc_slow_get_src();
+}
+
+uint32_t rtc_clk_slow_freq_get_hz(void)
+{
+    switch (rtc_clk_slow_src_get()) {
+    case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX;
+    default: return 0;
+    }
+}
+
+void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src)
+{
+    clk_ll_rtc_fast_set_src(clk_src);
+    esp_rom_delay_us(SOC_DELAY_RTC_FAST_CLK_SWITCH);
+}
+
+soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
+{
+    return clk_ll_rtc_fast_get_src();
+}
+
+static void rtc_clk_bbpll_disable(void)
+{
+    clk_ll_bbpll_disable();
+    s_cur_pll_freq = 0;
+}
+
+static void rtc_clk_bbpll_enable(void)
+{
+    clk_ll_bbpll_enable();
+}
+
+static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
+{
+// TODO: [ESP32C61] IDF-9513, modem support
+#if SOC_MODEM_CLOCK_SUPPORTED
+#ifdef BOOTLOADER_BUILD
+    modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable);
+#else
+    if (enable) {
+        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
+    } else {
+        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
+    }
+#endif
+#endif  //SOC_MODEM_CLOCK_SUPPORTED
+}
+
+static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
+{
+    /* Digital part */
+    clk_ll_bbpll_set_freq_mhz(pll_freq);
+    /* Analog part */
+    rtc_clk_enable_i2c_ana_master_clock(true);
+    /* BBPLL CALIBRATION START */
+    regi2c_ctrl_ll_bbpll_calibration_start();
+    clk_ll_bbpll_set_config(pll_freq, xtal_freq);
+    /* WAIT CALIBRATION DONE */
+    while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
+    esp_rom_delay_us(10);
+    /* BBPLL CALIBRATION STOP */
+    regi2c_ctrl_ll_bbpll_calibration_stop();
+    rtc_clk_enable_i2c_ana_master_clock(false);
+    s_cur_pll_freq = pll_freq;
+}
+
+/**
+ * Switch to use XTAL as the CPU clock source.
+ * Must satisfy: cpu_freq = XTAL_FREQ / div.
+ * Does not disable the PLL.
+ */
+static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
+{
+    clk_ll_ahb_set_ls_divider(div);
+    clk_ll_cpu_set_ls_divider(div);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq);
+}
+
+static void rtc_clk_cpu_freq_to_8m(void)
+{
+    clk_ll_ahb_set_ls_divider(1);
+    clk_ll_cpu_set_ls_divider(1);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
+    esp_rom_set_cpu_ticks_per_us(20);
+}
+
+/**
+ * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
+ * PLL must already be enabled.
+ * @param cpu_freq new CPU frequency
+ */
+static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
+{
+    clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
+    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
+}
+
+bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
+{
+    uint32_t source_freq_mhz;
+    soc_cpu_clk_src_t source;
+    uint32_t divider; // divider = freq of SOC_ROOT_CLK / freq of CPU_CLK
+    uint32_t real_freq_mhz;
+
+    uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
+    if (freq_mhz <= xtal_freq && freq_mhz != 0) {
+        divider = xtal_freq / freq_mhz;
+        real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
+        if (real_freq_mhz != freq_mhz) {
+            // no suitable divider
+            return false;
+        }
+
+        source_freq_mhz = xtal_freq;
+        source = SOC_CPU_CLK_SRC_XTAL;
+    } else if (freq_mhz == 80) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_PLL;
+        source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
+        divider = 6;
+    } else if (freq_mhz == 120) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_PLL;
+        source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
+        divider = 4;
+    } else if (freq_mhz == 160) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_PLL;
+        source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
+        divider = 3;
+    } else {
+        // unsupported frequency
+        return false;
+    }
+    *out_config = (rtc_cpu_freq_config_t) {
+        .source = source,
+        .div = divider,
+        .source_freq_mhz = source_freq_mhz,
+        .freq_mhz = real_freq_mhz
+    };
+    return true;
+}
+
+__attribute__((weak)) void rtc_clk_set_cpu_switch_to_bbpll(int event_id)
+{
+}
+
+void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
+{
+    soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
+    if (config->source == SOC_CPU_CLK_SRC_XTAL) {
+        rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
+        if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
+            // We don't turn off the bbpll if some consumers depend on bbpll
+            rtc_clk_bbpll_disable();
+        }
+    } else if (config->source == SOC_CPU_CLK_SRC_PLL) {
+        if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL) {
+            rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_PLL_EN_START);
+            rtc_clk_bbpll_enable();
+            rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
+        }
+        rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
+        rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_PLL_EN_STOP);
+    } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
+        rtc_clk_cpu_freq_to_8m();
+        if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
+            // We don't turn off the bbpll if some consumers depend on bbpll
+            rtc_clk_bbpll_disable();
+        }
+    }
+}
+
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
+{
+    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
+    uint32_t source_freq_mhz;
+    uint32_t div; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
+    uint32_t freq_mhz;
+    switch (source) {
+    case SOC_CPU_CLK_SRC_XTAL: {
+        div = clk_ll_cpu_get_ls_divider();
+        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
+        freq_mhz = source_freq_mhz / div;
+        break;
+    }
+    case SOC_CPU_CLK_SRC_PLL: {
+        div = clk_ll_cpu_get_hs_divider();
+        source_freq_mhz = clk_ll_bbpll_get_freq_mhz();
+        freq_mhz = source_freq_mhz / div;
+        break;
+    }
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        div = clk_ll_cpu_get_ls_divider();
+        source_freq_mhz = 20;
+        freq_mhz = source_freq_mhz / div;
+        break;
+    default:
+        ESP_HW_LOGE(TAG, "unsupported frequency configuration");
+        abort();
+    }
+    *out_config = (rtc_cpu_freq_config_t) {
+        .source = source,
+        .source_freq_mhz = source_freq_mhz,
+        .div = div,
+        .freq_mhz = freq_mhz
+    };
+}
+
+void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
+{
+    if (config->source == SOC_CPU_CLK_SRC_XTAL) {
+        rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
+    } else if (config->source == SOC_CPU_CLK_SRC_PLL &&
+               s_cur_pll_freq == config->source_freq_mhz) {
+        rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
+    } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
+        rtc_clk_cpu_freq_to_8m();
+    } else {
+        /* fallback */
+        rtc_clk_cpu_freq_set_config(config);
+    }
+}
+
+void rtc_clk_cpu_freq_set_xtal(void)
+{
+    rtc_clk_cpu_set_to_default_config();
+    // We don't turn off the bbpll if some consumers depend on bbpll
+    if (!s_bbpll_digi_consumers_ref_count) {
+        rtc_clk_bbpll_disable();
+    }
+}
+
+void rtc_clk_cpu_set_to_default_config(void)
+{
+    int freq_mhz = (int)rtc_clk_xtal_freq_get();
+
+    rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
+}
+
+void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
+{
+    rtc_clk_cpu_freq_to_pll_mhz(cpu_freq_mhz);
+    clk_ll_cpu_clk_src_lock_release();
+}
+
+soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
+{
+    uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
+    if (xtal_freq_mhz == 0) {
+        ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
+        return SOC_XTAL_FREQ_40M;
+    }
+    return (soc_xtal_freq_t)xtal_freq_mhz;
+}
+
+void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
+{
+    clk_ll_xtal_store_freq_mhz(xtal_freq);
+}
+
+static uint32_t rtc_clk_ahb_freq_get(void)
+{
+    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
+    uint32_t soc_root_freq_mhz;
+    uint32_t divider;
+    switch (source) {
+    case SOC_CPU_CLK_SRC_XTAL:
+        soc_root_freq_mhz = rtc_clk_xtal_freq_get();
+        divider = clk_ll_ahb_get_ls_divider();
+        break;
+    case SOC_CPU_CLK_SRC_PLL:
+        soc_root_freq_mhz = clk_ll_bbpll_get_freq_mhz();
+        divider = clk_ll_ahb_get_hs_divider();
+        break;
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        soc_root_freq_mhz = 20;
+        divider = clk_ll_ahb_get_ls_divider();
+        break;
+    default:
+        // Unknown SOC_ROOT clock source
+        soc_root_freq_mhz = 0;
+        divider = 1;
+        ESP_HW_LOGE(TAG, "Invalid SOC_ROOT_CLK");
+        break;
+    }
+    return soc_root_freq_mhz / divider;
+}
+
+uint32_t rtc_clk_apb_freq_get(void)
+{
+    return rtc_clk_ahb_freq_get() / clk_ll_apb_get_divider() * MHZ;
+}
+
+void rtc_dig_clk8m_enable(void)
+{
+    clk_ll_rc_fast_digi_enable();
+    esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
+}
+
+void rtc_dig_clk8m_disable(void)
+{
+    clk_ll_rc_fast_digi_disable();
+    esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
+}
+
+bool rtc_dig_8m_enabled(void)
+{
+    return clk_ll_rc_fast_digi_is_enabled();
+}
+
+// Workaround for bootloader not calibrated well issue.
+// Placed in IRAM because disabling BBPLL may influence the cache
+void rtc_clk_recalib_bbpll(void)
+{
+    rtc_cpu_freq_config_t old_config;
+    rtc_clk_cpu_freq_get_config(&old_config);
+
+    // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
+    // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
+    //   Turn off the BBPLL and do calibration again to fix the issue.
+    // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
+    //   requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
+    if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
+        rtc_clk_cpu_freq_set_xtal();
+        rtc_clk_cpu_freq_set_config(&old_config);
+    }
+}
+
+
+/* Name used in libphy.a:phy_chip_v7.o
+ * TODO: update the library to use rtc_clk_xtal_freq_get
+ */
+rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));
--- a/components/esp_hw_support/port/esp32c61/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32c61/rtc_clk_init.c
@ -0,0 +1,130 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <stdlib.h>
+#include "esp32c61/rom/ets_sys.h"
+#include "esp32c61/rom/rtc.h"
+#include "esp32c61/rom/uart.h"
+#include "soc/rtc.h"
+#include "esp_cpu.h"
+#include "regi2c_ctrl.h"
+#include "soc/lp_clkrst_reg.h"
+#include "soc/regi2c_dig_reg.h"
+#include "esp_hw_log.h"
+#include "sdkconfig.h"
+#include "esp_rom_uart.h"
+#include "esp_private/esp_pmu.h"
+#include "hal/clk_tree_ll.h"
+#include "hal/pmu_ll.h"
+#if SOC_MODEM_CLOCK_SUPPORTED   //TODO: [ESP32C61] IDF-9513
+#include "hal/modem_syscon_ll.h"
+#include "hal/modem_lpcon_ll.h"
+#endif
+#include "soc/pmu_reg.h"
+#include "pmu_param.h"
+
+static const char *TAG = "rtc_clk_init";
+
+/**
+ * Initialize the ICG map of some modem clock domains in the PMU_ACTIVE state
+ *
+ * A pre-initialization interface is used to initialize the ICG map of the
+ * MODEM_APB, I2C_MST and LP_APB clock domains in the PMU_ACTIVE state, and
+ * disable the clock gating of these clock domains in the PMU_ACTIVE state,
+ * because the system clock source (PLL) in the system boot up process needs
+ * to use the i2c master peripheral.
+ *
+ * ICG map of all modem clock domains under different power states (PMU_ACTIVE,
+ * PMU_MODEM and PMU_SLEEP) will be initialized in esp_perip_clk_init().
+ */
+static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void)
+{
+    /* Configure modem ICG code in PMU_ACTIVE state */
+    pmu_ll_hp_set_icg_modem(&PMU, PMU_MODE_HP_ACTIVE, PMU_HP_ICG_MODEM_CODE_ACTIVE);
+
+// TODO: [ESP32C61] IDF-9513, modem support
+#if SOC_MODEM_CLOCK_SUPPORTED
+    /* Disable clock gating for MODEM_APB, I2C_MST and LP_APB clock domains in PMU_ACTIVE state */
+    modem_syscon_ll_set_modem_apb_icg_bitmap(&MODEM_SYSCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
+    modem_lpcon_ll_set_i2c_master_icg_bitmap(&MODEM_LPCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
+    modem_lpcon_ll_set_lp_apb_icg_bitmap(&MODEM_LPCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
+#endif
+
+    /* Software trigger force update modem ICG code and ICG switch */
+    pmu_ll_imm_update_dig_icg_modem_code(&PMU, true);
+    pmu_ll_imm_update_dig_icg_switch(&PMU, true);
+}
+
+void rtc_clk_init(rtc_clk_config_t cfg)
+{
+    rtc_cpu_freq_config_t old_config, new_config;
+
+    rtc_clk_modem_clock_domain_active_state_icg_map_preinit();
+
+    /* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks.
+     * Note: this doesn't attempt to set the clocks to precise frequencies.
+     * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
+     * - SCK_DCAP value controls tuning of RC_SLOW clock.
+     *   The higher the value of DCAP is, the lower is the frequency.
+     * - CK8M_DFREQ value controls tuning of RC_FAST clock.
+     *   CLK_8M_DFREQ constant gives the best temperature characteristics.
+     * - RC32K_DFREQ value controls tuning of RC32K clock.
+     */
+    REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq);
+    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap);
+    REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq);
+    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
+    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
+
+    uint32_t hp_cali_dbias = get_act_hp_dbias();
+    uint32_t lp_cali_dbias = get_act_lp_dbias();
+
+    SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
+    SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S);
+    SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
+
+    clk_ll_rc_fast_tick_conf();
+
+    soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
+    esp_rom_output_tx_wait_idle(0);
+    rtc_clk_xtal_freq_update(xtal_freq);
+
+    // On ESP32C61, MSPI source clock's default HS divider leads to 120MHz, which is unusable before calibration
+    // Therefore, before switching SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider to make it run at
+    // 80MHz after the switch. PLL = 480MHz, so divider is 6.
+    clk_ll_mspi_fast_set_hs_divider(6);
+
+    /* Set CPU frequency */
+    rtc_clk_cpu_freq_get_config(&old_config);
+    uint32_t freq_before = old_config.freq_mhz;
+    bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
+    if (!res) {
+        ESP_HW_LOGE(TAG, "invalid CPU frequency value");
+        abort();
+    }
+    rtc_clk_cpu_freq_set_config(&new_config);
+
+    /* Re-calculate the ccount to make time calculation correct. */
+    esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
+
+    /* Slow & fast clocks setup */
+    // We will not power off RC_FAST in bootloader stage even if it is not being used as any
+    // cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
+    bool need_rc_fast_en = true;
+    if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
+        rtc_clk_32k_enable(true);
+    } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+        rtc_clk_32k_enable_external();
+    } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
+       rtc_clk_rc32k_enable(true);
+    }
+    rtc_clk_8m_enable(need_rc_fast_en);
+    rtc_clk_fast_src_set(cfg.fast_clk_src);
+    rtc_clk_slow_src_set(cfg.slow_clk_src);
+}
--- a/components/esp_hw_support/port/esp32c61/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c61/rtc_time.c
@ -0,0 +1,288 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "esp32c61/rom/ets_sys.h"
+#include "soc/rtc.h"
+#include "hal/lp_timer_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "hal/timer_ll.h"
+#include "soc/timer_group_reg.h"
+#include "esp_rom_sys.h"
+#include "assert.h"
+#include "hal/efuse_hal.h"
+#include "soc/chip_revision.h"
+#include "esp_private/periph_ctrl.h"
+
+static const char *TAG = "rtc_time";
+
+/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
+ * This feature counts the number of XTAL clock cycles within a given number of
+ * RTC_SLOW_CLK cycles.
+ *
+ * Slow clock calibration feature has two modes of operation: one-off and cycling.
+ * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
+ * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
+ * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
+ * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
+ * enabled using TIMG_RTC_CALI_START bit.
+ */
+
+/* On ESP32C61, TIMG_RTC_CALI_CLK_SEL can config to 0, 1, 2, 3
+ * 0 or 3: calibrate RC_SLOW clock
+ * 1: calibrate RC_FAST clock
+ * 2: calibrate 32K clock, which 32k depends on reg_32k_sel: 0: Internal 32 kHz RC oscillator, 1: External 32 kHz XTAL, 2: External 32kHz clock input by lp_pad_gpio0
+ */
+#define TIMG_RTC_CALI_CLK_SEL_RC_SLOW 0
+#define TIMG_RTC_CALI_CLK_SEL_RC_FAST 1
+#define TIMG_RTC_CALI_CLK_SEL_32K     2
+
+/**
+ * @brief Clock calibration function used by rtc_clk_cal
+ *
+ * Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
+ * This feature counts the number of XTAL clock cycles within a given number of
+ * RTC_SLOW_CLK cycles.
+ *
+ * Slow clock calibration feature has two modes of operation: one-off and cycling.
+ * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
+ * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
+ * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
+ * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
+ * enabled using TIMG_RTC_CALI_START bit.
+ *
+ * @param cal_clk which clock to calibrate
+ * @param slowclk_cycles number of slow clock cycles to count
+ * @return number of XTAL clock cycles within the given number of slow clock cycles
+ */
+static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
+
+    uint32_t cali_clk_sel = 0;
+    soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
+    soc_rtc_slow_clk_src_t old_32k_cal_clk_sel = clk_ll_32k_calibration_get_target();
+    if (cal_clk == RTC_CAL_RTC_MUX) {
+        cal_clk = (rtc_cal_sel_t)slow_clk_src;
+    }
+    if (cal_clk == RTC_CAL_RC_FAST) {
+        cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST;
+    } else if (cal_clk == RTC_CAL_RC_SLOW) {
+        cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW;
+    } else {
+        cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_32K;
+        clk_ll_32k_calibration_set_target((soc_rtc_slow_clk_src_t)cal_clk);
+    }
+
+
+    /* Enable requested clock (150k clock is always on) */
+    // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
+    // Only enable if originally was disabled, and set back to the disable state after calibration is done
+    // If the clock is already on, then do nothing
+    bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
+    if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
+            clk_ll_xtal32k_digi_enable();
+    }
+
+    bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
+    bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
+    if (cal_clk == RTC_CAL_RC_FAST) {
+        if (!rc_fast_enabled) {
+            rtc_clk_8m_enable(true);
+        }
+        if (!dig_rc_fast_enabled) {
+            rtc_dig_clk8m_enable();
+        }
+    }
+
+    bool rc32k_enabled = clk_ll_rc32k_is_enabled();
+    bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
+    if (cal_clk == RTC_CAL_RC32K) {
+        if (!rc32k_enabled) {
+            rtc_clk_rc32k_enable(true);
+        }
+        if (!dig_rc32k_enabled) {
+            clk_ll_rc32k_digi_enable();
+        }
+    }
+
+    /* There may be another calibration process already running during we call this function,
+     * so we should wait the last process is done.
+     */
+    if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
+        /**
+         * Set a small timeout threshold to accelerate the generation of timeout.
+         * The internal circuit will be reset when the timeout occurs and will not affect the next calibration.
+         */
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1);
+        while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
+               && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
+    }
+
+    /* Prepare calibration */
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
+    /* Figure out how long to wait for calibration to finish */
+
+    /* Set timeout reg and expect time delay*/
+    uint32_t expected_freq;
+    if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_32K) {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
+        expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
+    } else if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles));
+        expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
+    } else {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
+        expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
+    }
+    uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
+    /* Start calibration */
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+    SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+
+    /* Wait for calibration to finish up to another us_time_estimate */
+    esp_rom_delay_us(us_time_estimate);
+    uint32_t cal_val;
+    while (true) {
+        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
+            cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
+
+            /*The Fosc CLK of calibration circuit is divided by 32 for ECO1.
+              So we need to multiply the frequency of the Fosc for ECO1 and above chips by 32 times.
+              And ensure that this modification will not affect ECO0.*/
+            if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
+                if (cal_clk == RTC_CAL_RC_FAST) {
+                    cal_val = cal_val >> 5;
+                }
+            }
+            break;
+        }
+        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
+            cal_val = 0;
+            break;
+        }
+    }
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+
+    /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
+    if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
+        clk_ll_xtal32k_digi_disable();
+    }
+
+    if (cal_clk == RTC_CAL_RC_FAST) {
+        if (!dig_rc_fast_enabled) {
+            rtc_dig_clk8m_disable();
+        }
+        if (!rc_fast_enabled) {
+            rtc_clk_8m_enable(false);
+        }
+    }
+
+    if (cal_clk == RTC_CAL_RC32K) {
+        if (!dig_rc32k_enabled) {
+            clk_ll_rc32k_digi_disable();
+        }
+        if (!rc32k_enabled) {
+            rtc_clk_rc32k_enable(false);
+        }
+    }
+
+    // Always set back the calibration 32kHz clock selection
+    if (old_32k_cal_clk_sel != SOC_RTC_SLOW_CLK_SRC_INVALID) {
+        clk_ll_32k_calibration_set_target(old_32k_cal_clk_sel);
+    }
+
+    return cal_val;
+}
+
+static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
+{
+    uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
+    uint64_t delta = expected_xtal_cycles / 2000;                                    // 5/10000 = 0.05% error range
+    return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
+}
+
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    assert(slowclk_cycles);
+    soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
+
+    /*The Fosc CLK of calibration circuit is divided by 32 for ECO1.
+      So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
+      avoid excessive calibration time.*/
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
+        if (cal_clk == RTC_CAL_RC_FAST) {
+            slowclk_cycles = slowclk_cycles >> 5;
+        }
+    }
+
+    uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
+
+    if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
+        return 0;
+    }
+
+    uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
+    uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
+    uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
+    return period;
+}
+
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
+{
+    assert(period);
+    /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
+     * TODO: fix overflow.
+     */
+    return (time_in_us << RTC_CLK_CAL_FRACT) / period;
+}
+
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
+{
+    return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
+}
+
+uint64_t rtc_time_get(void)
+{
+    // return lp_timer_hal_get_cycle_count();
+    ESP_EARLY_LOGW(TAG, "rtc_timer has not been implemented yet");
+    return 0;
+}
+
+void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
+{
+    // TODO: IDF-5781
+    ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
+}
+
+uint32_t rtc_clk_freq_cal(uint32_t cal_val)
+{
+    if (cal_val == 0) {
+        return 0;   // cal_val will be denominator, return 0 as the symbol of failure.
+    }
+    return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
+}
+
+/// @brief if the calibration is used, we need to enable the timer group0 first
+__attribute__((constructor))
+static void enable_timer_group0_for_calibration(void)
+{
+#ifndef BOOTLOADER_BUILD
+    PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) {
+        if (ref_count == 0) {
+            timer_ll_enable_bus_clock(0, true);
+            timer_ll_reset_register(0);
+        }
+    }
+#else
+    // no critical section is needed for bootloader
+    int __DECLARE_RCC_RC_ATOMIC_ENV;
+    timer_ll_enable_bus_clock(0, true);
+    timer_ll_reset_register(0);
+#endif
+}
--- a/components/esp_hw_support/port/esp32c61/systimer.c
+++ b/components/esp_hw_support/port/esp32c61/systimer.c
@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_private/systimer.h"
+
+/**
+ * @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5).
+ *        So the resolution of the systimer is 40MHz/2.5 = 16MHz.
+ */
+
+uint64_t systimer_ticks_to_us(uint64_t ticks)
+{
+    return ticks / 16;
+}
+
+uint64_t systimer_us_to_ticks(uint64_t us)
+{
+    return us * 16;
+}
--- a/components/esp_hw_support/rtc_module.c
+++ b/components/esp_hw_support/rtc_module.c
@ -20,20 +20,22 @@
 #include "esp_private/rtc_ctrl.h"
 #include "esp_attr.h"

+//TODO: [ESP32C61] IDF-9331, c61 don't have lp-core, check
+
 #ifndef NDEBUG
 // Enable built-in checks in queue.h in debug builds
 #define INVARIANTS
 #endif
 #include "sys/queue.h"

-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8008
+#if !SOC_LP_PERIPH_SHARE_INTERRUPT // TODO: IDF-8008
 static const char *TAG = "rtc_module";
 #endif

 // rtc_spinlock is used by other peripheral drivers
 portMUX_TYPE rtc_spinlock = portMUX_INITIALIZER_UNLOCKED;

-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8008
+#if SOC_LP_PERIPH_SHARE_INTERRUPT // TODO: IDF-8008

 #define NOT_REGISTERED      (-1)

@ -97,11 +99,11 @@ out:
    portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock);
    return err;
 }
-#endif // !CONFIG_IDF_TARGET_ESP32C6 TODO: IDF-8008
+#endif // SOC_LP_PERIPH_SHARE_INTERRUPT TODO: IDF-8008

 esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t rtc_intr_mask, uint32_t flags)
 {
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8008
+#if !SOC_LP_PERIPH_SHARE_INTERRUPT // TODO: IDF-8008
    ESP_EARLY_LOGW(TAG, "rtc_isr_register() has not been implemented yet");
    return ESP_OK;
 #else
@ -132,7 +134,7 @@ esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t r

 esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
 {
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8008
+#if !SOC_LP_PERIPH_SHARE_INTERRUPT // TODO: IDF-8008
    ESP_EARLY_LOGW(TAG, "rtc_isr_deregister() has not been implemented yet");
    return ESP_OK;
 #else
@ -161,7 +163,7 @@ esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
 #endif
 }

-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8008
+#if SOC_LP_PERIPH_SHARE_INTERRUPT // TODO: IDF-8008
 /**
 * @brief This helper function can be used to avoid the interrupt to be triggered with cache disabled.
 *        There are lots of different signals on RTC module (i.e. sleep_wakeup, wdt, brownout_detect, etc.)
@ -184,7 +186,7 @@ static void s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask)

 IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu)
 {
-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8008
+#if SOC_LP_PERIPH_SHARE_INTERRUPT // TODO: IDF-8008
    if (rtc_isr_cpu == cpu) {
        rtc_intr_enabled |= RTCCNTL.int_ena.val;
        RTCCNTL.int_ena.val &= rtc_intr_cache;
@ -194,7 +196,7 @@ IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu)

 IRAM_ATTR void rtc_isr_noniram_enable(uint32_t cpu)
 {
-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8008
+#if SOC_LP_PERIPH_SHARE_INTERRUPT // TODO: IDF-8008
    if (rtc_isr_cpu == cpu) {
        RTCCNTL.int_ena.val = rtc_intr_enabled;
        rtc_intr_enabled = 0;
--- a/components/esp_mm/port/esp32c61/ext_mem_layout.c
+++ b/components/esp_mm/port/esp32c61/ext_mem_layout.c
@ -0,0 +1,26 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "soc/ext_mem_defs.h"
+#include "../ext_mem_layout.h"
+#include "hal/mmu_types.h"
+
+/**
+ * The start addresses in this list should always be sorted from low to high, as MMU driver will need to
+ * coalesce adjacent regions
+ */
+const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
+    [0] = {
+        .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
+        .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
+        .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
+        .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
+    },
+};
--- a/components/esp_pm/pm_impl.c
+++ b/components/esp_pm/pm_impl.c
@ -93,6 +93,8 @@
 #define REF_CLK_DIV_MIN 2
 #elif CONFIG_IDF_TARGET_ESP32C6
 #define REF_CLK_DIV_MIN 2
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define REF_CLK_DIV_MIN 2
 #elif CONFIG_IDF_TARGET_ESP32C5
 #define REF_CLK_DIV_MIN 2
 #elif CONFIG_IDF_TARGET_ESP32H2
--- a/components/esptool_py/Kconfig.projbuild
+++ b/components/esptool_py/Kconfig.projbuild
@ -91,7 +91,8 @@ menu "Serial flasher config"
    choice ESPTOOLPY_FLASHFREQ
        prompt "Flash SPI speed"
        # TODO: [ESP32C5] IDF-8649 switch back to 80M
-        default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C5
+        # TODO: [ESP32C61] IDF-9256
+        default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
        default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT
        default ESPTOOLPY_FLASHFREQ_60M if IDF_TARGET_ESP32C2
        config ESPTOOLPY_FLASHFREQ_120M
--- a/components/hal/esp32c5/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32c5/include/hal/clk_gate_ll.h
@ -1,72 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "hal/assert.h"
-#include "soc/periph_defs.h"
-#include "soc/pcr_reg.h"
-#include "soc/soc.h"
-#include "soc/soc_caps.h"
-#include "esp_attr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
-{
-    // Only add peripherals that haven't implemented clock enable by their own ll function
-    return 0;
-}
-
-static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable)
-{
-    // Only add peripherals that haven't implemented reset by their own ll function
-    return 0;
-}
-
-static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
-{
-    // Only add peripherals that haven't implemented clock enable by their own ll function
-    return 0;
-}
-
-static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
-{
-    // Only add peripherals that haven't implemented reset by their own ll function
-    return 0;
-}
-
-static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
-{
-    SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
-}
-
-static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
-{
-    CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-}
-
-static inline void periph_ll_reset(periph_module_t periph)
-{
-    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-}
-
-static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
-{
-    return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
-           REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/hal/esp32c61/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32c61/include/hal/clk_gate_ll.h
@ -1,217 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "hal/assert.h"
-#include "soc/periph_defs.h"
-#include "soc/pcr_reg.h"
-#include "soc/soc.h"
-#include "soc/soc_caps.h"
-#include "esp_attr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// TODO: [ESP32C61] IDF-9249, inherit from c6
-
-static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
-{
-    switch (periph) {
-        case PERIPH_SARADC_MODULE:
-            return PCR_SARADC_CLK_EN;
-        case PERIPH_LEDC_MODULE:
-            return PCR_LEDC_CLK_EN;
-        case PERIPH_UART0_MODULE:
-            return PCR_UART0_CLK_EN;
-        case PERIPH_UART1_MODULE:
-            return PCR_UART1_CLK_EN;
-        case PERIPH_I2C0_MODULE:
-            return PCR_I2C_CLK_EN;
-        case PERIPH_I2S1_MODULE:
-            return PCR_I2S_CLK_EN;
-        case PERIPH_TIMG0_MODULE:
-            return PCR_TG0_CLK_EN;
-        case PERIPH_TIMG1_MODULE:
-            return PCR_TG1_CLK_EN;
-        case PERIPH_SYSTIMER_MODULE:
-            return PCR_SYSTIMER_CLK_EN;
-        case PERIPH_SPI_MODULE:
-            return PCR_MSPI_CLK_EN;
-        case PERIPH_SPI2_MODULE:
-            return PCR_SPI2_CLK_EN;
-        case PERIPH_GDMA_MODULE:
-            return PCR_GDMA_CLK_EN;
-        case PERIPH_SHA_MODULE:
-            return PCR_SHA_CLK_EN;
-        case PERIPH_ECC_MODULE:
-            return PCR_ECC_CLK_EN;
-        case PERIPH_TEMPSENSOR_MODULE:
-            return PCR_TSENS_CLK_EN;
-        case PERIPH_ASSIST_DEBUG_MODULE:
-            return PCR_ASSIST_CLK_EN;
-        default:
-            return 0;
-    }
-}
-
-static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable)
-{
-    (void)enable; // unused
-
-    switch (periph) {
-        case PERIPH_SARADC_MODULE:
-            return PCR_SARADC_RST_EN;
-        case PERIPH_LEDC_MODULE:
-            return PCR_LEDC_RST_EN;
-        case PERIPH_UART0_MODULE:
-            return PCR_UART0_RST_EN;
-        case PERIPH_UART1_MODULE:
-            return PCR_UART1_RST_EN;
-        case PERIPH_I2C0_MODULE:
-            return PCR_I2C_RST_EN;
-        case PERIPH_I2S1_MODULE:
-            return PCR_I2S_RST_EN;
-        case PERIPH_TIMG0_MODULE:
-            return PCR_TG0_RST_EN;
-        case PERIPH_TIMG1_MODULE:
-            return PCR_TG1_RST_EN;
-        case PERIPH_SYSTIMER_MODULE:
-            return PCR_SYSTIMER_RST_EN;
-        case PERIPH_SPI_MODULE:
-            return PCR_MSPI_RST_EN;
-        case PERIPH_SPI2_MODULE:
-            return PCR_SPI2_RST_EN;
-        case PERIPH_GDMA_MODULE:
-            return PCR_GDMA_RST_EN;
-        case PERIPH_ECC_MODULE:
-            return PCR_ECC_RST_EN;
-        case PERIPH_TEMPSENSOR_MODULE:
-            return PCR_TSENS_RST_EN;
-        case PERIPH_SHA_MODULE:
-            if (enable == true) {
-                // Clear reset on digital signature and HMAC, otherwise SHA is held in reset
-                CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
-                CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
-            }
-            return PCR_SHA_RST_EN;
-        case PERIPH_ASSIST_DEBUG_MODULE:
-            return PCR_ASSIST_RST_EN;
-        default:
-            return 0;
-    }
-}
-
-static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
-{
-    switch (periph) {
-        case PERIPH_SARADC_MODULE:
-            return PCR_SARADC_CONF_REG;
-        case PERIPH_LEDC_MODULE:
-            return PCR_LEDC_CONF_REG;
-        case PERIPH_UART0_MODULE:
-            return PCR_UART0_CONF_REG;
-        case PERIPH_UART1_MODULE:
-            return PCR_UART1_CONF_REG;
-        case PERIPH_I2C0_MODULE:
-            return PCR_I2C_CONF_REG;
-        case PERIPH_I2S1_MODULE:
-            return PCR_I2S_CONF_REG;
-        case PERIPH_TIMG0_MODULE:
-            return PCR_TIMERGROUP0_CONF_REG;
-        case PERIPH_TIMG1_MODULE:
-            return PCR_TIMERGROUP1_CONF_REG;
-        case PERIPH_SYSTIMER_MODULE:
-            return PCR_SYSTIMER_CONF_REG;
-        case PERIPH_SPI_MODULE:
-            return PCR_MSPI_CONF_REG;
-        case PERIPH_SPI2_MODULE:
-            return PCR_SPI2_CONF_REG;
-        case PERIPH_GDMA_MODULE:
-            return PCR_GDMA_CONF_REG;
-        case PERIPH_SHA_MODULE:
-            return PCR_SHA_CONF_REG;
-        case PERIPH_ECC_MODULE:
-            return PCR_ECC_CONF_REG;
-        case PERIPH_TEMPSENSOR_MODULE:
-            return PCR_TSENS_CLK_CONF_REG;
-        case PERIPH_ASSIST_DEBUG_MODULE:
-            return PCR_ASSIST_CONF_REG;
-    default:
-        return 0;
-    }
-}
-
-static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
-{
-    switch (periph) {
-        case PERIPH_SARADC_MODULE:
-            return PCR_SARADC_CONF_REG;
-        case PERIPH_LEDC_MODULE:
-            return PCR_LEDC_CONF_REG;
-        case PERIPH_UART0_MODULE:
-            return PCR_UART0_CONF_REG;
-        case PERIPH_UART1_MODULE:
-            return PCR_UART1_CONF_REG;
-        case PERIPH_I2C0_MODULE:
-            return PCR_I2C_CONF_REG;
-        case PERIPH_I2S1_MODULE:
-            return PCR_I2S_CONF_REG;
-        case PERIPH_TIMG0_MODULE:
-            return PCR_TIMERGROUP0_CONF_REG;
-        case PERIPH_TIMG1_MODULE:
-            return PCR_TIMERGROUP1_CONF_REG;
-        case PERIPH_SYSTIMER_MODULE:
-            return PCR_SYSTIMER_CONF_REG;
-        case PERIPH_SPI_MODULE:
-            return PCR_MSPI_CONF_REG;
-        case PERIPH_SPI2_MODULE:
-            return PCR_SPI2_CONF_REG;
-        case PERIPH_GDMA_MODULE:
-            return PCR_GDMA_CONF_REG;
-        case PERIPH_SHA_MODULE:
-            return PCR_SHA_CONF_REG;
-        case PERIPH_ECC_MODULE:
-            return PCR_ECC_CONF_REG;
-        case PERIPH_TEMPSENSOR_MODULE:
-            return PCR_TSENS_CLK_CONF_REG;
-        case PERIPH_ASSIST_DEBUG_MODULE:
-            return PCR_ASSIST_CONF_REG;
-    default:
-        return 0;
-    }
-}
-
-static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
-{
-    SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
-}
-
-static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
-{
-    CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-}
-
-static inline void periph_ll_reset(periph_module_t periph)
-{
-    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-}
-
-static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
-{
-    return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
-           REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/heap/port/esp32c61/memory_layout.c
+++ b/components/heap/port/esp32c61/memory_layout.c
@ -0,0 +1,100 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "esp_attr.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "heap_memory_layout.h"
+#include "esp_heap_caps.h"
+
+//TODO: [ESP32C61] IDF-9253
+
+/**
+ * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
+ * Each type of memory map consists of one or more regions in the address space.
+ * Each type contains an array of prioritized capabilities.
+ * Types with later entries are only taken if earlier ones can't fulfill the memory request.
+ *
+ * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
+ * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
+ * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
+ * - Most other malloc caps only fit in one region anyway.
+ *
+ */
+
+/* Index of memory in `soc_memory_types[]` */
+enum {
+    SOC_MEMORY_TYPE_RAM     = 0,
+    SOC_MEMORY_TYPE_RTCRAM  = 1,
+    SOC_MEMORY_TYPE_NUM,
+};
+
+/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
+#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
+#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
+#else
+#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
+#endif
+
+/**
+ * Defined the attributes and allocation priority of each memory on the chip,
+ * The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
+ * if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
+ * in turn to continue matching.
+ */
+const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
+    /*                           Mem Type Name   High Priority Matching                      Medium Priority Matching    Low Priority Matching */
+    [SOC_MEMORY_TYPE_RAM]    = { "RAM",          { ESP32C6_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0,                         0 }},
+    [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM",       { MALLOC_CAP_RTCRAM,                        ESP32C6_MEM_COMMON_CAPS,   0 }},
+};
+
+const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
+
+/**
+ * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
+ *
+ * @note Because of requirements in the coalescing code which merges adjacent regions,
+ *       this list should always be sorted from low to high by start address.
+ *
+ */
+
+/**
+ * Register the shared buffer area of the last memory block into the heap during heap initialization
+ */
+#define APP_USABLE_DRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
+
+const soc_memory_region_t soc_memory_regions[] = {
+    { 0x40800000,           0x20000,                                   SOC_MEMORY_TYPE_RAM, 0x40800000,             false}, //D/IRAM level0, can be used as trace memory
+    { 0x40820000,           0x20000,                                   SOC_MEMORY_TYPE_RAM, 0x40820000,             false}, //D/IRAM level1, can be used as trace memory
+    { 0x40840000,           (APP_USABLE_DRAM_END-0x40840000),          SOC_MEMORY_TYPE_RAM, 0x40840000,             false}, //D/IRAM level2, can be used as trace memory
+    { APP_USABLE_DRAM_END,  (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END,    true},  //D/IRAM level3, can be used as trace memory (ROM reserved area)
+};
+
+const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
+
+
+extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
+extern int _rtc_reserved_start, _rtc_reserved_end;
+
+/**
+ * Reserved memory regions.
+ * These are removed from the soc_memory_regions array when heaps are created.
+ *
+ */
+
+// Static data region. DRAM used by data+bss and possibly rodata
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
+
+// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
+
+#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
+SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
+#endif
+
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data);
--- a/components/heap/port/memory_layout_utils.c
+++ b/components/heap/port/memory_layout_utils.c
@ -19,6 +19,8 @@
 #include "esp32c2/rom/rom_layout.h"
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/rom_layout.h"
+#elif CONFIG_IDF_TARGET_ESP32C61    //TODO: IDF-9526, refactor this
+#include "esp32c61/rom/rom_layout.h"
 #elif CONFIG_IDF_TARGET_ESP32C5
 #include "esp32c5/rom/rom_layout.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
--- a/components/newlib/newlib_init.c
+++ b/components/newlib/newlib_init.c
@ -34,6 +34,8 @@
 #include "esp32c2/rom/libc_stubs.h"
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/libc_stubs.h"
+#elif CONFIG_IDF_TARGET_ESP32C61    //TODO: IDF-9526, refactor this
+#include "esp32c61/rom/libc_stubs.h"
 #elif CONFIG_IDF_TARGET_ESP32C5
 #include "esp32c5/rom/libc_stubs.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
--- a/components/newlib/port/esp_time_impl.c
+++ b/components/newlib/port/esp_time_impl.c
@ -39,6 +39,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/rtc.h"
 #include "esp32c6/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C61    //TODO: IDF-9526, refactor this
+#include "esp32c61/rom/rtc.h"
+#include "esp32c61/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C5
 #include "esp32c5/rom/rtc.h"
 #include "esp32c5/rtc.h"
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@ -183,6 +183,10 @@ config SOC_DEEP_SLEEP_SUPPORTED
    bool
    default y

+config SOC_LP_PERIPH_SHARE_INTERRUPT
+    bool
+    default y
+
 config SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL
    int
    default 5
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@ -103,6 +103,7 @@
 #define SOC_RNG_SUPPORTED           1
 #define SOC_LIGHT_SLEEP_SUPPORTED   1
 #define SOC_DEEP_SLEEP_SUPPORTED    1
+#define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source

 #if SOC_CAPS_ECO_VER < 200
 #define SOC_DPORT_WORKAROUND                   1
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@ -127,6 +127,10 @@ config SOC_DEEP_SLEEP_SUPPORTED
    bool
    default y

+config SOC_LP_PERIPH_SHARE_INTERRUPT
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_26M
    bool
    default y
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@ -48,6 +48,7 @@
 #define SOC_RNG_SUPPORTED               1
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
+#define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_26M            1
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@ -179,6 +179,10 @@ config SOC_DEEP_SLEEP_SUPPORTED
    bool
    default y

+config SOC_LP_PERIPH_SHARE_INTERRUPT
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
    bool
    default y
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@ -64,6 +64,7 @@
 #define SOC_RNG_SUPPORTED               1
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
+#define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
@ -207,6 +207,10 @@ config SOC_DEEP_SLEEP_SUPPORTED
    bool
    default y

+config SOC_LP_PERIPH_SHARE_INTERRUPT
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
    bool
    default y
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@ -88,6 +88,7 @@
 #define SOC_RNG_SUPPORTED               1
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
+#define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
@ -247,6 +247,10 @@ config SOC_DEEP_SLEEP_SUPPORTED
    bool
    default y

+config SOC_LP_PERIPH_SHARE_INTERRUPT
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
    bool
    default y
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@ -78,6 +78,7 @@
 #define SOC_RNG_SUPPORTED               1
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
+#define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/components/spi_flash/cache_utils.c
+++ b/components/spi_flash/cache_utils.c
@ -35,6 +35,10 @@
 #include "esp32c6/rom/cache.h"
 #include "soc/extmem_reg.h"
 #include "soc/ext_mem_defs.h"
+#elif CONFIG_IDF_TARGET_ESP32C61    //TODO: IDF-9526, refactor this
+#include "esp32c61/rom/cache.h"
+#include "soc/cache_reg.h"
+#include "soc/ext_mem_defs.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/cache.h"
 #include "soc/extmem_reg.h"
@ -497,7 +501,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
    int i;
    bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
    uint32_t drom0_in_icache = 1;//always 1 in esp32s2
-#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C61 //TODO: [ESP32C61] IDF-9253
    drom0_in_icache = 0;
 #endif

--- a/components/spi_flash/flash_ops.c
+++ b/components/spi_flash/flash_ops.c
@ -41,6 +41,8 @@
 #include "esp32c2/rom/cache.h"
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32C61
+#include "esp32c61/rom/cache.h"
 #endif
 #include "esp_rom_spiflash.h"
 #include "esp_flash_partitions.h"
--- a/components/spi_flash/spi_flash_os_func_noos.c
+++ b/components/spi_flash/spi_flash_os_func_noos.c
@ -26,6 +26,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/ets_sys.h"
 #include "esp32c6/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32C61    //TODO: IDF-9526, refactor this
+#include "esp32c61/rom/ets_sys.h"
+#include "esp32c61/rom/cache.h"
 #elif CONFIG_IDF_TARGET_ESP32C5
 #include "esp32c5/rom/ets_sys.h"
 #include "esp32c5/rom/cache.h"
@ -46,7 +49,7 @@ typedef struct {
 } spi_noos_arg_t;

 static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 typedef struct {
    uint32_t icache_autoload;
 } spi_noos_arg_t;
@ -67,6 +70,9 @@ static IRAM_ATTR esp_err_t start(void *arg)
 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
    spi_noos_arg_t *spi_arg = arg;
    spi_arg->icache_autoload = Cache_Suspend_ICache();
+#elif CONFIG_IDF_TARGET_ESP32C61    // TODO: [ESP32C61] IDF-9253
+    spi_noos_arg_t *spi_arg = arg;
+    spi_arg->icache_autoload = Cache_Suspend_Cache();
 #elif CONFIG_IDF_TARGET_ESP32P4
    spi_noos_arg_t *spi_arg = arg;
    spi_arg->icache_autoload = Cache_Suspend_L2_Cache();
@ -89,6 +95,10 @@ static IRAM_ATTR esp_err_t end(void *arg)
    spi_noos_arg_t *spi_arg = arg;
    Cache_Invalidate_ICache_All();
    Cache_Resume_ICache(spi_arg->icache_autoload);
+#elif CONFIG_IDF_TARGET_ESP32C61
+    spi_noos_arg_t *spi_arg = arg;
+    Cache_Invalidate_All();
+    Cache_Resume_Cache(spi_arg->icache_autoload);
 #elif CONFIG_IDF_TARGET_ESP32P4
    spi_noos_arg_t *spi_arg = arg;
    Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
--- a/examples/get-started/.build-test-rules.yml
+++ b/examples/get-started/.build-test-rules.yml
@ -10,4 +10,4 @@ examples/get-started/blink:

 examples/get-started/hello_world:
  enable:
-    - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["linux", "esp32c5"]
+    - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["linux", "esp32c5", "esp32c61"]
--- a/examples/get-started/hello_world/README.md
+++ b/examples/get-started/hello_world/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ----- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | ----- |

 # Hello World Example

--- a/tools/ci/build_template_app.sh
+++ b/tools/ci/build_template_app.sh
@ -64,7 +64,7 @@ build_stage2() {
        --size-file size.json \
        --keep-going \
        --collect-size-info size_info.txt \
-        --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4
+        --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4 esp32c61
 }

 build_stage1() {
@ -78,7 +78,7 @@ build_stage1() {
        --build-log ${BUILD_LOG_CMAKE} \
        --size-file size.json \
        --collect-size-info size_info.txt \
-        --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4
+        --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4 esp32c61
 }

 # TODO: IDF-9197 remove the additional test for esp32c5 beta3