mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
test: Added LP core unit tests for LP SPI
This commit adds tests for LP SPI master and LP SPI slave devices.
This commit is contained in:
Sudeep Mohanty
parent
6e85d744a8
commit
70a0b4a1bf
@ -8,6 +8,10 @@ if(CONFIG_SOC_ULP_LP_UART_SUPPORTED)
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list(APPEND app_sources "test_lp_core_uart.c")
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endif()
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if(CONFIG_SOC_LP_SPI_SUPPORTED)
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list(APPEND app_sources "test_lp_core_spi.c")
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endif()
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set(lp_core_sources "lp_core/test_main.c")
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set(lp_core_sources_counter "lp_core/test_main_counter.c")
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@ -25,6 +29,11 @@ if(CONFIG_SOC_ULP_LP_UART_SUPPORTED)
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set(lp_core_sources_uart "lp_core/test_main_uart.c")
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endif()
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if(CONFIG_SOC_LP_SPI_SUPPORTED)
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set(lp_core_sources_spi_master "lp_core/test_main_spi_master.c")
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set(lp_core_sources_spi_slave "lp_core/test_main_spi_slave.c")
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endif()
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idf_component_register(SRCS ${app_sources}
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INCLUDE_DIRS "lp_core"
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REQUIRES ulp unity esp_timer test_utils
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@ -49,3 +58,8 @@ endif()
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if(CONFIG_SOC_ULP_LP_UART_SUPPORTED)
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ulp_embed_binary(lp_core_test_app_uart "${lp_core_sources_uart}" "${lp_core_exp_dep_srcs}")
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endif()
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if(CONFIG_SOC_LP_SPI_SUPPORTED)
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ulp_embed_binary(lp_core_test_app_spi_master "${lp_core_sources_spi_master}" "${lp_core_exp_dep_srcs}")
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ulp_embed_binary(lp_core_test_app_spi_slave "${lp_core_sources_spi_slave}" "${lp_core_exp_dep_srcs}")
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endif()
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@ -0,0 +1,38 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "ulp_lp_core_spi.h"
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#include "test_shared.h"
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volatile lp_core_test_commands_t spi_test_cmd = LP_CORE_NO_COMMAND;
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volatile uint8_t spi_master_tx_buf[100] = {0};
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volatile uint8_t spi_master_rx_buf[100] = {0};
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volatile uint32_t spi_tx_len = 0;
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int main(void)
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{
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/* Wait for the HP core to start the test */
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while (spi_test_cmd == LP_CORE_NO_COMMAND) {
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}
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/* Setup SPI transaction */
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lp_spi_transaction_t trans_desc = {
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.tx_length = spi_tx_len,
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.rx_length = spi_tx_len,
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.tx_buffer = (uint8_t *)spi_master_tx_buf,
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.rx_buffer = (uint8_t *)spi_master_rx_buf,
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};
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/* Transmit data */
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lp_core_lp_spi_master_transfer(&trans_desc, -1);
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/* Synchronize with the HP core running the test */
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spi_test_cmd = LP_CORE_NO_COMMAND;
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return 0;
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}
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@ -0,0 +1,32 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "ulp_lp_core_spi.h"
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#include "test_shared.h"
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volatile lp_core_test_command_reply_t spi_test_cmd_reply = LP_CORE_COMMAND_NOK;
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volatile uint8_t spi_slave_tx_buf[100] = {0};
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volatile uint8_t spi_slave_rx_buf[100] = {0};
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volatile uint32_t spi_rx_len = 0;
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int main(void)
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{
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/* Setup SPI transaction */
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lp_spi_transaction_t trans_desc = {
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.rx_length = spi_rx_len,
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.rx_buffer = (uint8_t *)spi_slave_rx_buf,
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.tx_buffer = NULL,
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};
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/* Receive data */
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lp_core_lp_spi_slave_transfer(&trans_desc, -1);
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/* Synchronize with the HP core running the test */
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spi_test_cmd_reply = LP_CORE_COMMAND_OK;
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return 0;
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}
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@ -24,6 +24,7 @@ typedef enum {
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LP_CORE_LP_UART_READ_TEST,
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LP_CORE_LP_UART_MULTI_BYTE_READ_TEST,
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LP_CORE_LP_UART_PRINT_TEST,
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LP_CORE_LP_SPI_WRITE_READ_TEST,
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LP_CORE_NO_COMMAND,
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} lp_core_test_commands_t;
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254
components/ulp/test_apps/lp_core/main/test_lp_core_spi.c
Normal file
254
components/ulp/test_apps/lp_core/main/test_lp_core_spi.c
Normal file
@ -0,0 +1,254 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "lp_core_test_app_spi_master.h"
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#include "lp_core_test_app_spi_slave.h"
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#include "ulp_lp_core.h"
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#include "lp_core_spi.h"
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#include "unity.h"
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#include "test_utils.h"
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#include "esp_log.h"
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#include "test_shared.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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extern const uint8_t lp_core_main_spi_master_bin_start[] asm("_binary_lp_core_test_app_spi_master_bin_start");
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extern const uint8_t lp_core_main_spi_master_bin_end[] asm("_binary_lp_core_test_app_spi_master_bin_end");
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extern const uint8_t lp_core_main_spi_slave_bin_start[] asm("_binary_lp_core_test_app_spi_slave_bin_start");
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extern const uint8_t lp_core_main_spi_slave_bin_end[] asm("_binary_lp_core_test_app_spi_slave_bin_end");
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static const char* TAG = "lp_core_spi_test";
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#define TEST_GPIO_PIN_MISO 6
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#define TEST_GPIO_PIN_MOSI 7
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#define TEST_GPIO_PIN_CLK 8
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#define TEST_GPIO_PIN_CS 4
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#define TEST_DATA_LEN_BYTES 42
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uint8_t expected_data[100] = {0};
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static void load_and_start_lp_core_firmware(ulp_lp_core_cfg_t* cfg, const uint8_t* firmware_start, const uint8_t* firmware_end)
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{
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TEST_ASSERT(ulp_lp_core_load_binary(firmware_start, (firmware_end - firmware_start)) == ESP_OK);
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TEST_ASSERT(ulp_lp_core_run(cfg) == ESP_OK);
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}
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static void setup_test_data(void)
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{
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uint8_t *tx_data = (uint8_t *)&ulp_spi_master_tx_buf;
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ulp_spi_tx_len = TEST_DATA_LEN_BYTES;
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/* Setup test data */
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for (int i = 0; i < ulp_spi_tx_len; i++) {
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tx_data[i] = (i + 1) % 256;
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expected_data[i] = tx_data[i];
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}
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}
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static void setup_expected_data(void)
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{
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ulp_spi_rx_len = TEST_DATA_LEN_BYTES;
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/* Setup expected data */
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for (int i = 0; i < TEST_DATA_LEN_BYTES; i++) {
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expected_data[i] = (i + 1) % 256;
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}
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}
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/* Base LP SPI bus settings */
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lp_spi_host_t host_id = 0;
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lp_spi_bus_config_t bus_config = {
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.miso_io_num = TEST_GPIO_PIN_MISO,
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.mosi_io_num = TEST_GPIO_PIN_MOSI,
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.sclk_io_num = TEST_GPIO_PIN_CLK,
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};
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/* Base LP SPI device settings */
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lp_spi_device_config_t device = {
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.cs_io_num = TEST_GPIO_PIN_CS,
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.spi_mode = 0,
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.clock_speed_hz = 10 * 1000, // 10 MHz
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.duty_cycle = 128, // 50% duty cycle
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};
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/* Base LP SPI slave device settings */
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lp_spi_slave_config_t slv_device = {
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.cs_io_num = TEST_GPIO_PIN_CS,
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.spi_mode = 0,
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};
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static void lp_spi_master_init(int spi_flags, bool setup_master_loop_back)
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{
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/* Initialize LP SPI bus */
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/* Setup loop back for tests which do not use an LP SPI slave for looping back the data. */
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bus_config.miso_io_num = setup_master_loop_back ? TEST_GPIO_PIN_MOSI : TEST_GPIO_PIN_MISO;
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TEST_ASSERT(lp_core_lp_spi_bus_initialize(host_id, &bus_config) == ESP_OK);
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/* Add LP SPI device */
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device.flags = spi_flags;
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TEST_ASSERT(lp_core_lp_spi_bus_add_device(host_id, &device) == ESP_OK);
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}
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static void lp_spi_slave_init(int spi_flags)
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{
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/* Initialize LP SPI bus */
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TEST_ASSERT(lp_core_lp_spi_bus_initialize(host_id, &bus_config) == ESP_OK);
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/* Add LP SPI slave device */
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if (spi_flags != 0) {
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slv_device.flags = spi_flags;
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}
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TEST_ASSERT(lp_core_lp_spi_slave_initialize(host_id, &slv_device) == ESP_OK);
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}
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static void lp_spi_master_execute_test(bool wait_for_slave_ready)
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{
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/* Load and run the LP core firmware */
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ulp_lp_core_cfg_t lp_cfg = {
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.wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU,
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};
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load_and_start_lp_core_firmware(&lp_cfg, lp_core_main_spi_master_bin_start, lp_core_main_spi_master_bin_end);
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if (wait_for_slave_ready) {
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/* Wait for the HP SPI device to be initialized */
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unity_wait_for_signal("LP SPI slave ready");
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}
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/* Setup test data */
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setup_test_data();
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/* Start the test */
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ulp_spi_test_cmd = LP_CORE_LP_SPI_WRITE_READ_TEST;
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while (ulp_spi_test_cmd != LP_CORE_NO_COMMAND) {
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/* Wait for the test to complete */
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vTaskDelay(1);
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}
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/* Verify the received data if we expect the data to be looped back from the LP SPI slave */
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uint8_t *rx_data = (uint8_t *)&ulp_spi_master_rx_buf;
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for (int i = 0; i < TEST_DATA_LEN_BYTES; i++) {
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ESP_LOGI(TAG, "LP SPI master received data: 0x%02x", rx_data[i]);
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}
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TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_data, rx_data, ulp_spi_tx_len);
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}
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static void lp_spi_slave_execute_test(void)
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{
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/* Load and run the LP core firmware */
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ulp_lp_core_cfg_t lp_cfg = {
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.wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU,
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};
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load_and_start_lp_core_firmware(&lp_cfg, lp_core_main_spi_slave_bin_start, lp_core_main_spi_slave_bin_end);
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/* Setup expected test data */
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setup_expected_data();
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/* Send signal to LP SPI master */
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unity_send_signal("LP SPI slave ready");
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/* Wait for the test to complete */
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while (ulp_spi_test_cmd_reply != LP_CORE_COMMAND_OK) {
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vTaskDelay(1);
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}
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/* Verify the received data */
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uint8_t *rx_data = (uint8_t *)&ulp_spi_slave_rx_buf;
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for (int i = 0; i < TEST_DATA_LEN_BYTES; i++) {
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ESP_LOGI(TAG, "LP SPI slave received data: 0x%02x", rx_data[i]);
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}
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TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_data, rx_data, TEST_DATA_LEN_BYTES);
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}
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void test_lp_spi_master(void)
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{
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/* Initialize LP SPI in master mode */
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lp_spi_master_init(0, false);
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/* Start the LP SPI master test */
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lp_spi_master_execute_test(true);
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}
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void test_lp_spi_slave(void)
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{
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/* Initialize LP SPI in slave mode */
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lp_spi_slave_init(0);
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/* Start the LP SPI slave test */
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lp_spi_slave_execute_test();
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}
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void test_lp_spi_master_3wire(void)
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{
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/* Initialize LP SPI in master mode */
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int spi_flags = LP_SPI_DEVICE_3WIRE;
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lp_spi_master_init(spi_flags, false);
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/* Start the LP SPI master test */
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lp_spi_master_execute_test(true);
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}
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void test_lp_spi_slave_3wire(void)
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{
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/* Initialize LP SPI in slave mode */
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int spi_flags = LP_SPI_DEVICE_3WIRE;
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lp_spi_slave_init(spi_flags);
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/* Start the LP SPI slave test */
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lp_spi_slave_execute_test();
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}
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void test_lp_spi_master_lsbfirst(void)
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{
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/* Initialize LP SPI in master mode */
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int spi_flags = LP_SPI_DEVICE_BIT_LSBFIRST;
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lp_spi_master_init(spi_flags, false);
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/* Start the LP SPI master test */
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lp_spi_master_execute_test(true);
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}
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void test_lp_spi_slave_lsbfirst(void)
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{
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/* Initialize LP SPI in slave mode */
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int spi_flags = LP_SPI_DEVICE_BIT_LSBFIRST;
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lp_spi_slave_init(spi_flags);
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/* Start the LP SPI slave test */
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lp_spi_slave_execute_test();
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}
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/* Test LP-SPI master loopback */
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TEST_CASE("LP-Core LP-SPI master loopback test", "[lp_core]")
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{
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/* Initialize LP SPI in master mode */
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lp_spi_master_init(0, true);
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/* Start the LP SPI master test */
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lp_spi_master_execute_test(false);
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}
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/* Test LP-SPI master loopback with active low CS line */
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TEST_CASE("LP-Core LP-SPI master loopback test with active high CS line", "[lp_core]")
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{
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/* Initialize LP SPI in master mode */
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int spi_flags = LP_SPI_DEVICE_CS_ACTIVE_HIGH;
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lp_spi_master_init(spi_flags, true);
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/* Start the LP SPI master test */
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lp_spi_master_execute_test(false);
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}
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/* Test LP-SPI master and LP-SPI slave communication */
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TEST_CASE_MULTIPLE_DEVICES("LP-Core LP-SPI master and LP-SPI slave read write test", "[lp_core_spi][test_env=generic_multi_device][timeout=150]", test_lp_spi_master, test_lp_spi_slave);
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/* Test LP-SPI master in 3-Wire SPI mode */
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TEST_CASE_MULTIPLE_DEVICES("LP-Core LP-SPI master and LP-SPI slave in 3-Wire SPI mode", "[lp_core_spi][test_env=generic_multi_device][timeout=150]", test_lp_spi_master_3wire, test_lp_spi_slave_3wire);
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/* Test LP-SPI master and LP-SPI slave in LSB first mode */
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TEST_CASE_MULTIPLE_DEVICES("LP-Core LP-SPI master and LP-SPI in LSB first SPI mode", "[lp_core_spi][test_env=generic_multi_device][timeout=150]", test_lp_spi_master_lsbfirst, test_lp_spi_slave_lsbfirst);
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