From 3da77e2d1b1584815750e0b636f57b7a6a3fbd13 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Fri, 22 Mar 2024 11:24:07 +0800 Subject: [PATCH] fix(uart): correct C2 UART_BITRATE_MAX value --- components/soc/esp32c2/include/soc/Kconfig.soc_caps.in | 2 +- components/soc/esp32c2/include/soc/clk_tree_defs.h | 5 ++--- components/soc/esp32c2/include/soc/soc_caps.h | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 2ec638f74e..5b277eaac7 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -645,7 +645,7 @@ config SOC_UART_FIFO_LEN config SOC_UART_BITRATE_MAX int - default 5000000 + default 2500000 config SOC_UART_SUPPORT_WAKEUP_INT bool diff --git a/components/soc/esp32c2/include/soc/clk_tree_defs.h b/components/soc/esp32c2/include/soc/clk_tree_defs.h index 10e1e22cf7..1d7a2cfe5f 100644 --- a/components/soc/esp32c2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c2/include/soc/clk_tree_defs.h @@ -202,9 +202,6 @@ typedef enum { UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F40M, /*!< UART source clock default choice is PLL_F40M */ } soc_periph_uart_clk_src_legacy_t; -/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// - - /////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// /** @@ -221,6 +218,8 @@ typedef enum { SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ } soc_periph_spi_clk_src_t; +/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// + /** * @brief Array initializer for all supported clock sources of I2C */ diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 05c60b0899..eda25b6638 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -290,7 +290,7 @@ #define SOC_UART_NUM (2) #define SOC_UART_HP_NUM (2) #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ -#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ +#define SOC_UART_BITRATE_MAX (2500000) /*!< Max bit rate supported by UART */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ #define SOC_UART_SUPPORT_PLL_F40M_CLK (1) /*!< Support APB as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */