diff --git a/components/esp_hw_support/port/esp32c5/Kconfig.rtc b/components/esp_hw_support/port/esp32c5/Kconfig.rtc index b02d6e6cc0..ce8a3ebe90 100644 --- a/components/esp_hw_support/port/esp32c5/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32c5/Kconfig.rtc @@ -12,15 +12,13 @@ choice RTC_CLK_SRC config RTC_CLK_SRC_EXT_OSC bool "External 32 kHz oscillator at 32K_XP pin" select ESP_SYSTEM_RTC_EXT_OSC - config RTC_CLK_SRC_INT_RC32K - bool "Internal 32 kHz RC oscillator" endchoice config RTC_CLK_CAL_CYCLES int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC default 1024 if RTC_CLK_SRC_INT_RC - range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K + range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC range 0 32766 if RTC_CLK_SRC_INT_RC help When the startup code initializes RTC_SLOW_CLK, it can perform diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index 97da0750e8..92a2c4f5c2 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -10,7 +10,6 @@ #include #include "soc/soc.h" #include "soc/clk_tree_defs.h" -#include "sdkconfig.h" #ifdef __cplusplus extern "C" { @@ -60,14 +59,12 @@ extern "C" { #define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 #define SOC_DELAY_RC_FAST_ENABLE 50 #define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 -#define SOC_DELAY_RC32K_ENABLE 300 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 #define RTC_CNTL_SCK_DCAP_DEFAULT 128 -#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 /* Various delays to be programmed into power control state machines */ #define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) @@ -124,7 +121,6 @@ typedef struct rtc_cpu_freq_config_s { */ typedef enum { RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK - RTC_CAL_RC32K = 0, //!< Internal 32kHz RC oscillator, as one type of 32k clock RTC_CAL_32K_XTAL = 1, //!< External 32kHz XTAL, as one type of 32k clock RTC_CAL_32K_OSC_SLOW = 2, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock RTC_CAL_RC_SLOW = 3, //!< Internal 150kHz RC oscillator @@ -144,7 +140,6 @@ typedef struct { uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency) uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency) uint32_t clk_8m_dfreq : 10; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) - uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; /** @@ -159,7 +154,6 @@ typedef struct { .clk_8m_clk_div = 0, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ - .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ } /** @@ -205,12 +199,6 @@ bool rtc_clk_32k_enabled(void); */ void rtc_clk_32k_bootstrap(uint32_t cycle); -/** - * @brief Enable or disable 32 kHz internal rc oscillator - * @param en true to enable, false to disable - */ -void rtc_clk_rc32k_enable(bool enable); - /** * @brief Enable or disable 8 MHz internal oscillator * @@ -241,7 +229,6 @@ soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); * * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000 * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 - * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768 * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768 * * rtc_clk_cal function can be used to get more precise value by comparing diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index a02bdb9acc..34f4dd7cf5 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -73,16 +73,6 @@ bool rtc_clk_32k_enabled(void) return clk_ll_xtal32k_is_enabled(); } -void rtc_clk_rc32k_enable(bool enable) -{ - if (enable) { - clk_ll_rc32k_enable(); - esp_rom_delay_us(SOC_DELAY_RC32K_ENABLE); - } else { - clk_ll_rc32k_disable(); - } -} - void rtc_clk_8m_enable(bool clk_8m_en) { if (clk_8m_en) { @@ -114,7 +104,6 @@ uint32_t rtc_clk_slow_freq_get_hz(void) switch (rtc_clk_slow_src_get()) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX; case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX; default: return 0; } diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c index b659bd2ba5..8d5c33800b 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c @@ -65,18 +65,16 @@ void rtc_clk_init(rtc_clk_config_t cfg) rtc_clk_modem_clock_domain_active_state_icg_map_preinit(); - /* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks. + /* Set tuning parameters for RC_FAST and RC_SLOW clocks. * Note: this doesn't attempt to set the clocks to precise frequencies. * Instead, we calibrate these clocks against XTAL frequency later, when necessary. * - SCK_DCAP value controls tuning of RC_SLOW clock. * The higher the value of DCAP is, the lower is the frequency. * - CK8M_DFREQ value controls tuning of RC_FAST clock. * CLK_8M_DFREQ constant gives the best temperature characteristics. - * - RC32K_DFREQ value controls tuning of RC32K clock. */ REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap); - REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); @@ -113,8 +111,6 @@ void rtc_clk_init(rtc_clk_config_t cfg) rtc_clk_32k_enable(true); } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { rtc_clk_32k_enable_external(); - } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - rtc_clk_rc32k_enable(true); } rtc_clk_8m_enable(need_rc_fast_en); rtc_clk_fast_src_set(cfg.fast_clk_src); diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c index 1c4694a479..97e5299f4e 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_time.c +++ b/components/esp_hw_support/port/esp32c5/rtc_time.c @@ -24,7 +24,7 @@ __attribute__((unused)) static const char *TAG = "rtc_time"; * RTC_SLOW_CLK cycles. */ -#define CLK_CAL_TIMEOUT_THRES(cal_clk, cycles) ((cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10)) +#define CLK_CAL_TIMEOUT_THRES(cal_clk, cycles) ((cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10)) static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { @@ -36,8 +36,6 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc cal_clk = RTC_CAL_RC_SLOW; } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - cal_clk = RTC_CAL_RC32K; } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { cal_clk = RTC_CAL_32K_OSC_SLOW; } @@ -67,17 +65,6 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc } } - bool rc32k_enabled = clk_ll_rc32k_is_enabled(); - bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled(); - if (cal_clk == RTC_CAL_RC32K) { - if (!rc32k_enabled) { - rtc_clk_rc32k_enable(true); - } - if (!dig_rc32k_enabled) { - clk_ll_rc32k_digi_enable(); - } - } - /* There may be another calibration process already running during we call this function, * so we should wait the last process is done. */ @@ -103,7 +90,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc /* Set timeout reg and expect time delay*/ REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk, slowclk_cycles)); uint32_t expected_freq; - if (cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) { + if (cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) { expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; } else if (cal_clk == RTC_CAL_RC_FAST) { expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; @@ -150,15 +137,6 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc } } - if (cal_clk == RTC_CAL_RC32K) { - if (!dig_rc32k_enabled) { - clk_ll_rc32k_digi_disable(); - } - if (!rc32k_enabled) { - rtc_clk_rc32k_enable(false); - } - } - return cal_val; } diff --git a/components/esp_hw_support/port/esp32c61/Kconfig.rtc b/components/esp_hw_support/port/esp32c61/Kconfig.rtc index b02d6e6cc0..ce8a3ebe90 100644 --- a/components/esp_hw_support/port/esp32c61/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32c61/Kconfig.rtc @@ -12,15 +12,13 @@ choice RTC_CLK_SRC config RTC_CLK_SRC_EXT_OSC bool "External 32 kHz oscillator at 32K_XP pin" select ESP_SYSTEM_RTC_EXT_OSC - config RTC_CLK_SRC_INT_RC32K - bool "Internal 32 kHz RC oscillator" endchoice config RTC_CLK_CAL_CYCLES int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC default 1024 if RTC_CLK_SRC_INT_RC - range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K + range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC range 0 32766 if RTC_CLK_SRC_INT_RC help When the startup code initializes RTC_SLOW_CLK, it can perform diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h index 91cebda696..12c15bc101 100644 --- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h @@ -59,14 +59,12 @@ extern "C" { #define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 #define SOC_DELAY_RC_FAST_ENABLE 50 #define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 -#define SOC_DELAY_RC32K_ENABLE 300 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 #define RTC_CNTL_SCK_DCAP_DEFAULT 128 -#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 /* Various delays to be programmed into power control state machines */ #define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) @@ -123,7 +121,6 @@ typedef struct rtc_cpu_freq_config_s { */ typedef enum { RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK - RTC_CAL_RC32K = 0, //!< Internal 32kHz RC oscillator, as one type of 32k clock RTC_CAL_32K_XTAL = 1, //!< External 32kHz XTAL, as one type of 32k clock RTC_CAL_32K_OSC_SLOW = 2, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock RTC_CAL_RC_SLOW = 3, //!< Internal 150kHz RC oscillator @@ -143,7 +140,6 @@ typedef struct { uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency) uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency) uint32_t clk_8m_dfreq : 10; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) - uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; /** @@ -158,7 +154,6 @@ typedef struct { .clk_8m_clk_div = 0, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ - .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ } /** @@ -204,12 +199,6 @@ bool rtc_clk_32k_enabled(void); */ void rtc_clk_32k_bootstrap(uint32_t cycle); -/** - * @brief Enable or disable 32 kHz internal rc oscillator - * @param en true to enable, false to disable - */ -void rtc_clk_rc32k_enable(bool enable); - /** * @brief Enable or disable 8 MHz internal oscillator * @@ -240,7 +229,6 @@ soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); * * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000 * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 - * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768 * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768 * * rtc_clk_cal function can be used to get more precise value by comparing diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk.c b/components/esp_hw_support/port/esp32c61/rtc_clk.c index c3cd694dd9..76bfb4eb40 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c @@ -73,16 +73,6 @@ bool rtc_clk_32k_enabled(void) return clk_ll_xtal32k_is_enabled(); } -void rtc_clk_rc32k_enable(bool enable) -{ - if (enable) { - clk_ll_rc32k_enable(); - esp_rom_delay_us(SOC_DELAY_RC32K_ENABLE); - } else { - clk_ll_rc32k_disable(); - } -} - void rtc_clk_8m_enable(bool clk_8m_en) { if (clk_8m_en) { @@ -114,7 +104,6 @@ uint32_t rtc_clk_slow_freq_get_hz(void) switch (rtc_clk_slow_src_get()) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX; case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX; default: return 0; } diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk_init.c b/components/esp_hw_support/port/esp32c61/rtc_clk_init.c index 8403fc90a4..2a59de7a3a 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk_init.c @@ -65,20 +65,18 @@ void rtc_clk_init(rtc_clk_config_t cfg) { rtc_cpu_freq_config_t old_config, new_config; - rtc_clk_modem_clock_domain_active_state_icg_map_preinit(); // TODO: comment? + rtc_clk_modem_clock_domain_active_state_icg_map_preinit(); - /* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks. + /* Set tuning parameters for RC_FAST and RC_SLOW clocks. * Note: this doesn't attempt to set the clocks to precise frequencies. * Instead, we calibrate these clocks against XTAL frequency later, when necessary. * - SCK_DCAP value controls tuning of RC_SLOW clock. * The higher the value of DCAP is, the lower is the frequency. * - CK8M_DFREQ value controls tuning of RC_FAST clock. * CLK_8M_DFREQ constant gives the best temperature characteristics. - * - RC32K_DFREQ value controls tuning of RC32K clock. */ REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap); - REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); @@ -114,8 +112,6 @@ void rtc_clk_init(rtc_clk_config_t cfg) rtc_clk_32k_enable(true); } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { rtc_clk_32k_enable_external(); - } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - rtc_clk_rc32k_enable(true); } rtc_clk_8m_enable(need_rc_fast_en); rtc_clk_fast_src_set(cfg.fast_clk_src); diff --git a/components/esp_hw_support/port/esp32c61/rtc_time.c b/components/esp_hw_support/port/esp32c61/rtc_time.c index b1278dc5e9..37c3637fb6 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_time.c +++ b/components/esp_hw_support/port/esp32c61/rtc_time.c @@ -23,7 +23,7 @@ __attribute__((unused)) static const char *TAG = "rtc_time"; * RTC_SLOW_CLK cycles. */ -#define CLK_CAL_TIMEOUT_THRES(cal_clk, cycles) ((cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10)) +#define CLK_CAL_TIMEOUT_THRES(cal_clk, cycles) ((cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10)) static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { @@ -35,8 +35,6 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc cal_clk = RTC_CAL_RC_SLOW; } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - cal_clk = RTC_CAL_RC32K; } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { cal_clk = RTC_CAL_32K_OSC_SLOW; } @@ -66,17 +64,6 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc } } - bool rc32k_enabled = clk_ll_rc32k_is_enabled(); - bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled(); - if (cal_clk == RTC_CAL_RC32K) { - if (!rc32k_enabled) { - rtc_clk_rc32k_enable(true); - } - if (!dig_rc32k_enabled) { - clk_ll_rc32k_digi_enable(); - } - } - /* There may be another calibration process already running during we call this function, * so we should wait the last process is done. */ @@ -102,7 +89,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc /* Set timeout reg and expect time delay*/ REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk, slowclk_cycles)); uint32_t expected_freq; - if (cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) { + if (cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) { expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; } else if (cal_clk == RTC_CAL_RC_FAST) { expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; @@ -149,15 +136,6 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc } } - if (cal_clk == RTC_CAL_RC32K) { - if (!dig_rc32k_enabled) { - clk_ll_rc32k_digi_disable(); - } - if (!rc32k_enabled) { - rtc_clk_rc32k_enable(false); - } - } - return cal_val; } diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 674b92920e..c8f0bd1bf8 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -78,8 +78,6 @@ __attribute__((weak)) void esp_clk_init(void) select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K); #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC) select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW); -#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K) - select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC32K); #else select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW); #endif @@ -155,8 +153,6 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; } } - } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - rtc_clk_rc32k_enable(true); } rtc_clk_slow_src_set(rtc_slow_clk_src); @@ -200,9 +196,8 @@ __attribute__((weak)) void esp_perip_clk_init(void) soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)( (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K - : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K - : MODEM_CLOCK_LPCLK_SRC_RC32K); + : MODEM_CLOCK_LPCLK_SRC_RC_SLOW); modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); #endif diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c index eb6e6b8f2c..035cc1c87f 100644 --- a/components/esp_system/port/soc/esp32c61/clk.c +++ b/components/esp_system/port/soc/esp32c61/clk.c @@ -73,8 +73,6 @@ __attribute__((weak)) void esp_clk_init(void) select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K); #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC) select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW); -#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K) - select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC32K); #else select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW); #endif @@ -147,8 +145,6 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; } } - } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - rtc_clk_rc32k_enable(true); } rtc_clk_slow_src_set(rtc_slow_clk_src); @@ -191,7 +187,6 @@ __attribute__((weak)) void esp_perip_clk_init(void) modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)( (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K - : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K : SOC_RTC_SLOW_CLK_SRC_RC_SLOW); modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); diff --git a/components/hal/esp32c5/clk_tree_hal.c b/components/hal/esp32c5/clk_tree_hal.c index c79d0d8276..15851b6c79 100644 --- a/components/hal/esp32c5/clk_tree_hal.c +++ b/components/hal/esp32c5/clk_tree_hal.c @@ -57,8 +57,6 @@ uint32_t clk_hal_lp_slow_get_freq_hz(void) return SOC_CLK_XTAL32K_FREQ_APPROX; case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_RC32K: - return SOC_CLK_RC32K_FREQ_APPROX; default: // Unknown RTC_SLOW_CLK mux input HAL_ASSERT(false); diff --git a/components/hal/esp32c5/include/hal/clk_tree_ll.h b/components/hal/esp32c5/include/hal/clk_tree_ll.h index 094850e496..ca391faddd 100644 --- a/components/hal/esp32c5/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c5/include/hal/clk_tree_ll.h @@ -129,34 +129,6 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1; } -/** - * @brief Enable the internal oscillator output for RC32K_CLK - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) -{ - // Enable rc32k xpd status - SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); -} - -/** - * @brief Disable the internal oscillator output for RC32K_CLK - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) -{ - // Disable rc32k xpd status - CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); -} - -/** - * @brief Get the state of the internal oscillator for RC32K_CLK - * - * @return True if the oscillator is enabled - */ -static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void) -{ - return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1; -} - /** * @brief Enable the internal oscillator output for RC_FAST_CLK */ @@ -235,32 +207,6 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled return LP_CLKRST.clk_to_hp.icg_hp_xtal32k; } -/** - * @brief Enable the digital RC32K_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) -{ - LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1; -} - -/** - * @brief Disable the digital RC32K_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) -{ - LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0; -} - -/** - * @brief Get the state of the digital RC32K_CLK - * - * @return True if the digital RC32K_CLK is enabled - */ -static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) -{ - return LP_CLKRST.clk_to_hp.icg_hp_osc32k; -} - /** * @brief Get XTAL_CLK frequency * @@ -488,9 +434,6 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rt case SOC_RTC_SLOW_CLK_SRC_XTAL32K: LP_CLKRST.lp_clk_conf.slow_clk_sel = 1; break; - case SOC_RTC_SLOW_CLK_SRC_RC32K: - LP_CLKRST.lp_clk_conf.slow_clk_sel = 2; - break; case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: LP_CLKRST.lp_clk_conf.slow_clk_sel = 3; break; @@ -513,8 +456,6 @@ static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_s return SOC_RTC_SLOW_CLK_SRC_RC_SLOW; case 1: return SOC_RTC_SLOW_CLK_SRC_XTAL32K; - case 2: - return SOC_RTC_SLOW_CLK_SRC_RC32K; case 3: return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW; default: diff --git a/components/hal/esp32c61/clk_tree_hal.c b/components/hal/esp32c61/clk_tree_hal.c index ad7f715260..9c8792081f 100644 --- a/components/hal/esp32c61/clk_tree_hal.c +++ b/components/hal/esp32c61/clk_tree_hal.c @@ -53,8 +53,6 @@ uint32_t clk_hal_lp_slow_get_freq_hz(void) return SOC_CLK_XTAL32K_FREQ_APPROX; case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_RC32K: - return SOC_CLK_RC32K_FREQ_APPROX; default: // Unknown RTC_SLOW_CLK mux input HAL_ASSERT(false); diff --git a/components/hal/esp32c61/include/hal/clk_tree_ll.h b/components/hal/esp32c61/include/hal/clk_tree_ll.h index 8eadfa9fbe..69af5794c8 100644 --- a/components/hal/esp32c61/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c61/include/hal/clk_tree_ll.h @@ -127,34 +127,6 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1; } -/** - * @brief Enable the internal oscillator output for RC32K_CLK - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) -{ - // Enable rc32k xpd status - SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); -} - -/** - * @brief Disable the internal oscillator output for RC32K_CLK - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) -{ - // Disable rc32k xpd status - CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); -} - -/** - * @brief Get the state of the internal oscillator for RC32K_CLK - * - * @return True if the oscillator is enabled - */ -static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void) -{ - return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1; -} - /** * @brief Enable the internal oscillator output for RC_FAST_CLK */ @@ -233,32 +205,6 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled return LP_CLKRST.clk_to_hp.icg_hp_xtal32k; } -/** - * @brief Enable the digital RC32K_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) -{ - LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1; -} - -/** - * @brief Disable the digital RC32K_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) -{ - LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0; -} - -/** - * @brief Get the state of the digital RC32K_CLK - * - * @return True if the digital RC32K_CLK is enabled - */ -static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) -{ - return LP_CLKRST.clk_to_hp.icg_hp_osc32k; -} - /** * @brief Get XTAL_CLK frequency * @@ -462,9 +408,6 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rt case SOC_RTC_SLOW_CLK_SRC_XTAL32K: LP_CLKRST.lp_clk_conf.slow_clk_sel = 1; break; - case SOC_RTC_SLOW_CLK_SRC_RC32K: - LP_CLKRST.lp_clk_conf.slow_clk_sel = 2; - break; case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: LP_CLKRST.lp_clk_conf.slow_clk_sel = 3; break; @@ -487,8 +430,6 @@ static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_s return SOC_RTC_SLOW_CLK_SRC_RC_SLOW; case 1: return SOC_RTC_SLOW_CLK_SRC_XTAL32K; - case 2: - return SOC_RTC_SLOW_CLK_SRC_RC32K; case 3: return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW; default: diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index f6d62e0f77..be113909e4 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1127,10 +1127,6 @@ config SOC_PM_SUPPORT_XTAL32K_PD bool default y -config SOC_PM_SUPPORT_RC32K_PD - bool - default y - config SOC_PM_SUPPORT_RC_FAST_PD bool default y @@ -1167,10 +1163,6 @@ config SOC_CLK_OSC_SLOW_SUPPORTED bool default y -config SOC_CLK_RC32K_SUPPORTED - bool - default y - config SOC_CLK_LP_FAST_SUPPORT_XTAL bool default y diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 6c50e48480..944dd514c3 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -26,18 +26,14 @@ extern "C" { * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock * can be computed in runtime through calibration. * - * 4) Internal 32kHz RC Oscillator: RC32K - * - * The exact frequency of this clock can be computed in runtime through calibration. - * - * 5) External 32kHz Crystal Clock (optional): XTAL32K + * 4) External 32kHz Crystal Clock (optional): XTAL32K * * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N * pins. * * XTAL32K_CLK can also be calibrated to get its exact frequency. * - * 6) External Slow Clock (optional): OSC_SLOW + * 5) External Slow Clock (optional): OSC_SLOW * * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the * RTC_SLOW_CLK. @@ -48,7 +44,6 @@ extern "C" { /* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ #define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ #define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ -#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ #define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ #define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ @@ -64,7 +59,6 @@ typedef enum { SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ SOC_ROOT_CLK_EXT_XTAL, /*!< External 48MHz crystal */ SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ - SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ } soc_root_clk_t; @@ -87,7 +81,6 @@ typedef enum { typedef enum { SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ } soc_rtc_slow_clk_src_t; @@ -128,7 +121,7 @@ typedef enum { SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ // For RTC domain SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ - SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ // For digital domain: peripherals, WIFI, BLE SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 05615e3fec..e520395f4a 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -535,7 +535,7 @@ // #define SOC_PM_SUPPORT_CPU_PD (1) #define SOC_PM_SUPPORT_MODEM_PD (1) #define SOC_PM_SUPPORT_XTAL32K_PD (1) -#define SOC_PM_SUPPORT_RC32K_PD (1) +// #define SOC_PM_SUPPORT_RC32K_PD (1) #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) #define SOC_PM_SUPPORT_TOP_PD (1) @@ -561,7 +561,6 @@ #define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */ #define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */ -#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */ #define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */ diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index bca2cc95ad..3553ab252a 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -567,10 +567,6 @@ config SOC_PM_SUPPORT_XTAL32K_PD bool default y -config SOC_PM_SUPPORT_RC32K_PD - bool - default y - config SOC_PM_SUPPORT_RC_FAST_PD bool default y @@ -627,10 +623,6 @@ config SOC_CLK_OSC_SLOW_SUPPORTED bool default y -config SOC_CLK_RC32K_SUPPORTED - bool - default y - config SOC_CLK_LP_FAST_SUPPORT_XTAL bool default y diff --git a/components/soc/esp32c61/include/soc/clk_tree_defs.h b/components/soc/esp32c61/include/soc/clk_tree_defs.h index 4c1f135c94..ab58324479 100644 --- a/components/soc/esp32c61/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c61/include/soc/clk_tree_defs.h @@ -24,18 +24,14 @@ extern "C" { * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock * can be computed in runtime through calibration. * - * 4) Internal 32kHz RC Oscillator: RC32K - * - * The exact frequency of this clock can be computed in runtime through calibration. - * - * 5) External 32kHz Crystal Clock (optional): XTAL32K + * 4) External 32kHz Crystal Clock (optional): XTAL32K * * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N * pins. * * XTAL32K_CLK can also be calibrated to get its exact frequency. * - * 6) External Slow Clock (optional): OSC_SLOW + * 5) External Slow Clock (optional): OSC_SLOW * * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the * RTC_SLOW_CLK. @@ -46,7 +42,6 @@ extern "C" { /* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ #define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ #define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ -#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ #define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ #define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ @@ -62,7 +57,6 @@ typedef enum { SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ - SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ } soc_root_clk_t; @@ -84,7 +78,6 @@ typedef enum { typedef enum { SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ } soc_rtc_slow_clk_src_t; @@ -124,7 +117,7 @@ typedef enum { SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ // For RTC domain SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ - SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ // For digital domain: peripherals, WIFI, BLE SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ @@ -377,7 +370,6 @@ typedef enum { CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */ CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */ CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */ - CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */ CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ CLKOUT_SIG_INVALID = 0xFF, } soc_clkout_sig_id_t; diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 541ee325f3..a7964e4151 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -458,7 +458,7 @@ // \#define SOC_PM_SUPPORT_CPU_PD (1) #define SOC_PM_SUPPORT_MODEM_PD (1) #define SOC_PM_SUPPORT_XTAL32K_PD (1) -#define SOC_PM_SUPPORT_RC32K_PD (1) +// \#define SOC_PM_SUPPORT_RC32K_PD (1) #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) // \#define SOC_PM_SUPPORT_TOP_PD (1) @@ -485,7 +485,6 @@ #define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */ #define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */ -#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */ #define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */