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efuse: Adds ERR_RST_ENABLE efuse for C3 and S3

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Closes https://github.com/espressif/esp-idf/issues/8357
This commit is contained in:
KonstantinKondrashov 2022-02-28 21:16:24 +08:00
parent 6e0308d352
commit 6d11c57b2a
11 changed files with 93 additions and 59 deletions
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11
components/efuse/esp32c3/esp_efuse_table.c
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@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 720eb12a076091cb1a236c15d9fa3308
// md5_digest_table c758e0f0a30842910db35d4b106601e4
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -311,6 +311,10 @@ static const esp_efuse_desc_t SECURE_VERSION[] = {
{EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
};
static const esp_efuse_desc_t ERR_RST_ENABLE[] = {
{EFUSE_BLK0, 159, 1}, // Use BLOCK0 to check error record registers,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
@ -858,6 +862,11 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[] = {
&ERR_RST_ENABLE[0], // Use BLOCK0 to check error record registers
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]

1
components/efuse/esp32c3/esp_efuse_table.csv
View File

@ -95,6 +95,7 @@
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, Use BLOCK0 to check error record registers, 0 - without check.
# EFUSE_RD_REPEAT_DATA4_REG #

Can't render this file because it contains an unexpected character in line 7 and column 87.

3
components/efuse/esp32c3/include/esp_efuse_table.h
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@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 720eb12a076091cb1a236c15d9fa3308
// md5_digest_table c758e0f0a30842910db35d4b106601e4
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -90,6 +90,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];

13
components/efuse/esp32s3/esp_efuse_table.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 9444b887379d924049af42806ca71d45
// md5_digest_table 9ad4ee9f762f38e72cc539962367b6a2
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -351,6 +351,10 @@ static const esp_efuse_desc_t SECURE_VERSION[] = {
{EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
};
static const esp_efuse_desc_t ERR_RST_ENABLE[] = {
{EFUSE_BLK0, 159, 1}, // Use BLOCK0 to check error record registers,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
@ -956,6 +960,11 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[] = {
&ERR_RST_ENABLE[0], // Use BLOCK0 to check error record registers
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]

1
components/efuse/esp32s3/esp_efuse_table.csv
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@ -104,6 +104,7 @@
FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enables ECC in Flash boot mode
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, Use BLOCK0 to check error record registers, 0 - without check.
# EFUSE_RD_REPEAT_DATA4_REG #

Can't render this file because it contains an unexpected character in line 8 and column 53.

5
components/efuse/esp32s3/include/esp_efuse_table.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 9444b887379d924049af42806ca71d45
// md5_digest_table 9ad4ee9f762f38e72cc539962367b6a2
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -100,6 +100,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];

42
components/soc/esp32c3/include/soc/efuse_reg.h
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@ -256,11 +256,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved (used for four backups method).*/
#define EFUSE_RPT4_RESERVED1 0x00000003
#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
#define EFUSE_RPT4_RESERVED1_V 0x3
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: Secure version (used by ESP-IDF anti-rollback feature).*/
@ -609,11 +615,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1 0x00000003
#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
#define EFUSE_RPT4_RESERVED1_V 0x3
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: The value of SECURE_VERSION.*/
@ -1561,11 +1573,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_ERR_S 0
#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE_ERR (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_V 0x1
#define EFUSE_ERR_RST_ENABLE_ERR_S 31
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1_ERR 0x00000003
#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x3
#define EFUSE_RPT4_RESERVED1_ERR (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x1
#define EFUSE_RPT4_RESERVED1_ERR_S 30
/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/

9
components/soc/esp32c3/include/soc/efuse_struct.h
View File

@ -75,7 +75,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7: 5; /*Reserved (used for four backups method).*/
uint32_t force_send_resume: 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
uint32_t secure_version: 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/
uint32_t rpt4_reserved1: 2; /*Reserved (used for four backups method).*/
uint32_t rpt4_reserved1: 1; /*Reserved (used for four backups method).*/
uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} pgm_data4;
@ -156,7 +157,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7: 5; /*Reserved.*/
uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/
uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/
uint32_t rpt4_reserved1: 2; /*Reserved.*/
uint32_t rpt4_reserved1: 1; /*Reserved.*/
uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_data3;
@ -323,7 +325,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7_err: 5; /*Reserved*/
uint32_t force_send_resume_err: 1; /*If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/
uint32_t secure_version_err: 16; /*If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/
uint32_t rpt4_reserved1_err: 2; /*Reserved.*/
uint32_t rpt4_reserved1_err: 1; /*Reserved.*/
uint32_t err_rst_enable_err: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_err3;

44
components/soc/esp32s3/include/soc/efuse_reg.h
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@ -429,18 +429,18 @@ apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3C)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Reserved (used for four backups method)..*/
#define EFUSE_RPT4_RESERVED1 (BIT(31))
#define EFUSE_RPT4_RESERVED1_M (BIT(31))
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved (used for four backups method).*/
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 31
/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set this bit to enable power glitch function..*/
#define EFUSE_POWERGLITCH_EN (BIT(30))
#define EFUSE_POWERGLITCH_EN_M (BIT(30))
#define EFUSE_POWERGLITCH_EN_V 0x1
#define EFUSE_POWERGLITCH_EN_S 30
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: Secure version (used by ESP-IDF anti-rollback feature)..*/
#define EFUSE_SECURE_VERSION 0x0000FFFF
@ -1473,18 +1473,18 @@ apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/
#define EFUSE_KEY_PURPOSE_2_ERR_S 0
#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Reserved..*/
#define EFUSE_RPT4_RESERVED1_ERR (BIT(31))
#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(31))
/* EFUSE_ERR_RST_ENABLE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE_ERR (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_V 0x1
#define EFUSE_ERR_RST_ENABLE_ERR_S 31
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1_ERR (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x1
#define EFUSE_RPT4_RESERVED1_ERR_S 31
/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define EFUSE_POWERGLITCH_EN_ERR (BIT(30))
#define EFUSE_POWERGLITCH_EN_ERR_M (BIT(30))
#define EFUSE_POWERGLITCH_EN_ERR_V 0x1
#define EFUSE_POWERGLITCH_EN_ERR_S 30
#define EFUSE_RPT4_RESERVED1_ERR_S 30
/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: If any bits in this filed are 1, then it indicates a programming error..*/
#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF

22
components/soc/esp32s3/include/soc/efuse_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EFUSE_STRUCT_H_
#define _SOC_EFUSE_STRUCT_H_
@ -113,8 +105,8 @@ typedef volatile struct efuse_dev_s {
uint32_t reg_flash_ecc_en : 1; /*Set 1 to enable ECC for flash boot.*/
uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
uint32_t reg_secure_version : 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/
uint32_t reg_powerglitch_en : 1; /*Set this bit to enable power glitch function.*/
uint32_t reg_rpt4_reserved1 : 1; /*Reserved (used for four backups method).*/
uint32_t reg_err_rst_enable : 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_data3;
@ -295,8 +287,8 @@ typedef volatile struct efuse_dev_s {
uint32_t reg_flash_ecc_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_force_send_resume_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_version_err : 16; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_powerglitch_en_err : 1;
uint32_t reg_rpt4_reserved1_err : 1; /*Reserved.*/
uint32_t reg_err_rst_enable_err : 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_err3;

1
tools/ci/check_copyright_ignore.txt
View File

@ -1622,7 +1622,6 @@ components/soc/esp32s3/include/soc/clkout_channel.h
components/soc/esp32s3/include/soc/cpu.h
components/soc/esp32s3/include/soc/cpu_caps.h
components/soc/esp32s3/include/soc/dport_access.h
components/soc/esp32s3/include/soc/efuse_struct.h
components/soc/esp32s3/include/soc/extmem_reg.h
components/soc/esp32s3/include/soc/extmem_struct.h
components/soc/esp32s3/include/soc/fe_reg.h