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Merge b7f95afe77 into 46acfdce96

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andste82 2024-09-26 11:42:34 +08:00 committed by GitHub
commit 6c3232f874
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GPG Key ID: B5690EEEBB952194
3 changed files with 8 additions and 8 deletions
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2
components/esp_hw_support/port/esp32/esp_clk_tree.c
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@ -55,7 +55,7 @@ uint32_t *freq_value)
clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision); clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
break; break;
case SOC_MOD_CLK_REF_TICK: case SOC_MOD_CLK_REF_TICK:
clk_src_freq = 1 * MHZ; clk_src_freq = REF_CLK_FREQ;
break; break;
case SOC_MOD_CLK_APLL: case SOC_MOD_CLK_APLL:
clk_src_freq = clk_hal_apll_get_freq_hz(); clk_src_freq = clk_hal_apll_get_freq_hz();

2
components/esp_hw_support/port/esp32s2/esp_clk_tree.c
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@ -53,7 +53,7 @@ uint32_t *freq_value)
clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision); clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision);
break; break;
case SOC_MOD_CLK_REF_TICK: case SOC_MOD_CLK_REF_TICK:
clk_src_freq = 1 * MHZ; clk_src_freq = REF_CLK_FREQ;
break; break;
case SOC_MOD_CLK_APLL: case SOC_MOD_CLK_APLL:
clk_src_freq = clk_hal_apll_get_freq_hz(); clk_src_freq = clk_hal_apll_get_freq_hz();

12
components/hal/esp32/include/hal/clk_tree_ll.h
View File

@ -669,31 +669,31 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider_fro
} }
/** /**
* @brief Set REF_TICK divider to make REF_TICK frequency at 1MHz * @brief Set REF_TICK divider to make REF_TICK frequency at REF_CLK_FREQ
* *
* @param cpu_clk_src Selected CPU clock source (one of soc_cpu_clk_src_t values) * @param cpu_clk_src Selected CPU clock source (one of soc_cpu_clk_src_t values)
* @param cpu_freq_mhz CPU frequency value, in MHz * @param cpu_freq_mhz CPU frequency value, in MHz
* *
* Divider = APB_CLK freq in Hz / 1MHz. Value in register = divider - 1. * Divider = APB_CLK freq in Hz / (REF_CLK_FREQ / MHZ). Value in register = divider - 1.
*/ */
static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(soc_cpu_clk_src_t cpu_clk_src, uint32_t cpu_freq_mhz) static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(soc_cpu_clk_src_t cpu_clk_src, uint32_t cpu_freq_mhz)
{ {
uint32_t apb_freq_mhz; uint32_t apb_freq_mhz;
switch (cpu_clk_src) { switch (cpu_clk_src) {
case SOC_CPU_CLK_SRC_XTAL: case SOC_CPU_CLK_SRC_XTAL:
apb_freq_mhz = cpu_freq_mhz; apb_freq_mhz = cpu_freq_mhz / (REF_CLK_FREQ / MHZ);
REG_WRITE(SYSCON_XTAL_TICK_CONF_REG, apb_freq_mhz - 1); REG_WRITE(SYSCON_XTAL_TICK_CONF_REG, apb_freq_mhz - 1);
break; break;
case SOC_CPU_CLK_SRC_PLL: case SOC_CPU_CLK_SRC_PLL:
apb_freq_mhz = 80; apb_freq_mhz = 80 / (REF_CLK_FREQ / MHZ);
REG_WRITE(SYSCON_PLL_TICK_CONF_REG, apb_freq_mhz - 1); REG_WRITE(SYSCON_PLL_TICK_CONF_REG, apb_freq_mhz - 1);
break; break;
case SOC_CPU_CLK_SRC_RC_FAST: case SOC_CPU_CLK_SRC_RC_FAST:
apb_freq_mhz = cpu_freq_mhz; apb_freq_mhz = cpu_freq_mhz / (REF_CLK_FREQ / MHZ);
REG_WRITE(SYSCON_CK8M_TICK_CONF_REG, apb_freq_mhz - 1); REG_WRITE(SYSCON_CK8M_TICK_CONF_REG, apb_freq_mhz - 1);
break; break;
case SOC_CPU_CLK_SRC_APLL: case SOC_CPU_CLK_SRC_APLL:
apb_freq_mhz = cpu_freq_mhz >> 1; apb_freq_mhz = (cpu_freq_mhz / (REF_CLK_FREQ / MHZ)) >> 1;
REG_WRITE(SYSCON_APLL_TICK_CONF_REG, apb_freq_mhz - 1); REG_WRITE(SYSCON_APLL_TICK_CONF_REG, apb_freq_mhz - 1);
break; break;
default: default: