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https://github.com/espressif/esp-idf.git
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fix reg operation missing
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@ -1 +1 @@
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Subproject commit 0f68ece75cd27b71def68b735e6a03db312a46c5
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Subproject commit 30a3ab11c441630e3e76fbf30212e546db377e8e
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@ -30,7 +30,7 @@ extern "C" {
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#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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//write value to register
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#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE(_r, _v)
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#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
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//read value from register
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static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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@ -97,7 +97,7 @@ static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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}
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//write value to register
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#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG(addr, val)
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#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
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//clear bits of register controlled by mask
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#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
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@ -112,7 +112,7 @@ static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
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//set bits of register controlled by mask and shift
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#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg),(DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))
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#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
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//get field of register
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#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
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@ -142,14 +142,14 @@
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//write value to register
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#define REG_WRITE(_r, _v) ({ \
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ASSERT_IF_DPORT_REG(_r, REG_WRITE); \
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ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
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(*(volatile uint32_t *)(_r)) = (_v); \
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})
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//read value from register
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#define REG_READ(_r) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_READ); \
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(*(volatile uint32_t *)_r); \
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(*(volatile uint32_t *)(_r)); \
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})
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//get bit or get bits from register
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